CN117608135A

CN117608135A - Array substrate, display panel and display device

Info

Publication number: CN117608135A
Application number: CN202311616964.4A
Authority: CN
Inventors: 张春旭; 戴珂; 杨海鹏; 周茂秀; 姜晓婷; 程敏
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Priority date: 2023-11-29
Filing date: 2023-11-29
Publication date: 2024-02-27

Abstract

The array substrate, the display panel and the display device comprise a substrate; a plurality of pixel electrodes arranged in an array on the substrate; the pixel electrode comprises a first main part and a plurality of branch parts, wherein the first main part extends along a first direction and is arranged close to the pixel electrode of the previous row, and the plurality of branch parts are positioned on one side of the first main part close to the pixel electrode of the next row and are obliquely arranged relative to the first main part; the first metal layer is positioned between the substrate and the layers where the plurality of pixel electrodes are positioned, the orthographic projection of the first metal layer on the substrate and the orthographic projection of the first trunk part on the substrate are not overlapped with each other, and the orthographic projection of the first metal layer on the substrate and the orthographic projection of the plurality of branch parts on the substrate are not overlapped with each other.

Description

Array substrate, display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

The thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation, portability, etc., has been rapidly developed in recent years, and has gradually replaced the conventional cathode ray tube display device (Cathode Ray Tube display, CRT), and has taken the dominant role in the current flat panel display market. At present, TFT-LCDs are widely used in various large, medium and small-sized products, and almost cover the main electronic products of the current information society, such as liquid crystal televisions, high definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigators, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and illusive displays.

Disclosure of Invention

The embodiment of the disclosure provides an array substrate, a display panel and a display device, which are used for solving the problem of low transmittance of display products in the prior art.

The embodiment of the disclosure provides an array substrate, a display panel and a display device, and the specific scheme is as follows:

in one aspect, an embodiment of the present disclosure provides an array substrate, including:

a substrate base;

a plurality of pixel electrodes arranged in an array on the substrate; the pixel electrode comprises a first main part and a plurality of branch parts, the first main part extends along a first direction and is arranged close to the pixel electrode of the previous row, and the plurality of branch parts are positioned on one side of the first main part close to the pixel electrode of the next row and are obliquely arranged relative to the first main part;

the first metal layer is positioned between the substrate and the layers where the pixel electrodes are positioned, the orthographic projection of the first metal layer on the substrate and the orthographic projection of the first trunk part on the substrate are not overlapped, and the orthographic projection of the first metal layer on the substrate and the orthographic projection of the branch parts on the substrate are not overlapped.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the pixel electrode includes a second trunk portion extending along the first direction and located in a middle region of the pixel electrode;

the first metal layer comprises a first floating electrode, and the orthographic projection of the first floating electrode on the substrate is positioned in the orthographic projection of the second trunk part on the substrate.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a first transfer electrode is further included between the first metal layer and the layers where the plurality of pixel electrodes are located, the first transfer electrode is coupled to the pixel electrodes, and a front projection of the first transfer electrode on the substrate is located in a front projection of the first floating electrode on the substrate.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the pixel electrode further includes a third trunk portion extending along the second direction and located in a middle region of the pixel electrode;

the first metal layer further comprises a second floating electrode, and the orthographic projection of the second floating electrode on the substrate is located in the orthographic projection of the third trunk part on the substrate.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the array substrate further includes a second switching electrode integrally provided with the first switching electrode, and a front projection of the second switching electrode on the substrate is located in a front projection of the second floating electrode on the substrate.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, a connection electrode integrally provided with the pixel electrode is further included, the connection electrode includes a first overlapping portion, the first metal layer further includes a third floating electrode, and an orthographic projection of the first overlapping portion on the substrate is located in an orthographic projection of the third floating electrode on the substrate.

In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a transistor is further included, a first pole of the transistor is coupled between the connection electrode and the first switching electrode, and the first pole of the transistor includes a second overlapping portion, and an orthographic projection of the second overlapping portion on the substrate is located within an orthographic projection of the first overlapping portion on the substrate.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the array substrate further includes a plurality of data lines arranged along the first direction and extending along the second direction, one of the data lines being coupled to a portion of the pixel electrodes arranged in the same row along the second direction;

The first metal layer further comprises a shielding electrode, and the orthographic projection of the shielding electrode on the substrate is positioned between the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the data line adjacent to the pixel electrode and insulated from each other on the substrate.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the data line includes a data portion between adjacent pixel electrodes arranged along the first direction;

the array substrate further comprises a common electrode line which is arranged at the gap of the pixel electrode, is in the same layer with the pixel electrode and is arranged with the same material, and the orthographic projection of the common electrode line on the substrate covers the orthographic projection of the data line outside the data part on the substrate.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, a plurality of gate lines extending in the first direction and arranged in the second direction are further included, the gate lines including gate line portions between adjacent pixel electrodes arranged in the second direction;

the common electrode line comprises a common electrode part which is positioned on the side where the grid electrode of the transistor is positioned and extends along the second direction, and the orthographic projection of the common electrode part on the substrate base plate covers the orthographic projection of the grid line outside the grid line part on the substrate base plate.

In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the array substrate further includes a transistor, where a gate of the transistor is located in an area surrounded by the data line, the gate line, and the pixel electrode;

the orthographic projection of the common electrode line on the substrate covers the orthographic projection of the edge of the gate electrode of the transistor, which is close to the pixel electrode, on the substrate.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a plurality of data lines are further included, the plurality of data lines being arranged along the first direction and extending along the second direction;

the pixel electrodes are positioned at gaps between adjacent data lines, each m (m is an integer greater than or equal to 3) of the pixel electrodes arranged along the second direction are contained in one pixel, and the light emitting colors of each m of the pixel electrodes arranged along the second direction are different;

in the same row of the pixels arranged along the second direction, at least part of adjacent pixel electrodes are coupled with the same side of the data lines.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, at least one pixel arranged in the second direction is a repeating unit, the pixel electrode of the same repeating unit is coupled to the same data line, and the pixel electrode of an adjacent repeating unit is coupled to a different data line.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the repeating unit includes one or two of the pixels.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the pixel includes a first pixel electrode, a second pixel electrode, and a third pixel electrode;

in the same row of pixels arranged along the second direction, the first pixel electrode of each pixel is coupled with the data line on one side of the row of pixels, the second pixel electrode of each pixel is coupled with the data line on the other side of the row of pixels, and two third pixel electrodes of two adjacent pixels are respectively coupled with the data lines on two sides of the row of pixels.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, a size of the pixel electrode in the first direction is larger than a size of the pixel electrode in the second direction.

On the other hand, based on the same inventive concept, the embodiment of the present disclosure provides a display panel, which includes an array substrate and a counter substrate that are opposite to each other, wherein the array substrate is the above-mentioned array substrate provided by the embodiment of the present disclosure.

In some embodiments, in the display panel provided by the embodiments of the present disclosure, the opposite substrate includes a black matrix, and the array substrate includes a third floating electrode, and an orthographic projection of the third floating electrode on the substrate is located within an orthographic projection of the black matrix on the substrate.

On the other hand, based on the same inventive concept, the embodiments of the present disclosure provide a display device including the above display panel provided by the embodiments of the present disclosure.

The beneficial effects of the present disclosure are as follows:

the array substrate, the display panel and the display device provided by the embodiment of the disclosure comprise a substrate; a plurality of pixel electrodes arranged in an array on the substrate; the pixel electrode comprises a first main part and a plurality of branch parts, wherein the first main part extends along a first direction and is arranged close to the pixel electrode of the previous row, and the plurality of branch parts are positioned on one side of the first main part close to the pixel electrode of the next row and are obliquely arranged relative to the first main part; the first metal layer is positioned between the substrate and the layers where the plurality of pixel electrodes are positioned, the orthographic projection of the first metal layer on the substrate and the orthographic projection of the first trunk part on the substrate are not overlapped with each other, and the orthographic projection of the first metal layer on the substrate and the orthographic projection of the plurality of branch parts on the substrate are not overlapped with each other. By arranging the first metal layer, the first main part and the plurality of branch parts of the pixel electrode are not overlapped with each other, the influence of the first metal layer on the transmittance is reduced, and the transmittance is improved.

Drawings

FIG. 1 is a schematic diagram of a sub-pixel region of an array substrate;

fig. 2 is a schematic structural diagram of a region where two sub-pixels of an array substrate are located according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of the gate line layer in FIG. 2;

FIG. 4 is a schematic diagram of the structure of the active layer in FIG. 2;

FIG. 5 is a schematic diagram of a layer of the data line in FIG. 2;

FIG. 6 is a schematic view of the structure of the layer in which the via hole is formed in FIG. 2;

FIG. 7 is a schematic diagram of a layer of the pixel electrode in FIG. 2;

fig. 8 is a schematic structural diagram of a region where two sub-pixels of an array substrate are located according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram of the gate line layer in FIG. 8;

fig. 10 is a schematic structural diagram of a region where a sub-pixel of an array substrate provided in an embodiment of the disclosure is located;

FIG. 11 is a schematic diagram of a layer of the data line in FIG. 10;

FIG. 12 is a schematic cross-sectional view taken along line I-II of FIG. 10;

FIG. 13 is a schematic diagram of a tri-gate pixel architecture;

FIG. 14 is a signal waveform diagram of the first and last data lines of FIG. 13;

FIG. 15 is a signal waveform diagram of the first and last data lines of FIG. 13 except for the other data lines;

fig. 16 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure;

Fig. 17 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure;

fig. 18 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure;

fig. 19 is a schematic structural diagram of a region where one sub-pixel in the display panel according to an embodiment of the disclosure is located;

FIG. 20 is a schematic cross-sectional view taken along line III-IV of FIG. 19;

fig. 21 is a schematic structural diagram of a display device according to an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It is noted that in the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described in this disclosure with reference to cross-sectional views that are schematic illustrations of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing techniques and/or tolerances, will be expected. Thus, the embodiments described in this disclosure should not be construed as limited to the particular shapes of regions as illustrated in this disclosure but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat may typically have rough and/or nonlinear features; the sharp corners illustrated may be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their sizes and shapes are not intended to illustrate the precise shape of a region and are not to reflect an actual scale, so as to merely schematically illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed description of known functions and known components.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.

In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on, connected to, or intervening elements or layers may be present. When an element or layer is referred to as being "disposed on" a side of another element or layer, it can be directly on the side of the other element or layer, be directly connected to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. The term "and/or" includes any and all combinations of one or more of the associated listed items.

Fig. 1 is a schematic structural diagram of a region where one sub-pixel of an array substrate is located in the related art. As shown in fig. 1, in the region where the sub-pixel is located, the first metal layer (M1) includes a common electrode line (CL) and a Gate Line (GL), and the first metal layer (M1) may be made of a light-impermeable metal material; the common electrode line (CL) is intersected with the first main part (Px 1) and the plurality of branch parts (Px 2) of the pixel electrode (PX), so that the common electrode line (CL) can shade part of light, reduce light transmittance and influence display brightness. The display brightness can be improved by increasing the backlight brightness, but the power consumption is increased, and the development trend and the requirement of low power consumption cannot be met. Therefore, how to improve the transmittance of the product is a technical problem that needs to be solved by those skilled in the art.

In order to improve the above technical problems in the related art, an embodiment of the present disclosure provides an array substrate, and an exemplary schematic structural diagram of a region where two sub-pixels are located in the array substrate is shown in fig. 2, and as can be seen from fig. 2, the array substrate of the present disclosure includes:

a substrate 101, wherein the substrate 101 may be a substrate that allows visible light to pass through, for example, glass, quartz, plastic, or the like;

A plurality of pixel electrodes 102 arranged in an array on the substrate 101, optionally, the size of the pixel electrodes 102 in the first direction X is larger than the size of the pixel electrodes 102 in the second direction Y; the pixel electrode 102 includes a first trunk portion 1021 and a plurality of branch portions 1022, the first trunk portion 1021 extending along the first direction X and being disposed adjacent to the previous row of pixel electrodes 102, the plurality of branch portions 1022 being disposed on a side of the first trunk portion 1021 adjacent to the next row of pixel electrodes 102 and being disposed obliquely with respect to the first trunk portion 1021; alternatively, the pixel electrode 102 is non-closed at four corners, and at the left side of the pixel electrode 102, the partial branch parts 1022 are disconnected from each other; the material of the pixel electrode 102 includes at least one transparent conductive material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), aluminum Zinc Oxide (AZO), gallium Zinc Oxide (GZO);

the first metal layer M1 is located between the substrate 101 and the layers where the plurality of pixel electrodes 102 are located, the orthographic projection of the first metal layer M1 on the substrate 101 and the orthographic projection of the first trunk 1021 on the substrate 101 do not overlap each other, and the orthographic projection of the first metal layer M1 on the substrate 101 and the orthographic projection of the plurality of branches 1022 on the substrate 101 do not overlap each other; in some embodiments, the first metal layer M1 may include a metal material of molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), or the like.

Fig. 1 is a schematic structural diagram of a region where one sub-pixel of a wiring substrate is located in the related art, and fig. 2 is a schematic structural diagram of a region where two sub-pixels of an array substrate are located in the related art. As can be seen from comparing fig. 1 and 2, the present disclosure provides that the first metal layer M1 and the first trunk portion 1021 and the plurality of branch portions 1022 do not overlap each other, which is equivalent to removing the common electrode line (CL) overlapping the first trunk portion 1021 and the plurality of branch portions 1022 in the first metal layer M1 in the related art, thereby reducing the influence of the first metal layer M1 on the transmittance, and thus improving the transmittance. The actual aperture ratio of the pixel is exemplified by 55 inch 4k pixels, which can be improved by about 2.4%.

With continued reference to fig. 2 and 7, the common electrode line 103 is disposed on the layer where the pixel electrode 102 is disposed in the present disclosure, which will be described in detail later. It is easy to understand that, in the case where the gap between adjacent pixel electrodes 102 is large, the present disclosure may also keep the common electrode line 103 in the first metal layer M1, and set the common electrode line 103 at the gap of the pixel electrode 102, while shielding the common electrode line 103 with the Black Matrix (BM) of the opposite substrate, at this time, the common electrode line 103 may play a role of improving the signal uniformity of the common electrode.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, as shown in fig. 2, 3 and 7, the pixel electrode 102 may further include a second trunk portion 1023 extending along the first direction X and located in a middle area of the pixel electrode 102, the second trunk portion 1023 being connected to the plurality of branch portions 1022, and extending directions of the plurality of branch portions 1022 on both sides of the second trunk portion 1023 being different; the first metal layer M1 comprises a first floating electrode 104, the front projection of the first floating electrode 104 on the substrate 101 being located within the front projection of the second stem on the 1023 substrate 101. The floating electrode in this disclosure is an electrode that is not loaded with an electrical signal.

As can be seen from fig. 2 and 7, the extending directions of the plurality of branch portions 1022 on both sides of the second trunk portion 1023 are different, and may be that the plurality of branch portions 1022 extend toward the upper right in the upper right region Q1 of the second trunk portion 1023; in the upper left region Q2 of the second trunk 1023, a plurality of branch parts 1022 extend toward the upper left; in the lower left region Q3 of the second trunk 1023, a plurality of branch parts 1022 extend downward to the left; in the lower right region Q4 of the second trunk 1023, the plurality of branch portions 1022 extend downward toward the right. In the same region (for example, the upper right region Q1, the upper left region Q2, the lower left region Q3, or the lower right region Q4), the extending direction of the slit between the adjacent branch portions 1022 is the same as the extending direction of the branch portions 1022, and the liquid crystal molecules in the same region are orderly arranged under the slit direction control. The liquid crystal molecules at the second trunk 1023 are simultaneously controlled by the slit direction of the upper left region Q2 and the slit direction of the lower left region Q3, and by the slit direction of the upper right region Q1 and the slit direction of the lower right region Q4. The different directions of the slits in the different regions may cause disorder of the ordering of the liquid crystal molecules at the second trunk portion 1023 to appear dark fringes.

The present disclosure means that the first floating electrode 104 is disposed at the dark stripe region by disposing the first floating electrode 104 at the second trunk 1023, so that the first floating electrode 104 does not affect the transmittance; and, the first floating electrode 104 and the second trunk 1023 overlap each other to form a storage capacitor Cst, which is beneficial to effectively maintaining the voltage of the pixel electrode 102 until the next updated picture.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, as shown in fig. 2, 3 and 7, the pixel electrode 102 may further include a third trunk portion 1024 extending along the second direction Y and located in a middle area of the pixel electrode 102, the third trunk portion 1024 is integrally disposed with the plurality of branch portions 1022, and extension directions of the plurality of branch portions 1022 on both sides of the third trunk portion 1024 are different; the first metal layer M1 may further include a second floating electrode 105, where an orthographic projection of the second floating electrode 105 on the substrate 101 is located within an orthographic projection of the third trunk 1024 on the substrate 101; alternatively, the second floating electrode 105 is integrally provided with the first floating electrode 104.

As can be seen from fig. 2 and 7, the liquid crystal molecules at the third trunk 1024 are simultaneously controlled by the slit direction of the upper right region Q1 and the slit direction of the upper left region Q2, and by the slit direction of the lower left region Q3 and the slit direction of the lower right region Q4. The different directions of the slits in the different regions may cause disorder of the ordering of the liquid crystal molecules at the third trunk 1024 to appear dark lines.

The present disclosure means that the second floating electrode 105 is disposed at the dark stripe region by disposing the second floating electrode 105 at the third trunk 1024, and thus the second floating electrode 105 does not affect the transmittance; and, the second floating electrode 105 and the third trunk 1024 overlap each other to form a storage capacitor Cst, which is beneficial to effectively maintaining the voltage of the pixel electrode 102 until the next updated picture.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in fig. 2, 3 and 7, the array substrate may further include a connection electrode 106 integrally provided with the pixel electrode 102, where the connection electrode 106 is located on a side of the pixel electrode 102 near the data line 107 coupled to the pixel electrode 102, the connection electrode 106 includes a first overlapping portion 106', the first metal layer M1 further includes a third floating electrode 108, and a front projection of the first overlapping portion 106' on the substrate 101 is located in a front projection of the third floating electrode 108 on the substrate 101. Optionally, the third floating electrode 108 is integrally disposed with or disconnected from the first floating electrode 104, which is not specifically limited in this disclosure.

Since the region other than the pixel electrode 102 is a Black Matrix (BM) region, the connection electrode 106 and the third floating electrode 108 disposed on the side of the pixel electrode 102 near the data line 107 coupled to the pixel electrode 102 are located in the Black Matrix (BM) region, and thus the transmittance is not affected. In addition, the third floating electrode 108 and the connection electrode 106 overlap each other to form a storage capacitor Cst, which is advantageous in that the voltage of the pixel electrode 102 integrally provided with the connection electrode 106 is effectively maintained until the next refresh screen.

It should be noted that, to avoid the first floating electrode 104 and the second floating electrode 105 from affecting the transmittance, the present disclosure provides that the first floating electrode 104 is located in the area of the second trunk 1023, and the second floating electrode 105 is located in the area of the third trunk 1024. In view of the fact that the third floating electrode 108 is located in the Black Matrix (BM) region in the present disclosure, the transmittance is not affected, so, in order to ensure that the storage capacitance Cst between the connection electrode 106 and the third floating electrode 108 is large, the present disclosure provides that the orthographic projection of the first overlapping portion 106' of the connection electrode 106 on the substrate 101 is located within the orthographic projection of the third floating electrode 108 on the substrate 101.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in fig. 8 and 9, the first metal layer M1 may further include a shielding electrode 109, where the orthographic projection of the shielding electrode 109 on the substrate 101 is located between the orthographic projection of the pixel electrode 102 on the substrate 101 and the orthographic projection of the data line 107 (i.e. the right data line 107 in fig. 8) adjacent to the pixel electrode 102 and insulated from each other on the substrate 101. In this arrangement, the shielding electrode 109 can play a role in shielding the signal of the data line 107 (e.g., the right data line 107 in fig. 8) to avoid interference with the signal of the pixel electrode 102. Alternatively, the shielding electrode 109 is integrally provided with the first floating electrode 104, or the shielding electrode 109 is provided to be disconnected from the first floating electrode 104, which is not particularly limited in the present disclosure. With continued reference to fig. 8 and 9, it can be seen that the front projection of the shielding electrode 109 onto the substrate 101 at least partially overlaps with the front projection of the common electrode line 103 onto the substrate 101, optionally the front projection of the common electrode line 103 onto the substrate 101 covers the front projection of the shielding electrode 109 onto the substrate 101.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in fig. 10 to 12, a first switching electrode 110 located between the first metal layer M1 and the layers where the plurality of pixel electrodes 102 are located may be further included, where the first switching electrode 110 is coupled to the pixel electrode 102 and is disposed with a first electrode, a second electrode, and a same material of the transistor 111, and an orthographic projection of the first switching electrode 110 on the substrate 101 is located within an orthographic projection of the first floating electrode 104 on the substrate 101. As can be seen from fig. 12, there are a gate insulating layer 112, a passivation layer 113, a color resist layer 114 and a planarization layer 115 between the first metal layer M1 and the layer where the pixel electrode 102 is located, wherein the sum of the thicknesses of the color resist layer 114 and the planarization layer 115 is between 3 μm and 5 μm, and the thicknesses of the gate insulating layer 112 and the passivation layer 113 is between 0.4 μm and 0.6 μm. The first switching electrode 110 and the first floating electrode 104 only have the gate insulating layer 112 therebetween, so that a larger storage capacitance Cst is formed between the first switching electrode 110 and the first floating electrode 104. Therefore, in the case that the storage capacitance Cst between the first floating electrode 104, the second floating electrode 105, the third floating electrode 108 and the pixel electrode 102 of the first metal layer M1 is insufficient to well maintain the pixel voltage, the present disclosure can use the storage capacitance Cst formed by the first switching electrode 110 and the first floating electrode 104 to maintain the pixel voltage until the next frame of picture update.

For similar reasons for disposing the first switching electrode 110, as shown in fig. 10 and 11, in the above-mentioned array substrate provided in the embodiments of the present disclosure, a second switching electrode 116 integrally disposed with the first switching electrode 110 may also be disposed, where an orthographic projection of the second switching electrode 116 on the substrate 101 is located within an orthographic projection of the second floating electrode 105 on the substrate 101; in addition, a first pole s of the transistor 111 may be further arranged to be coupled between the connection electrode 106 and the first switching electrode 110, i.e. alternatively, the first pole s and the first switching electrode 110 may be electrically connected, the first pole s of the transistor comprising a second overlap s ', the orthographic projection of the second overlap s ' on the substrate 101 being located within the orthographic projection of the first overlap 106' of the connection electrode 106 on the substrate 101.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, as shown in fig. 2, 5 and 7, to improve the uniformity of the common electrode signal, the common electrode line 103 disposed on the same layer and material as the pixel electrode 102 may be disposed in a mesh structure at the gap of the pixel electrode 102; meanwhile, in order to shield the interference of the data line 107 on the pixel electrode 102 and to avoid the influence of the larger load of the data line 107 on the charging rate, the present disclosure may provide that the data line 107 includes a data portion 107' between adjacent pixel electrodes 102 arranged along the first direction X, and the orthographic projection of the common electrode line 103 on the substrate 101 covers the orthographic projection of the data line 107 outside the data portion 107' on the substrate 101, that is, the common electrode line 103 arranged in the same layer as the pixel electrode is arranged in a hollowed structure at the data portion 107 '.

In some embodiments, in order to shield the interference of the gate line 117 on the pixel electrode 102 and to avoid the influence of the larger load of the gate line 117 on the charging rate, as shown in fig. 2, 3 and 7, the present disclosure may provide that the gate line 117 includes a gate line portion 117' between adjacent pixel electrodes 102 arranged in the second direction Y, and the front projection of the common electrode line 103 on the substrate 101 covers the front projection of the gate line 117 on the substrate 101 except the gate line portion 117', that is, the common electrode line 103 arranged in the same layer as the pixel electrode is arranged in a hollowed structure at the gate line portion 117 '.

In other embodiments, in order to shield the interference of the gate electrode g of the transistor 111 on the pixel electrode 102, as shown in fig. 2, 3 and 7, the present disclosure provides that the common electrode line 103 includes a common electrode portion 103 'located on the side of the gate electrode g and extending along the second direction Y, and the orthographic projection of the common electrode portion 103' on the substrate 101 covers the orthographic projection of the gate electrode g of the transistor 111 on the substrate 101 near the edge of the pixel electrode 102. Of course, in some embodiments, the common electrode portion 103' may also have a certain distance from the gate electrode g. In addition, as can be seen from fig. 2, 5 and 7, there is a space between the common electrode part 103 'and the second overlapping part s' of the first pole s.

In some embodiments, as shown in fig. 4 and 5, a mask may be used to make a pattern on the active layer a of the transistor 111 and the layer on which the data line 107 is located, where the active layer a has a similar pattern to the data line 107 and the first and second poles s and d of the transistor 111. In a specific implementation, the semiconductor material layer of the active layer a may be coated first, then the metal material layer of the data line 107 is coated, and then the metal material layer is patterned by using one mask plate to form the data line 107, the first pole s and the second pole d of the transistor 111, and the active layer a is patterned on the semiconductor layer, so that the number of mask plates can be reduced, and the cost can be further reduced.

In some embodiments, the transistor 111 may be a p-type transistor or an n-type transistor, and the transistor 111 may be a bottom gate transistor, a top gate transistor, a double gate transistor, or the like, which is not limited herein. The first pole s of the transistor 111 may be a source, the second pole d may be a drain, or the first pole s of the transistor 111 may be a drain, and the second pole d may be a source in the present disclosure, which is not limited herein. The material of the active layer a of the transistor 111 may be amorphous silicon (a-Si), polysilicon (poly), oxide (Oxide, such as indium gallium zinc Oxide IGZO), or the like. Alternatively, as shown in fig. 5 to 7, the first electrode s of the transistor 111 may be coupled with the pixel electrode 102 through a via H penetrating the planarization layer 115, the color resist layer 114, and the passivation layer 113.

In some embodiments, the material of the gate insulating layer 112 and the passivation layer 113 may be at least one of inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc.; the material of the planarization layer 115 includes, but is not limited to, at least one of polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, urethane acrylate resin, novolac epoxy acryl resin. The color resist layer 114 may include red, green, blue, etc.

With the increasing severity of the market situation, the cost reduction of products has become a trend, and more display products are designed by using a three-gate (triple gate) pixel architecture. Fig. 13 is a schematic diagram of a tri-gate pixel architecture, as can be seen from fig. 13, the tri-gate pixel architecture includes a plurality of red sub-pixels R, a plurality of green sub-pixels G and a plurality of blue sub-pixels B, each pixel P includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, each row of sub-pixels is connected with a gate line 117, two adjacent sub-pixels of the same column of sub-pixels are respectively connected with data lines 107 on two sides, so that three gate lines 117 are provided in each pixel P to respectively control transistors 111 and a data line 107 of the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B to perform data signal writing. Compared with the scheme of controlling one row of sub-pixels by one data line 107, the tri-gate pixel architecture can reduce the number of data lines 107, thereby reducing the number of source driving chips for providing data signals to the data lines 107, which is beneficial to reducing the cost, and therefore, the industry is gradually invested in developing the tri-gate pixel architecture as a low-cost scheme.

In some embodiments, the circuit signal processing method of the tri-gate pixel structure shown in fig. 13 is to apply signals of a column of pixels to the left and right data lines 107 controlling the column of pixels, so as to implement control. For the first data line 107 and the last data line 107, signals are split only when the pixel connected thereto is displayed, and when the pixel not connected thereto is displayed, data signals are given to L0. Therefore, in the gray-scale screen, the waveforms of the first data line 107 and the last data line 107 are similar to those of fig. 14, and the other data lines 107 are at the constant high level as shown in fig. 15, or the other data lines 107 are at the low level.

For a product with an insufficient charging rate, each gate line 117 may be turned on for a multiple-line period such that the subpixels controlled by the current gate line 117 write data signals while precharging the subpixels of the next line, thereby increasing the charging rate. However, since the first data line 107 and the last data line 107 are connected to the data signal only when the sub-pixel controlled by the first data line 107 and the last data line 107 need to be displayed, the sub-pixels controlled by the first data line 107 and the last data line 107 are not precharged, and the charge rate is poor, so that the gray scale difference from other column sub-pixels is large, and edge jaggies occur.

In the display product of the three-grid pixel architecture, the first data line 107 and the last data line 107 respectively control the sub-pixels of three colors, namely the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B, and the brightness difference of the three colors is more easily captured by human eyes; meanwhile, the sub-pixels of the three-grid pixel architecture are long in the transverse direction, so that the brightness difference display is wider, and the edge jaggies are easier to observe.

Based on this, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 16 to 18, it may be provided that each m (m is an integer of 3 or more) of the pixel electrodes 102 arranged along the second direction Y are included in one pixel P, and the light emission color of each m of the pixel electrodes 102 arranged along the second direction Y is different; in the same row of pixels P arranged in the second direction Y, at least part of the adjacent pixel electrodes 102 are coupled with the same-side data line 107.

Since each gate line 117 is turned on for a plurality of rows of time periods, in the case where the adjacent pixel electrodes 102 are coupled to the same-side data line 107 in the present disclosure, the next one of the adjacent pixel electrodes 102 can be precharged while the first data line 107 and the last data line 107 load data signals for the previous one of the adjacent pixel electrodes 102, so that the difference in brightness of the light output of the next one of the adjacent pixel electrodes 102 from the other column pixel electrodes 102 is small or even no, and thus edge jaggies caused by the excessive difference in brightness between the first column and the last column of sub-pixels and the other column of sub-pixels can be effectively improved.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, as shown in fig. 16 and 17, at least one pixel P arranged in the second direction Y is a repeating unit RU, the pixel electrode 102 of the same repeating unit RU may be coupled to the same data line 107, and the pixel electrode 102 of an adjacent repeating unit RU is coupled to a different data line 107. According to the scheme, in the first column and the last column of sub-pixels, the sub-pixels with three colors of the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B are not pre-charged, and are changed into the red sub-pixel R, the brightness of the green sub-pixel G and the blue sub-pixel B is consistent with the signals controlled by other data lines 107, so that the problem of edge jaggy can be effectively solved.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the repeating unit RU may include one or two pixels P. Since the data signal controlled by each column is scattered into dots (dots) whether the inversion is performed with one pixel P or two pixels P, the problem of the shaking of the head is not generated while improving the edge jaggies.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, as shown in fig. 17, the pixel P includes a first pixel electrode 102a, a second pixel electrode 102b, and a third pixel electrode 102c; in the same row of pixels P arranged along the second direction Y, the first pixel electrode 102a of each pixel P is coupled to the data line 107 on one side (e.g., right side) of the row of pixels P, the second pixel electrode 102b of each pixel P is coupled to the data line 107 on the other side (e.g., left side) of the row of pixels P, and the two third pixel electrodes 102c of two adjacent pixels P are respectively coupled to the data lines 101 on both sides of the row of pixels P. This makes it possible to couple both the adjacent sub-pixel belonging to the same pixel P and the adjacent sub-pixel belonging to the adjacent pixel P to the same-side data line 107, so that edge aliasing can be effectively improved.

Specifically, in fig. 17, the first pixel electrode 102a belongs to the red sub-pixel R, the second pixel electrode 102B belongs to the green sub-pixel G, and the third pixel electrode 102c belongs to the blue pixel B, and the red sub-pixels R in the same column are all coupled to the right data line 107, the green sub-pixels G in the same column are all coupled to the left data line, and the blue sub-pixels B in the same column are alternately coupled to the left data line 107 and the right data line 107; under the scheme, only one color of the green sub-pixel G in the first column of sub-pixels is dark, and the edge sawtooth defect of the first column is obviously improved; in the last column of the sub-pixels, the red sub-pixel R is darker, the blue sub-pixel B has bright-dark change at intervals of one row, and compared with the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B, the three colors have bright-dark change, and the edge jaggies of the last column are also obviously improved. Meanwhile, the data signals are loaded by taking the sub-pixels as a unit instead of taking the columns as a unit, so that the occurrence probability of the shaking marks can be greatly reduced while the edge saw teeth are improved.

Of course, in some embodiments, it is also possible to arrange that the first pixel electrode 102a belongs to the green sub-pixel G, the second pixel electrode 102B belongs to the red sub-pixel R, the third pixel electrode 102c belongs to the blue sub-pixel B, and the same-column green sub-pixels G are all coupled to the right data line 107, the same-column red sub-pixels R are all coupled to the left data line, and the same-column blue sub-pixels B are alternately coupled to the left data line 107 and the right data line 107; or the first pixel electrode 102a belongs to the blue pixel B, the second pixel electrode 102B belongs to the green sub-pixel G, and the third pixel electrode 102c belongs to the red sub-pixel R, and the same-column blue sub-pixels B are all coupled to the right data line 107, the same-column green sub-pixels G are all coupled to the left data line, and the same-column red sub-pixels R are alternately coupled to the left data line 107 and the right data line 107, which is not limited herein.

Based on the same inventive concept, the embodiments of the present disclosure provide a display panel, as shown in fig. 19 and 20, including an array substrate 001 and a counter substrate 002 that are opposite to each other, where the array substrate 001 is the above-mentioned array substrate provided in the embodiments of the present disclosure. Since the principle of the display panel for solving the problems is similar to that of the array substrate, the implementation of the display panel can refer to the embodiment of the array substrate, and the repetition is omitted.

In some embodiments, in the above display panel provided in the embodiments of the present disclosure, as shown in fig. 19, the opposite substrate 002 includes a black matrix BM, and the orthographic projection of the third floating electrode 108 of the array substrate 001 on the substrate 101 is located within the orthographic projection of the black matrix BM on the substrate 101, so as to avoid the third floating electrode 108 from affecting the transmittance.

In some embodiments, in the above display panel provided in the embodiments of the present disclosure, as shown in fig. 20, the opposite substrate 002 may further include a common electrode layer 201 and a substrate 202, and the common electrode layer 201 may be disposed over the display area AA; in addition, a liquid crystal layer 003 may be disposed between the array substrate 001 and the opposite substrate 002, a first alignment layer may be disposed on a side of the array substrate 001 facing the opposite substrate 002, a first polarizer may be disposed on a side of the array substrate 001 away from the opposite substrate 002, a second alignment layer may be disposed on a side of the opposite substrate 002 away from the array substrate 001, a second polarizer may be disposed on a side of the opposite substrate 002 away from the array substrate 001, and a polarization direction of the first polarizer and a polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in fig. 21, including the above-mentioned display panel PNL provided in the embodiment of the present disclosure, and a backlight module BLU located on a light incident side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side-in type backlight module. Alternatively, the side-entry backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, and the like, which are stacked, and the light bar is located at one side of the light guide plate in the thickness direction of the light guide plate. The direct type backlight module can comprise a matrix light source, a reflecting sheet, a diffusion plate, a brightness enhancement film and the like, wherein the reflecting sheet, the diffusion plate, the brightness enhancement film and the like are arranged on the light emitting side of the matrix light source in a stacked mode, and the reflecting sheet comprises an opening which is opposite to the position of each lamp bead in the matrix light source. The beads in the light bar, the beads in the matrix light source, may be Light Emitting Devices (LEDs), such as quantum dot light emitting devices (QLEDs), micro light emitting devices (e.g., mini LEDs, micro LEDs), etc.

Among them, micro light emitting devices of sub-millimeter level and even of micrometer level belong to self-luminous devices like Organic Light Emitting Devices (OLEDs). It has a series of advantages of high brightness, ultra low delay, ultra large visible angle, etc. as the organic light emitting device. And because the inorganic luminescent device emits light based on a metal semiconductor with more stable property and lower resistance, the inorganic luminescent device has the advantages of lower power consumption, higher high temperature and low temperature resistance and longer service life compared with an organic luminescent device which emits light based on an organic substance. And when the miniature light-emitting device is used as a backlight source, a more precise dynamic backlight effect can be realized, the glare phenomenon caused between the bright and dark areas of the screen by the traditional dynamic backlight can be solved while the brightness and the contrast of the screen are effectively improved, and the visual experience is optimized.

In some embodiments, the display device provided by the embodiments of the present disclosure may be: projectors, 3D printers, virtual reality devices, cell phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigators, smartwatches, fitness bracelets, personal digital assistants, and any other product or component having a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to: the system comprises a radio frequency unit, a network module, an audio output and input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), or the like. For example, the control chip may further include a memory, a power module, and the like, and realize power supply and signal input/output functions through wires, signal lines, and the like that are additionally provided. For example, the control chip may also include hardware circuitry, computer-executable code, and the like. The hardware circuitry may include conventional Very Large Scale Integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components; the hardware circuitry may also include field programmable gate arrays, programmable array logic, programmable logic devices, or the like. In addition, it will be understood by those skilled in the art that the above structures do not constitute limitations of the above display device provided by the embodiments of the present disclosure, in other words, more or fewer components described above may be included in the above display device provided by the embodiments of the present disclosure, or certain components may be combined, or different arrangements of components may be provided.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims

1. An array substrate, characterized by comprising:

a substrate base;

2. The array substrate of claim 1, wherein the pixel electrode includes a second trunk portion extending in the first direction and located in a middle region of the pixel electrode;

3. The array substrate of claim 2, further comprising a first transfer electrode between the first metal layer and the layer of the plurality of pixel electrodes, the first transfer electrode coupled to the pixel electrode, and an orthographic projection of the first transfer electrode on the substrate within an orthographic projection of the first floating electrode on the substrate.

4. The array substrate of claim 3, wherein the pixel electrode further comprises a third trunk portion extending in the second direction and located at a middle region of the pixel electrode;

5. The array substrate of claim 4, further comprising a second transfer electrode integrally disposed with the first transfer electrode, an orthographic projection of the second transfer electrode on the substrate being within an orthographic projection of the second floating electrode on the substrate.

6. The array substrate of claim 3, further comprising a connection electrode integrally provided with the pixel electrode, the connection electrode including a first overlap portion, the first metal layer further including a third floating electrode, an orthographic projection of the first overlap portion on the substrate being located within an orthographic projection of the third floating electrode on the substrate.

7. The array substrate of claim 6, further comprising a transistor having a first pole coupled between the connection electrode and the first transfer electrode, the first pole comprising a second overlap, an orthographic projection of the second overlap onto the substrate being within an orthographic projection of the first overlap onto the substrate.

8. The array substrate of any one of claims 1 to 7, further comprising a plurality of data lines arranged in the first direction and extending in the second direction, one of the data lines being coupled to a portion of the pixel electrodes arranged in the second direction in the same row;

9. The array substrate of claim 8, wherein the data line includes a data portion between adjacent pixel electrodes arranged along the first direction;

10. The array substrate of claim 9, further comprising a plurality of gate lines extending in the first direction and arranged in the second direction, the gate lines including gate line portions between adjacent pixel electrodes arranged in the second direction;

the orthographic projection of the common electrode line on the substrate base plate covers the orthographic projection of the grid line outside the grid line part on the substrate base plate.

11. The array substrate of claim 10, further comprising a transistor, wherein a gate electrode of the transistor is located in an area surrounded by the data line, the gate line, and the pixel electrode;

the common electrode line comprises a common electrode part which is positioned on the side where the grid electrode of the transistor is positioned and extends along the second direction, and the orthographic projection of the common electrode part on the substrate base plate covers the orthographic projection of the grid electrode of the transistor, which is close to the edge of the pixel electrode, on the substrate base plate.

12. The array substrate of any one of claims 1 to 7, 9 to 11, further comprising a plurality of data lines arranged along the first direction and extending along the second direction;

13. The array substrate of claim 12, wherein at least one pixel arranged in the second direction is a repeating unit, the pixel electrode of the same repeating unit is coupled to the same data line, and the pixel electrode of an adjacent repeating unit is coupled to a different data line.

14. The array substrate of claim 13, wherein the repeating unit includes one or two of the pixels.

15. The array substrate of claim 12, wherein the pixel includes a first pixel electrode, a second pixel electrode, and a third pixel electrode;

16. The array substrate of claim 12, wherein a size of the pixel electrode in the first direction is greater than a size of the pixel electrode in the second direction.

17. A display panel comprising an array substrate and a counter substrate disposed opposite to each other, wherein the array substrate is an array substrate according to any one of claims 1 to 16.

18. The display panel of claim 17, wherein the counter substrate comprises a black matrix, the array substrate comprises a third floating electrode, and an orthographic projection of the third floating electrode on the substrate is located within an orthographic projection of the black matrix on the substrate.

19. A display device comprising the display panel according to claim 17 or 18.