CN115016185B

CN115016185B - Display panel and preparation method thereof

Info

Publication number: CN115016185B
Application number: CN202210683240.0A
Authority: CN
Inventors: 马涛; 艾飞
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2022-06-16
Filing date: 2022-06-16
Publication date: 2024-01-30
Anticipated expiration: 2042-06-16
Also published as: CN115016185A

Abstract

The application provides a display panel and a preparation method of the display panel, wherein the display panel comprises an array substrate and a color resistance layer which are oppositely arranged; the array substrate at least comprises a first thin film transistor, a first pixel electrode electrically connected with the first thin film transistor, a second thin film transistor and a second pixel electrode electrically connected with the second thin film transistor, wherein the first pixel electrode corresponds to a first sub-pixel area, and the second pixel electrode corresponds to a second sub-pixel area; the array substrate is provided with a scanning line and a first data line, and the first thin film transistor and the second thin film transistor are respectively and electrically connected with the scanning line and the first data line; the color resistance layer at least comprises a first color resistance block and a transparent color resistance block, wherein the first color resistance block corresponds to the first sub-pixel area, the transparent color resistance block corresponds to the second sub-pixel area, and the color of the first color resistance block is red, green or blue. The display panel can improve the light transmittance and further improve the brightness.

Description

Display panel and preparation method thereof

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a preparation method of the display panel.

Background

The display panel is an important component of the display device. When the display panel is a liquid crystal display panel, the structure of the liquid crystal display panel is generally composed of a Color Filter (CF), a thin film transistor array substrate (Thin FilmTransistor Array Substrate, TFT Array Substrate) and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates, and the operating principle is that the rotation of liquid crystal molecules of the liquid crystal layer is controlled by applying a driving voltage to the two substrates, so that light provided by the backlight module is refracted out and finally passes through the Color Filter to obtain an image. When the display panel is an organic light-emitting display panel, the organic light-emitting display panel comprises a flexible substrate, a thin film transistor layer, an anode layer, a light-emitting layer, a cathode layer and a color resistance layer which are sequentially laminated, and light rays emitted by the light-emitting layer pass through the color resistance layer to obtain images.

The conventional display panel has a plurality of pixel units arranged in a matrix, and each pixel unit includes three sub-pixel units of Red (Red, R), green (Green, G), and Blue (B). The formation of the sub-pixel units of different colors is formed by providing color resists of corresponding colors on the color resist layer. In the prior art, R, G, B color resistors arranged on the color resistor layer are all absorption type color resistors. When light is incident, only light of the corresponding color can be transmitted, and light of the other two colors is absorbed, so that the light transmittance of the display panel is low and the brightness is insufficient.

Disclosure of Invention

The embodiment of the application provides a display panel and a preparation method of the display panel, which can improve the light transmittance of the display panel and further improve the brightness of the display panel.

The embodiment of the application provides a display panel, which comprises:

the array substrate and the color resistance layer are oppositely arranged;

the array substrate at least comprises a first thin film transistor, a first pixel electrode electrically connected with the first thin film transistor, a second thin film transistor and a second pixel electrode electrically connected with the second thin film transistor, wherein the first pixel electrode corresponds to a first sub-pixel area, and the second pixel electrode corresponds to a second sub-pixel area;

the array substrate is provided with a scanning line and a first data line, and the first thin film transistor and the second thin film transistor are respectively and electrically connected with the scanning line and the first data line;

the color resistance layer at least comprises a first color resistance block and a transparent color resistance block, the first color resistance block corresponds to the first sub-pixel area, the color of the first color resistance block is red, green or blue, and the transparent color resistance block corresponds to the second sub-pixel area.

In some embodiments, the second thin film transistor is disposed on the first thin film transistor, the first thin film transistor is a top gate thin film transistor, the second thin film transistor is a bottom gate thin film transistor, and the gate of the first thin film transistor and the gate of the second thin film transistor are the same gate.

In some embodiments, the first sub-pixel region has the same area as the second sub-pixel region

In some embodiments, the array substrate further includes a third thin film transistor, a third pixel electrode electrically connected to the third thin film transistor, a fourth thin film transistor, and a fourth pixel electrode electrically connected to the fourth thin film transistor, the third pixel electrode corresponding to a third sub-pixel region; the fourth pixel electrode corresponds to a fourth sub-pixel area;

the array substrate is also provided with a second data line;

the color resistance layer further comprises a second color resistance block and a third color resistance block, the second color resistance block corresponds to the third sub-pixel area, and the third color resistance block corresponds to the fourth sub-pixel area;

the third thin film transistor and the fourth thin film transistor are electrically connected with the scanning line and the second data line respectively.

In some embodiments, the second color block is the same color as the third color block, the second color block being red, blue, or green.

In some embodiments, the second color blocker is red, blue, or green in color; the third color block is a transparent color block.

In some embodiments, the data line includes a first sub data line and a second sub data line, the first thin film transistor is connected to the first sub data line, and the second thin film transistor is connected to the second sub data line.

The embodiment of the application also provides a preparation method of the display panel, which comprises the following steps:

providing a first thin film transistor;

forming a first pixel electrode on the first thin film transistor, wherein the first pixel electrode corresponds to a first sub-pixel area;

providing a second thin film transistor;

forming a second pixel electrode on the second thin film transistor, wherein the second pixel electrode corresponds to a second sub-pixel region;

providing a scanning line and a first data line;

connecting the first thin film transistor and the second thin film transistor to the scanning line, and connecting the first thin film transistor and the second thin film transistor to the first data line to form an array substrate;

forming a color resistance layer on the array substrate;

or providing a color resistance layer, and arranging the color resistance layer and the array substrate in a box-to-box manner;

In some embodiments, the providing a first thin film transistor includes providing a substrate base plate; disposing a first active layer on the substrate base plate; forming a first source electrode and a first drain electrode at two ends of the first active layer respectively;

after forming the first pixel electrode on the first drain electrode, the providing the first thin film transistor further includes forming a first gate insulating layer on the first active layer, the first source electrode, and the first drain electrode; forming a gate electrode on the first gate insulating layer;

the providing a second thin film transistor includes: forming the second gate insulating layer on the gate electrode; forming a second active layer on the second gate insulating layer, and forming a second source electrode and a second drain electrode at both ends of the second active layer, respectively; wherein the gate is common to the first thin film transistor and the second thin film transistor.

In some embodiments, electrically connecting the first source and the second source to the first data line includes: forming a through hole on the first gate insulating layer and the second gate insulating layer; a conductor is arranged in the through hole; electrically connecting two ends of the conductor with the first source electrode and the second source electrode respectively; the first source electrode or the second source electrode is electrically connected to the first data line.

The display panel and the preparation method of the display panel provided by the embodiment of the application are characterized in that the display panel is provided with a first thin film transistor and a first pixel electrode electrically connected with the first thin film transistor, and the first pixel electrode corresponds to a first sub-pixel area; the first pixel electrode corresponds to the first sub-pixel region. Since the first thin film transistor and the second thin film transistor are electrically connected to the scan line, the first thin film transistor and the second thin film transistor are electrically connected to the first data line, the scan line and the first data line can control the first pixel electrode and the second pixel electrode together, i.e. the first pixel electrode and the second pixel electrode can be charged or discharged simultaneously. Therefore, when the first sub-pixel area is lightened, the second sub-pixel area is correspondingly lightened, and the transparent color block corresponds to the second sub-pixel area due to the first sub-pixel area corresponding to the first color block, so that the light transmittance of the display panel can be further increased by the transparent color block, and the brightness of the display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a type of an RGBW pixel unit in the related art.

Fig. 2 is a schematic diagram of a first structure of a display panel according to an embodiment of the present application.

Fig. 3 is a schematic diagram of a second structure of the display panel according to the embodiment of the present application.

Fig. 4 is a schematic side view of a first side view of an array substrate according to an embodiment of the present application.

Fig. 5 is a schematic top view of a first schematic structure of an array substrate according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a third structure of a display panel according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a fourth structure of a display panel according to an embodiment of the present application.

Fig. 8 is a schematic top view of a second type of an array substrate according to an embodiment of the present application.

Fig. 9 is a schematic view of a fifth structure of a display panel according to an embodiment of the present application.

Fig. 10 is a schematic view of a sixth structure of a display panel according to an embodiment of the present application.

Fig. 11 is a schematic view of a seventh structure of a display panel according to an embodiment of the present application.

Fig. 12 is a schematic top view of a third top view of an array substrate according to an embodiment of the present application.

Fig. 13 is a schematic view of an eighth structure of a display panel according to an embodiment of the present application.

Fig. 14 is a schematic view of a ninth structure of a display panel according to an embodiment of the present application.

Fig. 15 is a schematic top view of a fourth top view of an array substrate according to an embodiment of the present application.

Fig. 16 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application.

Fig. 17 is a schematic diagram of a first process flow of the display panel according to the embodiment of the present application.

Fig. 18 is a schematic diagram of a second process flow of the display panel according to the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

With the rapid development of display technology, the size of display devices is increasing, and the frequency of driving circuits is also increasing, so that thin film transistors with higher mobility are required to operate. The mobility refers to the average drift velocity of carriers (electrons and holes) under the action of a unit electric field, namely the velocity of carriers moving under the action of the electric field. The faster the carriers move, the greater the mobility; the slower the carriers move, the smaller the mobility. The mobility of the existing amorphous silicon thin film transistor cannot meet the requirement of a large-sized display device.

Therefore, polysilicon thin film transistors and metal oxide thin film transistors having high mobility are widely paid attention to, and metal oxide semiconductor thin film transistors (Thin Film Transistor, TFT), such as IGZO (Indium Gallium Zinc Oxide ) thin film transistors, are widely used in display devices because of their high mobility, transparency, simple manufacturing process, and the like. In addition, low temperature polysilicon (LTPS, low Temperature Poly-Silicon) technology is widely used in liquid crystal displays (Liquid Crystal Display, LCD) and organic light emitting displays (AMOLED, active Matrix/Organic Light Emitting Diode) with its mature process and high mobility.

The display panel is an important component of an LCD display device. For LCDs, a liquid crystal display panel is generally composed of a color resist layer, a thin film transistor array substrate, and a liquid crystal layer disposed between the two substrates, and the operating principle is to control the rotation of liquid crystal molecules of the liquid crystal layer by applying a driving voltage to the two glass substrates, so as to refract light provided by the backlight module to generate an image. When the display panel is an organic light-emitting display panel, the organic light-emitting display panel comprises a flexible substrate, a thin film transistor layer, an anode layer, a light-emitting layer, a cathode layer and a color resistance layer which are sequentially laminated, and light rays emitted by the light-emitting layer pass through the color resistance layer to obtain images.

The conventional liquid crystal display panel has a plurality of pixels arranged in a matrix, and each pixel includes three sub-pixels of Red (Red, R), green (Green, G), and Blue (B). Because the R, G, B color filters adopted in the prior art are all absorption type color resistance layers, when light rays are incident, only light with corresponding colors can be transmitted, and light with other two colors is absorbed, so that the light transmittance of the display panel is lower and the brightness is insufficient.

In this regard, an RGBW technique is proposed, in which White (W) sub-pixels are added to the original RGB three primary colors, and a four-color pixel design is adopted, which is a sub pixel rendering technique. Wherein, the light group layer corresponding to the white sub-pixel is transparent photoresistance, and the light transmittance can reach more than 99%. The white sub-pixel is added, so that the light transmittance of the display is greatly improved. Consistency of color appearance in the new pixel arrangement. Meanwhile, the light transmittance of the liquid crystal panel is greatly improved, and the power consumption is lower when the pictures with the same brightness are displayed; under the same power consumption, the brightness is greatly improved, so that the display device displays more distinct layers of pictures and more transparent pictures. Referring to fig. 1, fig. 1 is a schematic diagram of an RGBW pixel unit in the related art. The first sub-pixel unit 20 is a red sub-pixel unit, the second sub-pixel unit 40 is a green sub-pixel unit, the third sub-pixel unit 60 is a blue sub-pixel unit, and the fourth sub-pixel unit 80 is a white sub-pixel unit. Common RGBW pixel units can be classified into stripe RGBW as in fig. 1 (a), pentile RGBW as in fig. 1 (b), and special RGBW as in fig. 1 (c).

Therefore, the RGBW technology is adopted to solve the problems of insufficient brightness and excessive power consumption of the high-resolution screen to a certain extent. Of course, this display technology ensures that the total number of pixels is unchanged at the same resolution, but the number of sub-pixels occupied by each of the three colors red, green and blue is changed from one third of the RGB technology to one fourth of the present day.

The display device adopting the RGBW technology solves the problems of low brightness and high energy consumption, and the display device screen adopting the RGBW technology reduces about 35 percent of energy consumption and improves about 50 percent of brightness compared with the display device screen adopting the RGB technology under the same brightness.

Therefore, the RGBW technology is to add a white sub-pixel unit to the original RGB technology, and becomes a four-color pixel unit design. And the light transmittance of the display panel is greatly improved in a new pixel arrangement mode. When the pictures with the same brightness are displayed, the power consumption is lower (the power consumption of the needed backlight is lower); and under the condition of the same power consumption, the brightness is greatly improved, so that the picture level is more clear.

The application provides a display panel and a preparation method of the display panel, which can improve the light transmittance of the display panel and improve the brightness of the display panel. The following description is made in detail with reference to the accompanying drawings.

The application provides a display panel 10, wherein the display panel 10 comprises an array substrate 100 and a color resistance layer 200 which are oppositely arranged. Referring to fig. 2, fig. 2 is a schematic diagram of a first structure of a display panel according to an embodiment of the disclosure. When the display panel 10 is a liquid crystal display panel, the display panel 10 further includes a liquid crystal layer 300 disposed between the array substrate 100 and the color resist layer 200. Among them, the liquid crystal display panel has many advantages of thin body, power saving, no radiation, etc., and has been widely used, such as liquid crystal televisions, mobile phones, personal Digital Assistants (PDAs), digital cameras, computer screens or notebook computer screens, etc. Referring to fig. 3, fig. 3 is a schematic diagram of a second structure of the display panel according to the embodiment of the present application. When the display panel 10 is an organic light emitting display panel, the display panel 10 further includes a light emitting layer disposed between the array substrate 100 and the color resist layer 200. The organic light-emitting display panel is a device which has high brightness, full viewing angle, high response speed and flexible display.

The array substrate 100 may have a plurality of sub-pixel areas, which are in one-to-one correspondence with the sub-pixel areas, and the color block layer 200 is provided with a plurality of color blocks having different colors or transparent color blocks, so that the light emitted through the color block layer 200 has a plurality of colors.

Referring to fig. 4 and fig. 5, fig. 4 is a schematic side view structure of an array substrate according to an embodiment of the present application, and fig. 5 is a schematic top view structure of an array substrate according to an embodiment of the present application. The array substrate 100 at least includes a first thin film transistor 105, a first pixel electrode 106 connected to the first thin film transistor 105, a second thin film transistor 107, and a second pixel electrode 108 connected to the second thin film transistor 107, wherein the first pixel electrode 106 corresponds to the first sub-pixel region 103, and the second pixel electrode 108 corresponds to the second sub-pixel region 104. The array substrate 100 is provided with a scan line 101 and a first data line 102, and the first thin film transistor 105 and the second thin film transistor 107 are electrically connected to the scan line 101 and the first data line 102, respectively. Optionally, the scan line 101 and the first data line 102 are perpendicular to each other, and the regular line arrangement can avoid shielding the light by the lines. Referring to fig. 6, fig. 6 is a schematic diagram of a third structure of a display panel according to an embodiment of the disclosure. Fig. 7 is a disassembled plan view of fig. 6. The color block layer 200 at least includes a first color block 201 and a transparent color block 202, the first color block 201 corresponds to the first sub-pixel region 103, the transparent color block 202 corresponds to the second sub-pixel region 104, and the color of the first color block 201 is red, green or blue.

Specifically, the first thin film transistor 105 includes a first source electrode 1051, a first drain electrode 1052, and a first gate electrode 1053, and the first drain electrode 1052 is electrically connected to the first pixel electrode 106. Specifically, the second thin film transistor 107 includes a second source 1071, a second drain 1072, and a second gate 1073, and the second drain 1072 is electrically connected to the second pixel electrode 108.

The first thin film transistor 105 and the second thin film transistor 107 are electrically connected to the scan line 101, and the first thin film transistor 105 and the second thin film transistor 107 are connected to the first data line 102. Specifically, the first gate 1053 and the second gate 1073 are electrically connected to the scan line 101, and the first source 1051 and the second source 1071 are electrically connected to the first data line 102. Alternatively, the first gate 1053 and the second gate 1073 may be electrically connected to the scan line 101, or the first gate 1053 and the second gate 1073 may be electrically connected to the scan line 101 after the first gate 1053 and the second gate 1073 are electrically connected. Alternatively, the first source electrode 1051 and the second source electrode 1071 may be electrically connected to the first data line 102, or the first source electrode 1051 and the second source electrode 1071 may be electrically connected to the first data line 102 after the first source electrode 1051 and the second source electrode 1071 are electrically connected.

Since the first gate electrode 1053 and the second gate electrode 1073 are electrically connected to the scan line 101, and the first source electrode 1051 and the second source electrode 1071 are connected to the first data line 102, the scan line 101 and the first data line 102 can commonly control the first pixel electrode 106 and the second pixel electrode 108, i.e. the first pixel electrode 106 and the second pixel electrode 108 can be charged or discharged simultaneously. The second sub-pixel area 104 is also lit accordingly when the first sub-pixel area 103 is lit. The first color block 201 corresponds to the first sub-pixel region 103, and the transparent color block 202 corresponds to the second sub-pixel region 104. The transparent color block 202 may further increase the light transmittance of the display panel 10, so that the brightness of the display panel 10 is improved. For example, when the first color block 201 is red, that is, when the first subpixel area 103 and the second subpixel area 104 are simultaneously turned on, one red subpixel and one white subpixel are simultaneously present on the display panel 10.

The display panel 10 provided in the embodiment of the present application is provided with a first thin film transistor 105 and a first pixel electrode 106 electrically connected to the first thin film transistor 105, where the first pixel electrode 106 corresponds to the first sub-pixel region 103; a second thin film transistor 107 and a second pixel electrode 108 electrically connected to the second thin film transistor, wherein the second pixel electrode 108 corresponds to the second sub-pixel region 104. Since the first thin film transistor 105 and the second thin film transistor 107 are electrically connected to the scan line 101, and the thin film transistor 107 and the second thin film transistor 107 are connected to the first data line 102, the scan line 101 and the first data line 102 can commonly control the first pixel electrode 106 and the second pixel electrode 108, i.e., the first pixel electrode 106 and the second pixel electrode 108 can be charged or discharged at the same time. Therefore, when the first sub-pixel region 103 is turned on, the second sub-pixel region 104 is also turned on, and the transparent color block 202 corresponds to the second sub-pixel region 104 due to the first sub-pixel region 103 corresponding to the first color block, the transparent color block 202 can further increase the light transmittance of the display panel 10, so that the brightness of the display panel 10 is improved.

TABLE 1

	L(cd/m ² )	CIE-x	CIE-y
				White sub-pixel unit	478.65	0.2969	0.3167
Black sub-pixel unit	0.3617	0.2547	0.2494
				Red sub-pixel unit	99.178	0.6565	0.3356
Green sub-pixel unit	337.45	0.2888	0.6528
				Blue sub-pixel unit	39.786	0.1495	0.0572

By the image color forming principle, the light emitted by the white sub-pixel unit can be regarded as superposition of a certain number of equal amount of red, green and blue sub-pixels, and the transmittance of white is about 3 times that of other colors, so that the transmittance of the display panel 10 can be increased by increasing the white sub-pixel unit, which is beneficial to the reduction of the power consumption of the display panel 10. The same illumination intensity lights the sub-pixel units with different colors, so that the brightness of the light passing through the corresponding sub-pixel units can be obtained. As can be seen from Table 1, the brightness of the light corresponding to the white sub-pixel unit is 478.65cd/m ² Further description of the addition of white sub-pixel elements may increase the light transmittance of the display panel 10 over sub-pixel elements of other colors, which is advantageous for reducing the power consumption of the display panel 10.

In some embodiments, the first active layer 1055 and the second active layer 1075 may be Oxide (Oxide), low Temperature Polysilicon (LTPS), amorphous Silicon, oxide (LTPS), or LTPS, respectively. The LTPS has high mobility and is suitable for application of high refresh frequency and high PPI; the Oxide has low leakage rate, is beneficial to the performance of devices under low frequency, and reduces the power consumption.

In some embodiments, the area of the first sub-pixel region 103 may be the same as or different from the area of the second sub-pixel region 104. Optionally, the ratio of the area of the first sub-pixel region 103 to the area of the second sub-pixel region 104 is 1:1 or 2:1. It can be understood that the smaller the ratio, the greater the light transmittance of the display panel 10; the larger the ratio, the smaller the transmittance of the display panel 10. When the area of the first sub-pixel region 103 and the area of the second sub-pixel region are 1:1, the display panel 10 can satisfy the better light transmittance, and the generated color is not distorted or color deviation is not generated.

In some embodiments, the second thin film transistor 107 is disposed on the first thin film transistor 105, the first thin film transistor 105 is a top gate thin film transistor, the second thin film transistor 107 is a bottom gate thin film transistor, and the first gate 1053 and the second gate 1073 are the same gate.

With continued reference to fig. 4, fig. 6, and fig. 7, fig. 7 is a schematic diagram of a fourth structure of the display panel according to the embodiment of the present application. Fig. 7 is a disassembled plan view of fig. 6. The top gate thin film transistor includes a first substrate 1054, a first active layer 1055, first source and drain electrodes 1051 and 1052 spaced apart from each other, a first gate insulating layer 1056 and a first gate electrode 1053, the first active layer 1055 being disposed on the first substrate 1054, the first source and drain electrodes 1051 and 1052 being connected to both ends of the first active layer 1055, respectively, and the first gate insulating layer 1056 covering the first active layer 1055, the first source electrode 1051 and the first drain electrode 1052.

The bottom gate thin film transistor includes a second substrate 1074, a second active layer 1075, a second source 1071 and a second drain 1072 spaced apart from each other, a second gate insulating layer 1076 and a second gate 1073, the second gate insulating layer 1076 is disposed on the second gate 1073, the second active layer 1075 is disposed on the second gate insulating layer 1076, and the second source 1071 and the second drain 1072 are connected to two ends of the second active layer 1075, respectively.

It is to be understood that when the second thin film transistor 107 is disposed on the first thin film transistor 105, the first gate 1053 and the second gate 1073 may be located on the same plane. The first gate electrode 1053 and the second gate electrode 1073 may be connected by a wire, and the first gate electrode 1053 and the second gate electrode 1073 may be a common gate electrode, that is, the common gate electrode may be used for the first thin film transistor 105 or the second thin film transistor 107. In the prior art, one gate corresponds to one thin film transistor, and in the embodiment of the present application, one gate corresponds to two thin film transistors, so that one gate is reduced, occupation of space can be reduced, and process steps can be reduced. In addition, the first thin film transistor 105 and the second thin film transistor 107 are stacked, which can reduce the occupied space of the array substrate 100 and is more beneficial to the miniaturization of the display panel 10.

In some embodiments, please refer to fig. 8, fig. 8 is a schematic diagram illustrating a second top view structure of the array substrate according to an embodiment of the present application. The array substrate 100 further includes a third thin film transistor 112, a third pixel electrode electrically connected to the third thin film transistor 112, a fourth thin film transistor 114, and a fourth pixel electrode electrically connected to the fourth thin film transistor 114, wherein the third pixel electrode corresponds to the third sub-pixel region 110, and the fourth pixel electrode corresponds to the fourth sub-pixel region 111.

The array substrate 100 is further provided with a second data line 109. Optionally, the second data line 109 is parallel to the first data line 102. The color resist layer 200 further includes a second color resist block 203 and a third color resist block 204, wherein the second color resist block 203 corresponds to the third sub-pixel region 110, and the third color resist block 204 corresponds to the fourth sub-pixel region 111.

Specifically, the third thin film transistor 112 includes a third source electrode 1121, a third drain electrode 1122, and a third gate electrode 1123, and the third drain electrode 1122 is electrically connected to the third pixel electrode. The fourth thin film transistor 114 includes a fourth source 1141, a fourth drain 1142, and a fourth gate 1143, and the fourth drain 1142 is electrically connected to the fourth pixel electrode.

Wherein, the third thin film transistor 112 and the fourth thin film transistor 114 are electrically connected to the scan line 101, and the third thin film transistor 112 and the fourth thin film transistor 114 are connected to the second data line 109. Specifically, the third gate electrode 1123 and the fourth gate electrode 1143 are electrically connected to the scan line 101, and the third source electrode 1121 and the fourth source electrode 1141 are electrically connected to the second data line 109. Alternatively, the third gate electrode 1123 and the fourth gate electrode 1143 may be electrically connected to the scan line 101, or the fourth gate electrode 1143 may be electrically connected to the scan line 101 after the third gate electrode 1123 is electrically connected to the fourth gate electrode 1143, or the third gate electrode 1123 may be electrically connected to the scan line 101 after the third gate electrode 1123 is electrically connected to the fourth gate electrode 1143. Alternatively, the third source electrode 1121 and the third source electrode 1121 may be electrically connected to the second data line 109, or the third source electrode 1121 may be electrically connected to the second data line 109 after the third source electrode 1121 is electrically connected to the third source electrode 1121.

Since the third gate electrode 1123 and the fourth gate electrode 1143 are electrically connected to the scan line 101, and the third source electrode 1121 and the fourth source electrode 1141 are connected to the second data line 109, the scan line 101 and the second data line 109 can commonly control the third pixel electrode and the fourth pixel electrode, i.e., the third pixel electrode and the fourth pixel electrode can be charged or discharged at the same time. The fourth sub-pixel area 111 is also lit accordingly when the third sub-pixel area 110 is lit. Since the scan line 101 commonly controls the first sub-pixel region 103, the second sub-pixel region 104, the third sub-pixel region 110 and the fourth sub-pixel region 111, the first sub-pixel region 103 and the second sub-pixel region 104, the third sub-pixel region 110 and the fourth sub-pixel region 111 exhibit different brightness changes due to different signals input to the first data line 102 and the second data line 109, and the color resist layer 200 is added, so that the display panel 10 exhibits rich color changes.

In some embodiments, the fourth thin film transistor 114 is disposed on the third thin film transistor 112, the third thin film transistor 112 is a top gate thin film transistor, the fourth thin film transistor 114 is a bottom gate thin film transistor, and the third gate 1123 and the fourth gate 1143 are the same gate.

In some embodiments, the second color blocker 203 is the same color as the third color blocker 204, and the second color blocker 203 is red, green, or blue.

Optionally, the color of the second color block 203 is the same as the color of the first color block 201, for example, the color of the first color block 201 is blue, and the color of the second color block 203 and the color of the third color block 204 are also blue, so that the first sub-pixel area 103, the third sub-pixel area 110 and the fourth sub-pixel area 111 are blue sub-pixel areas, and the second sub-pixel area 104 is a white sub-pixel area.

Optionally, the color of the second color block 203 is different from the color of the first color block 201, for example, the color of the first color block 201 is red, and the color of the second color block 203 and the third color block 204 is green or blue; for example, referring to fig. 9, fig. 9 is a schematic diagram of a fifth structure of the display panel provided in the embodiment of the present application, the color of the first color block 201 is blue, the color of the second color block 203 and the color of the third color block 204 are green, so that the first sub-pixel area 103 is a blue sub-pixel area, the second sub-pixel area 104 is a white sub-pixel area, and the third sub-pixel area 110 and the fourth sub-pixel area 111 are all green sub-pixel areas.

In some embodiments, the second color blocker 203 is different from the third color blocker 204, the second color blocker 203 being red, blue or green in color; the third color block 204 is a transparent color block 202. In some cases, referring to fig. 10, fig. 10 is a schematic view of a sixth structure of a display panel according to an embodiment of the disclosure. The third sub-pixel region 110 is adjacent to the first sub-pixel region 103, the fourth sub-pixel region 111 is adjacent to the second sub-pixel region 104, for example, the first color block 201 is blue, the second color block 203 is green, the third color block 204 is the transparent block 202, so that the first sub-pixel region 103 is a blue sub-pixel region, the second sub-pixel region 104 is a white sub-pixel region, the third sub-pixel region 110 is a green sub-pixel region and the fourth sub-pixel region 111 is a white sub-pixel region; in other cases, referring to fig. 11, fig. 11 is a schematic view of a seventh structure of a display panel according to an embodiment of the disclosure. The fourth sub-pixel region 111 is adjacent to the first sub-pixel region 103, and the third sub-pixel region 110 is adjacent to the second sub-pixel region 104. For example, the first color block 201 is red, the second color block 203 is green, and the third color block 204 is a transparent block 202, so that the first sub-pixel region 103 is a blue sub-pixel region, the second sub-pixel region 104 is a white sub-pixel region, the third sub-pixel region 110 is a green sub-pixel region, and the fourth sub-pixel region 111 is a white sub-pixel region.

In some embodiments, referring to fig. 12, fig. 12 is a schematic top view of a third top view of an array substrate according to an embodiment of the present application. The array substrate 100 further includes a fifth thin film transistor 119, a fifth pixel electrode electrically connected to the fifth thin film transistor 119, a sixth thin film transistor 121, and a sixth pixel electrode electrically connected to the sixth thin film transistor 121, wherein the fifth pixel electrode corresponds to the fifth sub-pixel region 117, and the sixth pixel electrode corresponds to the sixth sub-pixel region 118.

The array substrate 100 is further provided with a third data line 116. Optionally, the third data line 116 is parallel to the first data line 102 and the second data line 109. The color resist layer 200 further includes a fourth color resist block 205 and a fifth color resist block 206, wherein the fourth color resist block 205 corresponds to the fifth sub-pixel region 117, and the fifth color resist block 206 corresponds to the sixth sub-pixel region 118.

Specifically, the fifth thin film transistor 119 includes a fifth source electrode 1191, a fifth drain electrode 1192, and a fifth gate electrode 1193, the fifth drain electrode 1192 is electrically connected to a fifth pixel electrode, and the sixth subpixel region 118 is provided with a sixth thin film transistor 121 and a sixth pixel electrode connected to the sixth thin film transistor 121. Specifically, the sixth thin film transistor 121 includes a sixth source electrode 1211, a sixth drain electrode 1212, and a sixth gate electrode 1213, and the sixth drain electrode 1212 is electrically connected to the sixth pixel electrode.

Wherein, the fifth thin film transistor 119 and the sixth thin film transistor 121 are electrically connected to the scan line 101; the fifth thin film transistor 119 and the sixth thin film transistor 121 are connected to the third data line 116. Specifically, the fifth gate 1193 and the sixth gate 1213 are electrically connected to the scan line 101, and the fifth source 1191 and the sixth source 1211 are electrically connected to the third data line 116. Alternatively, the fifth gate 1193 and the sixth gate 1213 may be electrically connected to the scan line 101, or the sixth gate 1213 may be electrically connected to the scan line 101 after the fifth gate 1193 is electrically connected to the sixth gate 1213, or the fifth gate 1193 may be electrically connected to the scan line 101 after the fifth gate 1193 is electrically connected to the sixth gate 1213. Optionally, the fifth source 1191 and the fifth source 1191 may be electrically connected to the third data line 116, or the fifth source 1191 may be electrically connected to the third data line 116 after the fifth source 1191 is electrically connected to the fifth source 1191.

In some embodiments, the sixth thin film transistor 121 is disposed on the fifth thin film transistor 119, the fifth thin film transistor 119 is a top gate thin film transistor, the sixth thin film transistor 121 is a bottom gate thin film transistor, and the fifth gate 1193 and the sixth gate 1213 are the same gate.

Since the fifth gate electrode 1193 and the sixth gate electrode 1213 are electrically connected to the scan line 101, and the fifth source electrode 1191 and the sixth source electrode 1211 are connected to the third data line 116, the scan line 101 and the third data line 116 can commonly control the fifth pixel electrode and the sixth pixel electrode, i.e. the fifth pixel electrode and the sixth pixel electrode can be charged or discharged simultaneously. The sixth sub-pixel area 118 is also lit accordingly when the fifth sub-pixel area 117 is lit. Since the scan line 101 commonly controls the first sub-pixel region 103, the second sub-pixel region 104, the third sub-pixel region 110, the fourth sub-pixel region 111, the fifth sub-pixel region 117 and the sixth sub-pixel region 118, the first sub-pixel region 103 and the second sub-pixel region 104, the third sub-pixel region 110 and the fourth sub-pixel region 111, the fifth sub-pixel region 117 and the sixth sub-pixel region 118 exhibit different light and shade changes due to different signals input to the first data line 102, the second data line 109 and the third data line 116, and the color resist layer 200 is added, so that the display panel 10 exhibits rich color changes.

Hereinafter, the first sub-pixel region 103, the third sub-pixel region 110, and the fifth sub-pixel region 117 are sequentially located at one side of the scan line 101, and the second sub-pixel region 104, the fourth sub-pixel region 111, and the sixth sub-pixel region 118 are sequentially located at the other side of the scan line 101 will be described as an example. The first sub-pixel region 103, the third sub-pixel region 110, and the fifth sub-pixel region 117 are arranged along the first direction, and the second sub-pixel region 104, the fourth sub-pixel region 111, and the sixth sub-pixel region 118 are also arranged along the first direction. The first sub-pixel region 103 and the second sub-pixel region 104 are arranged along the second direction, the third sub-pixel region 110 and the fourth sub-pixel region 111 are arranged along the second direction, and the third sub-pixel region 110 and the fourth sub-pixel region 111 are also arranged along the second direction.

In order to achieve the purposes of reasonable layout and space saving, the first sub-pixel area 103, the third sub-pixel area 110 and the fifth sub-pixel area 117 are sequentially located at one side of the scan line 101, and the second sub-pixel area 104, the fourth sub-pixel area 111 and the sixth sub-pixel area 118 are sequentially located at the other side of the scan line 101; the first sub-pixel region 103 and the second sub-pixel region 104 are located on the same side of the first data line 102, the third sub-pixel region 110 and the fourth sub-pixel region 111 are located on the same side of the third data line 116, and the fifth sub-pixel region 117 and the sixth sub-pixel region 118 are located on the same side of the third data line 116.

The first color block 201 of the color resist layer 200 corresponds to the first sub-pixel region 103, the transparent color block 202 corresponds to the second sub-pixel region 104, the second color block 203 corresponds to the third sub-pixel region 110, the third color block 204 corresponds to the fourth sub-pixel region 111, the fourth color block 205 corresponds to the fifth sub-pixel region 117, and the fifth region corresponds to the sixth sub-pixel region 118.

In some embodiments, the fourth color blocker 205 is the same color as the fifth color blocker 206, and the fourth color blocker 205 is red, green, or blue. Optionally, the color of the fourth color block 205 is the same as the color of the second color block 203 and the color of the first color block 201, for example, the color of the first color block 201 is blue, and the color of the second color block 203 and the color of the fourth color block 205 are also blue, so that the first sub-pixel area 103, the third sub-pixel area 110 and the fifth sub-pixel area 117 are all blue sub-pixel areas, and the second sub-pixel area 104 is white. Optionally, the color of the fourth color block 205 is different from the color of the second color block 203 and the color of the first color block 201, for example, referring to fig. 13, fig. 13 is a schematic diagram of an eighth structure of the display panel provided in the embodiment of the present application, the color of the first color block 201 is blue, the color of the second color block 203 is green, the color of the fourth color block 205 is red, so that the first sub-pixel area 103 is blue, the third sub-pixel area 110 is green, and the fifth sub-pixel area 117 is red, and the second sub-pixel area 104 is white. If the color of the third color block 204 is the same as the color of the second color block 203, the color of the fifth color block 206 is the same as the color of the fourth color block 205, the color of the third color block is green, the color of the fifth color block is red, such that the first sub-pixel region 103 is blue, the third sub-pixel region 110 is green, and the fifth sub-pixel region 117 is red, the second sub-pixel region 104 is white, the fourth sub-pixel region 111 is green, and the sixth sub-pixel region 118 is red.

It is understood that mixing red, green, and blue light in a proportion can form white light. In the above-described embodiment, by setting the colors of the respective color blocks, the effect of RGBW is exhibited to enhance the light transmittance of the display panel 10.

In some embodiments, referring to fig. 14, fig. 14 is a schematic view of a ninth structure of a display panel according to an embodiment of the present application. The fourth color block 205 is different from the fifth color block 206, and the fourth color block 205 is red, blue or green; fifth color block 206 is transparent color block 202. For example, the first color block 201 is blue, the second color block 203 is green, and the fourth color block 205 is red. If the third color block 204 and the fifth color block 206 are transparent blocks 202, the first sub-pixel area 103 is blue, the third sub-pixel area 110 is green, and the fifth sub-pixel area 117 is red, and the second sub-pixel area 104, the fourth sub-pixel area 111, and the sixth sub-pixel area 118 are white. It is understood that the RGBW effect is also exhibited in the present embodiment, unlike the above, the color block of white in the present embodiment increases, and further, the transmittance of the display panel 10 increases.

In some embodiments, it may be desirable to increase the light transmittance of the blue subpixel element because there are fewer photoreceptor cells for the blue color in the human eye. Since the transparent block 202 corresponds to the second sub-pixel region 104 and the first block 201 corresponds to the first sub-pixel region 103, the first sub-pixel region 103 is a blue sub-pixel and the second sub-pixel region 104 is a white sub-pixel. When the blue sub-pixel is lightened, the white sub-pixel is correspondingly lightened, so that the light transmittance of the blue sub-pixel is further increased, and the white sub-pixel is convenient for human eyes to recognize.

In some embodiments, referring to fig. 15, fig. 15 is a schematic top view of a fourth top view of an array substrate according to an embodiment of the present application. The first data line 102 includes a first sub data line 1021 and a second sub data line 1022, the first source 1051 is connected to the first sub data line 1021, and the second source 1071 is connected to the second sub data line 1022. The first sub-data line 1021 and the second sub-data line 1022 respectively input different signals, so that the first sub-data line 1021 and the scanning line 101 control the first pixel electrode 106, the second sub-data line 1022 and the scanning line 101 control the second pixel electrode 108, the first sub-pixel region 103 and the second sub-pixel region 104 show different brightness changes, and the color resistance layer 200 is added, so that the display panel 10 shows rich color changes.

The application also provides a display device comprising the display panel 10. The display device can be a device with a display function such as a television, a computer, a mobile phone or a watch.

Referring to fig. 16 and 17, fig. 16 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application, and fig. 17 is a schematic flow chart of a first process of the display panel according to an embodiment of the present application.

The present application also provides a method for preparing the display panel 10, which can be used to prepare the display panel 10 in the above embodiment, and the method for preparing the display panel 10 is specifically as follows.

S1, providing a first thin film transistor 105.

S2, a first pixel electrode 106 is formed on the first thin film transistor 105, where the first pixel electrode 106 corresponds to the first sub-pixel area 103.

S3, providing a second thin film transistor 107.

S4, a second pixel electrode 108 is formed on the second thin film transistor 107, where the second pixel electrode 108 corresponds to the second sub-pixel region 104.

S5, providing a scanning line 101 and a data line.

S6, connecting the first thin film transistor 105 and the second thin film transistor 107 to the scan line 101, and connecting the first thin film transistor 105 and the second thin film transistor 107 to the data line, so as to form the array substrate 100.

S7, forming a color resistance layer 200 on the array substrate 100.

The step of forming the color resist layer 200 on the array substrate 100 may be replaced by providing a color resist layer 200, and arranging the color resist layer 200 and the array substrate 100 in a box-to-box manner.

It can be understood that the color resist layer 200 is formed on the array substrate 100 to prepare an organic display panel; a color resist layer 200 is provided, and the color resist layer 200 and the array substrate 100 are arranged in a box to prepare a liquid crystal display panel.

The color block 200 at least includes a first color block 201 and a transparent color block 202, the first color block 201 corresponds to the first sub-pixel region 103, the transparent color block 202 corresponds to the second sub-pixel region 104, and the color of the first color block 201 is red, green or blue.

In some embodiments, referring to fig. 18, fig. 18 is a schematic diagram of a second process flow of the display panel according to the embodiments of the present application. Wherein the step of providing the first thin film transistor 105 specifically comprises providing a substrate base plate; disposing a first active layer 1055 on a substrate base plate; a first source electrode 1051 and a first drain electrode 1052 are formed at both ends of the first active layer 1055, respectively.

After the step of forming the first pixel electrode 106 over the first drain electrode 1052, the step of providing the first thin film transistor 105 further includes forming a first gate insulating layer 1056 over the first active layer 1055, the first source electrode 1051, and the first drain electrode 1052; a gate electrode is formed on the first gate insulating layer 1056.

The step of providing the second thin film transistor 107 specifically includes forming a second gate insulating layer 1076 on the gate electrode; a second active layer 1075 is formed on the second gate insulating layer 1076, and a second source electrode 1071 and a second drain electrode 1072 are formed at both ends of the second active layer 1075, respectively; wherein the gate is shared by the first thin film transistor 105 and the second thin film transistor 107.

In some embodiments, after the step of forming the second source 1071 and the second drain 1072 at two ends of the second active layer 1075, respectively, the method further includes covering the second source 1071 and the second drain 1072 with a planarization layer 1077, and disposing a common electrode 1078 on a side of the planarization layer 1077 away from the second source 1071 and the second drain 1072.

In some embodiments, the step of electrically connecting the first source 1051 and the second source 1071 to the first data line 102 specifically includes: forming a via hole on the first gate insulating layer 1056 and the second gate insulating layer 1076; arranging a conductor in the through hole; both ends of the conductor are electrically connected to the first source 1051 and the second source 1071, respectively; the first source 1051 or the second source 1071 is electrically connected to the first data line 102. The first gate insulating layer 1056 and the second gate insulating layer 1076 are interlayer dielectric layers (Inter Layer Dielectric, ILD).

In other embodiments, the first source 1051 and the second source 1071 are each connected to a conductor.

The display panel 10 and the method for manufacturing the display panel 10 provided in the embodiments of the present application, wherein the display panel 10 has a first thin film transistor 105 and a first pixel electrode 106 electrically connected to the first thin film transistor 105, and the first pixel electrode 106 corresponds to the first sub-pixel region 103; a second thin film transistor 107 and a second pixel electrode 108 electrically connected to the second thin film transistor, wherein the second pixel electrode 108 corresponds to the second sub-pixel region 104. Since the first thin film transistor 105 and the second thin film transistor 107 are electrically connected to the scan line 101, and the thin film transistor 107 and the second thin film transistor 107 are connected to the first data line 102, the scan line 101 and the first data line 102 can commonly control the first pixel electrode 106 and the second pixel electrode 108, i.e., the first pixel electrode 106 and the second pixel electrode 108 can be charged or discharged at the same time. Therefore, when the first sub-pixel region 103 is turned on, the second sub-pixel region 104 is also turned on, and the transparent color block 202 corresponds to the second sub-pixel region 104 due to the first sub-pixel region 103 corresponding to the first color block, the transparent color block 202 can further increase the light transmittance of the display panel 10, so that the brightness of the display panel 10 is improved.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features.

The display panel and the preparation method of the display panel provided by the embodiment of the application are described in detail. Specific examples are set forth herein to illustrate the principles and embodiments of the present application, with the description of the examples given above only to assist in understanding the present application. Meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims

1. A display panel, comprising:

the array substrate and the color resistance layer are oppositely arranged;

the array substrate at least comprises a first thin film transistor, a first pixel electrode, a second thin film transistor, a second pixel electrode, a third thin film transistor, a third pixel electrode, a fourth thin film transistor and a fourth pixel electrode, wherein the first pixel electrode is electrically connected with the first thin film transistor, the second pixel electrode is electrically connected with the second thin film transistor, the first pixel electrode corresponds to a first sub-pixel area, the second pixel electrode corresponds to a second sub-pixel area, and the third pixel electrode corresponds to a third sub-pixel area; the fourth pixel electrode corresponds to a fourth sub-pixel area;

The array substrate is provided with a scanning line, a first data line and a second data line, the first data line comprises a first sub-data line and a second sub-data line, the first thin film transistor is respectively and electrically connected with the scanning line and the first sub-data line, the second thin film transistor is respectively and electrically connected with the scanning line and the second sub-data line, and the third thin film transistor and the fourth thin film transistor are respectively and electrically connected with the scanning line and the second data line;

the color resistance layer at least comprises a first color resistance block, a second color resistance block, a third color resistance block and a transparent color resistance block, wherein the first color resistance block corresponds to the first sub-pixel area, the transparent color resistance block corresponds to the second sub-pixel area, the second color resistance block corresponds to the third sub-pixel area, and the third color resistance block corresponds to the fourth sub-pixel area; the colors of the first color block and the second color block are different, the colors of the second color block and the third color block are the same, the first sub-pixel area and the third sub-pixel area are positioned on one side of the scanning line, the second sub-pixel area and the fourth sub-pixel area are positioned on the other side of the scanning line, the first sub-pixel area and the second sub-pixel area are oppositely arranged, and the third sub-pixel area and the fourth sub-pixel area are oppositely arranged;

The color of the first color block is blue, the first sub-pixel area is a blue sub-pixel, and the second sub-pixel area is a white sub-pixel; when the blue sub-pixel is turned on, the white sub-pixel is correspondingly turned on.

2. The display panel according to claim 1, wherein the second thin film transistor is disposed on the first thin film transistor, the first thin film transistor is a top gate thin film transistor, the second thin film transistor is a bottom gate thin film transistor, and a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are the same gate electrode.

3. The display panel of claim 1, wherein an area of the first subpixel region is the same as an area of the second subpixel region.

4. The display panel of claim 1, wherein the second color block is red, blue or green in color.

5. The display panel of claim 1, wherein the data line comprises a first sub data line and a second sub data line, the first thin film transistor is connected to the first sub data line, and the second thin film transistor is connected to the second sub data line.

6. A method for manufacturing a display panel, comprising:

providing a first thin film transistor;

providing a second thin film transistor;

providing a scanning line and a first data line;

forming a color resistance layer on the array substrate;

or providing the color resistance layer and arranging the color resistance layer and the array substrate in a box-to-box manner;

the array substrate further comprises a third thin film transistor, a third pixel electrode electrically connected with the third thin film transistor, a fourth thin film transistor and a fourth pixel electrode electrically connected with the fourth thin film transistor, and the third pixel electrode corresponds to a third sub-pixel area; the fourth pixel electrode corresponds to a fourth sub-pixel area; the first data line comprises a first sub-data line and a second sub-data line, the first thin film transistor is respectively and electrically connected with the scanning line and the first sub-data line, the second thin film transistor is respectively and electrically connected with the scanning line and the second sub-data line, the second data line is further arranged on the array substrate, and the third thin film transistor and the fourth thin film transistor are respectively and electrically connected with the scanning line and the second data line; the color resistance layer at least comprises a first color resistance block, a second color resistance block, a third color resistance block and a transparent color resistance block, wherein the first color resistance block corresponds to the first sub-pixel area, the color of the first color resistance block is blue, and the transparent color resistance block corresponds to the second sub-pixel area; the second color block corresponds to the third sub-pixel area, and the third color block corresponds to the fourth sub-pixel area; the colors of the first color block and the second color block are different, the colors of the second color block and the third color block are the same, the first sub-pixel area and the third sub-pixel area are positioned on one side of the scanning line, the second sub-pixel area and the fourth sub-pixel area are positioned on the other side of the scanning line, the first sub-pixel area and the second sub-pixel area are oppositely arranged, and the third sub-pixel area and the fourth sub-pixel area are oppositely arranged; the first sub-pixel area is a blue sub-pixel, and the second sub-pixel area is a white sub-pixel; when the blue sub-pixel is turned on, the white sub-pixel is correspondingly turned on.

7. The method of manufacturing a display panel according to claim 6, wherein the providing a first thin film transistor includes providing a substrate base plate; disposing a first active layer on the substrate base plate; forming a first source electrode and a first drain electrode at two ends of the first active layer respectively;

the providing a second thin film transistor includes: forming a second gate insulating layer on the gate electrode; forming a second active layer on the second gate insulating layer, and forming a second source electrode and a second drain electrode at both ends of the second active layer, respectively; wherein the gate is common to the first thin film transistor and the second thin film transistor.

8. The method of manufacturing a display panel according to claim 7, wherein electrically connecting the first source electrode and the second source electrode to the first data line comprises: forming a through hole on the first gate insulating layer and the second gate insulating layer; a conductor is arranged in the through hole; electrically connecting two ends of the conductor with the first source electrode and the second source electrode respectively; the first source electrode or the second source electrode is electrically connected to the first data line.