CN117913122A

CN117913122A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN117913122A
Application number: CN202410114673.3A
Authority: CN
Inventors: 殷华湘; 曹磊; 张青竹; 姚佳欣; 张亚东
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2024-01-26
Filing date: 2024-01-26
Publication date: 2024-04-19

Abstract

The application provides a semiconductor device and a method for manufacturing the same, the semiconductor device includes: the source electrode, the drain electrode, the grid electrode and the channel structure are arranged on one side of the substrate, the channel structure comprises a lamination formed by a plurality of nano sheets, and the grid electrode surrounds the nano sheets. In the present application, the substrate may include a first substrate and a second substrate which are sequentially stacked, wherein the first substrate is a semiconductor material and the second substrate is an insulating material, that is, the substrate of the present application is a semiconductor-on-insulator substrate, so that the performance of GAAFET can be optimized. The semiconductor device provided by the application comprises the isolation structure, wherein the isolation structure is arranged between the channel structure and the second substrate, and extends to the source electrode and the drain electrode in the direction parallel to the plane of the substrate, so that effective isolation is formed among the substrate, the grid electrode, the drain electrode and the source electrode, and parasitic channel leakage of the substrate is restrained by utilizing the isolation structure, thereby reducing off-state leakage current of the device under the condition of shorter grid length and improving the integral performance of the device.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a semiconductor device and a method of manufacturing the same.

Background

With the development of semiconductor technology, the feature size of integrated circuits is continuously shrinking, and the conventional tri-gate or dual-gate fin field effect transistor (fin field-Effect Transistor, finFET) is limited to nodes below 3 nanometers (nm), and the nanosheet ring gate transistor (Nanosheet-Gate all round Fin Field-Effect Transistor, nanosheet-GAAFET) breaks through the limitation of the 3nm node, so that the semiconductor device is widely focused and studied.

Nanosheet-GAAFET are novel devices with a gate-all-around structure and horizontal nanoplates (Nanosheet, NS) as conductive channels. In the aspect of gate control, the gate-surrounding structure has better gate control capability than a FinFET device structure, short channel effect of the device can be effectively inhibited, and in the aspect of current driving, nanosheet-GAAFET have inversion carriers of 'body inversion', and the current driving performance of the device can be remarkably enhanced through the increase of effective gate width and the design of nano-sheet stacking in the vertical direction.

Current Nanosheet-GAAFET can be classified into GAAFET based on Bulk silicon substrate (Bulk-Si) and GAAFET based on Silicon On Insulator (SOI) depending on the substrate material. Compared with GAAFET based on a Bulk silicon substrate, GAAFET based on the silicon on insulator can effectively simplify the process manufacturing flow and inhibit Bulk-Si electric leakage, so that the method has a great application prospect.

However, GAAFET on a silicon-on-insulator basis still suffers from leakage problems due to bottom parasitic channels, degrading the device performance of GAAFET on a silicon-on-insulator basis.

Disclosure of Invention

Accordingly, an object of the present application is to provide a semiconductor device and a method for manufacturing the same, which can suppress parasitic channel leakage, reduce off-state leakage current of the device, and improve overall performance of the device.

The present application provides a semiconductor device including:

The substrate comprises a first substrate and a second substrate which are sequentially stacked, wherein the first substrate is made of a semiconductor material, and the second substrate is made of an insulating material;

The source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is positioned between the source electrode and the drain electrode, and the channel structure comprises a lamination formed by a plurality of nano sheets;

The isolation structure is arranged between the channel structure and the second substrate, and extends to the source electrode and the drain electrode in a direction parallel to the plane of the substrate;

A gate surrounding the nanoplatelets.

As a possible implementation, one side of the isolation structure is in contact with the source and the other side of the isolation structure is in contact with the drain in a direction parallel to the plane of the substrate.

As one possible implementation manner, the substrate includes a third substrate, the third substrate is located on a side of the second substrate away from the first substrate, the third substrate and the source electrode and the drain electrode do not overlap, and a material of the third substrate is a semiconductor material;

the third substrate is covered by the isolation structure, and the third substrate and the source and drain are separated by the isolation structure.

As one possible implementation manner, the substrate includes a third substrate, the third substrate is located on a side of the second substrate away from the first substrate, the third substrate and the source electrode and the drain electrode do not overlap, and a material of the third substrate is a semiconductor material; the isolation structure comprises a first isolation structure and a second isolation structure;

The third substrate is located between the channel structure and the second substrate, a first isolation structure is arranged between the third substrate and the source electrode, and a second isolation structure is arranged between the third substrate and the drain electrode.

As a possible implementation, the first isolation structure and the second isolation structure comprise a first sidewall adjacent to the channel structure in a direction parallel to the plane of the substrate, the first sidewall and the sidewall of the channel structure being flush in a direction perpendicular to the plane of the substrate.

As a possible implementation manner, the isolation structure includes a first isolation portion and a second isolation portion, where the first isolation portion is located on a side of the second isolation portion away from the substrate;

In the direction parallel to the plane of the substrate, the first isolation part comprises a second side wall far away from the channel structure, the second isolation part comprises a third side wall far away from the channel structure, the second side wall and the third side wall are not flush in the direction perpendicular to the plane of the substrate, and the third side wall is arranged on one side of the second side wall close to the source electrode or the drain electrode.

As a possible implementation, the material of the isolation structure is a low-k dielectric material.

The application provides a manufacturing method of a semiconductor device, which comprises the following steps:

Providing a substrate, and forming a plurality of laminated structures formed by alternately laminating a first semiconductor layer and a second semiconductor layer on one side of the substrate; the substrate comprises a first substrate, a second substrate and a third substrate which are sequentially stacked, wherein the first substrate and the third substrate are made of semiconductor materials, and the second substrate is made of insulating materials;

Etching the laminated structure and the third substrate with partial thickness to form a source electrode region and a drain electrode region, wherein a channel region is arranged between the source electrode region and the drain electrode region;

Etching to remove the third substrate positioned in the source electrode region and the drain electrode region, and etching to remove all or part of the third substrate along the direction towards the channel region on a plane parallel to the substrates to form grooves which completely or partially separate the laminated structure and the second substrate;

filling insulating materials in the grooves to form isolation structures;

Forming a source electrode and a drain electrode in the source electrode region and the drain electrode region respectively, wherein the isolation structure is arranged between the laminated structure and the second substrate, and extends to the source electrode and the drain electrode in a direction parallel to a plane of the substrate;

And replacing the first semiconductor layer with a grid, wherein the grid surrounds the second semiconductor layer, and a channel structure is formed by a lamination formed by a plurality of second semiconductor layers.

As a possible implementation manner, the etching to remove the third substrate located in the source region and the drain region, etching to remove all or part of the third substrate along a direction toward the channel region on a plane parallel to the substrates, and forming the recess includes:

Etching and removing the third substrate positioned in the source electrode region and the drain electrode region by utilizing an anisotropic etching process;

and etching and removing all or part of the third substrate along the direction towards the channel region by utilizing an isotropic etching process on a plane parallel to the substrate to form a groove.

As a possible implementation, before etching to remove the third substrate located in the source region and the drain region, the method further includes:

etching and removing part of the first semiconductor layer in the direction parallel to the plane of the substrate to form an inward recess;

Forming a protection side wall in the inward recess, wherein the protection side wall covers part of the third substrate;

The etching to remove the third substrate located in the source region and the drain region by using an anisotropic etching process comprises:

Etching to remove the third substrate which is positioned in the source electrode region and the drain electrode region and is not covered by the protection side wall by utilizing an anisotropic etching process;

filling insulating materials in the grooves, and forming the isolation structure comprises the following steps:

Filling insulating materials in the grooves, and forming an isolation structure by self-aligned etching, wherein the isolation structure comprises a first isolation part and a second isolation part, and the first isolation part is positioned at one side of the second isolation part away from the substrate;

In the direction parallel to the plane of the substrate, the first isolation part comprises a second side wall far away from the channel region, the second isolation part comprises a third side wall far away from the channel region, the second side wall and the third side wall are not flush in the direction perpendicular to the plane of the substrate, the third side wall and the side wall of the protection side wall are flush, and the third side wall is arranged on one side, close to the source region or the drain region, of the second side wall.

The present application provides a semiconductor device including: the substrate, set up source, drain, grid and channel structure of one side of the substrate, the channel structure is located between source and drain, the channel structure includes the lamination that a plurality of nanoplates formed, the grid surrounds the nanoplate, in this way, through substrate, source, drain, grid and channel structure constitution basic GAAFET. In the present application, the substrate may include a first substrate and a second substrate which are sequentially stacked, wherein the first substrate is a semiconductor material and the second substrate is an insulating material, that is, the substrate of the present application is a semiconductor-on-insulator substrate, so that the performance of GAAFET can be optimized. The semiconductor device provided by the application comprises the isolation structure, wherein the isolation structure is arranged between the channel structure and the second substrate, and extends to the source electrode and the drain electrode in the direction parallel to the plane of the substrate, so that effective isolation is formed among the substrate, the grid electrode, the drain electrode and the source electrode, and parasitic channel leakage of the semiconductor substrate, which is near the channel structure, is prepared by utilizing the isolation structure to inhibit GAAFET on the semiconductor substrate on an insulator, thereby reducing off-state leakage current of the device under the condition of shorter grid length and improving the integral performance of the device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a schematic cross-sectional structure of a silicon-on-insulator-based GAAFET;

fig. 2 is a schematic three-dimensional structure of a semiconductor device according to an embodiment of the present application;

fig. 3 and fig. 4 are schematic cross-sectional structures of the semiconductor device shown in fig. 1 in various directions according to an embodiment of the present application;

FIG. 5 is a schematic cross-sectional view of another embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of another embodiment of the present application;

Fig. 7 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

Fig. 8 to 32 are schematic structural views showing a method for manufacturing a semiconductor device according to an embodiment of the present application.

Detailed Description

In order to make the present application better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.

While the embodiments of the present application have been illustrated and described in detail in the drawings, the cross-sectional view of the device structure is not to scale in the general sense for ease of illustration, and the drawings are merely exemplary and should not be construed as limiting the scope of the application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Current Nanosheet-GAAFET can be classified into GAAFET based on Bulk silicon substrate (Bulk-Si) and GAAFET based on Silicon On Insulator (SOI) depending on the substrate material.

The existence of thicker bottom fins (Sub-fin) at the bottom of the stacked nanoplates in GAAFET of the bulk silicon substrate results in a larger leakage current at Nanosheet-GAAFET, where the bulk silicon substrate typically employs a heavily doped well of opposite doping type to the source or drain to suppress parasitic channel leakage at the bottom of the source or drain and gate. However, in process nodes of 5nm and below, the suppression capability of the heavily doped well to parasitic channel leakage is reduced, and the problem of leakage current caused by band-to-band (BTBT) tunneling between the source and drain by the heavily doped well may also exist based on GAAFET of the bulk silicon substrate.

The GAAFET based on the silicon on insulator has the advantages that the substrate material is rich, so that a heavily doped well is not needed, an isolation medium in the substrate is not needed to be formed by using a Shallow Trench Isolation (STI), the process manufacturing flow is greatly simplified, the process stability is high, and the electrical stability of GAAFET manufactured by using the silicon on insulator can be improved.

The silicon-on-insulator-based GAAFET substrate material comprises a bottom silicon, an insulating layer and a top silicon 10, which are stacked in sequence, the top silicon 10 being covered by a channel structure, the top silicon 10 being flanked by a source and a drain, respectively, as shown with reference to fig. 1. As the gate length is gradually reduced, the top silicon becomes a parasitic channel, resulting in leakage problems, degrading the performance of the silicon-on-insulator-based GAAFET device.

Based on this, the present application provides a semiconductor device, and the substrate of the present application includes a first substrate and a second substrate which are stacked, and is a semiconductor-on-insulator substrate, so that the performance of GAAFET can be optimized. The semiconductor device provided by the application comprises the isolation structure, wherein the isolation structure is arranged between the channel structure and the second substrate, and extends to the source electrode and the drain electrode in the direction parallel to the plane of the substrate, so that effective isolation is formed among the substrate, the grid electrode, the drain electrode and the source electrode, and parasitic channel leakage of the semiconductor substrate, which is near the channel structure, is prepared by utilizing the isolation structure to inhibit GAAFET on the semiconductor substrate on an insulator, thereby reducing off-state leakage current of the device under the condition of shorter grid length and improving the integral performance of the device.

For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

Referring to fig. 2, a schematic three-dimensional structure of a semiconductor device according to an embodiment of the present application is shown.

The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, a gate 160, and an isolation structure 200.

In the embodiment of the present application, the substrate 110 includes a first substrate 111, a second substrate 112, and a third substrate 113 that are sequentially stacked, and the third substrate 113 is located on a side of the second substrate 112 away from the first substrate 111, as shown with reference to fig. 3 or 4, wherein the first substrate 111 and the third substrate 112 are semiconductor materials, such as silicon or germanium. The second substrate 112 is an insulating material, such as silicon oxide. The substrate of the present application is a semiconductor-on-insulator substrate, which can improve GAAFET performance.

As an example, the first substrate 111 is silicon, the second substrate 112 is silicon oxide, and the third substrate 113 is silicon, and then the substrate 110 may be a silicon-on-insulator (SOI) substrate.

In the embodiment of the present application, a source 131, a drain 132 and a channel structure are disposed on one side of a substrate 110, the channel structure is disposed between the source 131 and the drain 132, the channel structure includes a stack formed by a plurality of nano-sheets, wherein the channel structure is obtained by removing a first semiconductor layer 121 in the stack structure, the stack structure is formed by alternately stacking the first semiconductor layer 121 and a second semiconductor layer 122, that is, the nano-sheets in the channel structure are the second semiconductor layer 122 in the stack structure, and refer to fig. 3 and 4, wherein fig. 3 is a schematic cross-sectional structure of the semiconductor device shown in fig. 2 in the YY direction provided in the embodiment of the present application, fig. 4 is a schematic cross-sectional structure of the semiconductor device shown in fig. 2 in the XX direction provided in the embodiment of the present application, the schematic cross-sectional structure of the XX direction is a direction parallel to fin lines of fins, and the schematic cross-sectional structure of the YY direction is a direction perpendicular to fin lines of fins.

In the embodiment of the present application, a space is provided between the plurality of nano-sheets in the channel structure, and the space is filled with the gate 160, that is, the gate 160 surrounds the nano-sheets, so as to form a ring gate structure.

In an embodiment of the present application, the isolation structure 200 is disposed between the channel structure and the second substrate 112, the isolation structure 200 and the second substrate 112 are in direct contact, and the isolation structure 200 extends to the source 131 and the drain 132 in a direction parallel to a plane in which the substrate 110 is located. In this way, effective isolation is formed among the substrate 110, the channel structure, the gate 160, the drain 132 and the source 131, and parasitic channel leakage of the substrate 110 is suppressed by using the isolation structure 200, so that off-state leakage current of the device is reduced, and overall performance of the device is improved.

Since the third substrate 113 is covered by the gate electrode 160 on both sides of the source electrode 131 and the drain electrode 132, the third substrate 113 forms a parasitic channel, so that the leakage current caused by the parasitic channel is reduced, and the third substrate 113, the gate electrode 160, the source electrode 131 and the drain electrode 132 may be isolated, or the third substrate 113, the gate electrode 160, the source electrode 131 and the drain electrode 132 may be isolated.

In some embodiments, the third substrate 113 may be removed during the process, that is, in the finally manufactured semiconductor device, the substrate 110 includes only the first substrate 111 and the second substrate 112, and referring to fig. 5, fig. 5 is a schematic cross-sectional structure in the XX direction of the semiconductor device shown in fig. 2, which is provided in the embodiment of the present application, so that a parasitic channel formed by the third substrate 113 may be removed by removing the third substrate 113, thereby avoiding a leakage current caused by the parasitic channel.

The morphology of the isolation structure 200 for suppressing parasitic channel leakage is specifically described below by taking three examples as examples:

A first possible implementation is to completely remove the third substrate 113, i.e. the isolation structure 200 is located between the gate 160 and the second substrate 112, and the sidewalls of both sides of the isolation structure 200 are respectively in contact with the source 131 and the drain 132, at which time the isolation structure 200 is an integral structure, as shown with reference to fig. 5, that is, in a direction parallel to the plane of the substrate 110, one side of the isolation structure 200 is in contact with the source 131 and the other side of the isolation structure 200 is in contact with the drain 130. Thus, the isolation structure 200 is disposed between the source 131 and the drain 132, and the isolation structure 200 is not conductive and without the third substrate 113, parasitic channel leakage can be completely avoided.

A second possible implementation is to remove part of the third substrate 113. In the direction perpendicular to the plane of the substrate 110, the third substrate 113 is only disposed in the area overlapping the channel structure, and the third substrate 113, the source 131 and the drain 132 are not overlapped, the third substrate 113, the source 131 and the drain 132 are separated by the isolation structure 200, the third substrate 113 is covered by the isolation structure 200, referring to fig. 6, fig. 6 is a schematic cross-sectional structure in XX direction of the semiconductor device shown in fig. 2, which is provided in the embodiment of the present application, and the isolation structure 200 is an integral structure, so that the isolation structure 200 is used to completely isolate the third substrate 113, the gate 160, the source 131 and the drain 132, thereby reducing the leakage current caused by parasitic channels.

A third possible implementation is to remove part of the third substrate 113. In a direction perpendicular to the plane of the substrate 110, the third substrate 113 is disposed only in a region overlapping the channel structure, the third substrate 113 is located between the channel structure and the second substrate 112, i.e., one side surface of the third substrate 113 is in contact with the gate electrode 160, and the third substrate 113 and the source electrode 131 and the drain electrode 132 do not overlap. The isolation structure 200 may include a first isolation structure and a second isolation structure, the first isolation structure is disposed between the third substrate 113 and the source electrode 131, and the second isolation structure is disposed between the third substrate 113 and the drain electrode 132, as shown with reference to fig. 4. Thus, the isolation structure 200 is used to completely isolate the third substrate 113, the source electrode 131 and the drain electrode 132, thereby reducing the leakage current caused by the parasitic channel.

In some embodiments, the first isolation structure and the second isolation structure each include a first sidewall proximate to the channel structure in a direction parallel to the plane of the substrate 110, the first sidewall and the sidewall of the channel structure being flush in a direction perpendicular to the plane of the substrate 110. That is, the isolation structure 200 corresponds to the inner sidewall 206 between adjacent nano-sheets, which is simple and easy to control for the process of forming the isolation structure 200.

It should be noted that the positions of the first isolation structure and the second isolation structure may be interchanged, that is, the second isolation structure is disposed between the third substrate 113 and the source electrode 131, and the first isolation structure is disposed between the third substrate 113 and the drain electrode 132. In addition, the first isolation structure and the second isolation structure may be symmetrical structures, thereby avoiding degradation of device performance due to the first isolation structure and the second isolation structure.

In an embodiment of the present application, whether the isolation structure 200 is a unitary structure or comprises 2 structures, the isolation structure 200 comprises 2 portions, a first isolation portion 210 and a second isolation portion 220, wherein the first isolation portion 210 is located on a side of the second isolation portion 220 away from the substrate 110, that is, the first isolation portion 210 is closer to the gate 160 and the second isolation portion 220 is closer to the second substrate 112.

The first isolation portion 210 includes a second sidewall away from the channel structure in a direction parallel to the plane of the substrate 110, the second isolation portion 220 includes a third sidewall away from the channel structure, the second sidewall and the third sidewall are not level in a direction perpendicular to the plane of the substrate 110, and the third sidewall is disposed on a side of the second sidewall near the source 131 or the drain 132. That is, the second isolation portion 220 protrudes toward the source 131 or the drain 132 as compared to the first isolation portion 210, thereby causing the isolation structure 200 to extend toward the source 131 or the drain 132. This is because the formation process of the isolation structure 200 is performed before the formation of the inner sidewall 206, so as to protect the trench structure, and thus the isolation structure 200 forms a special structure with such non-flush sidewalls, so that the manufacturing cost of the device can be reduced as much as possible by adding the process for forming the isolation structure 200 to suppress the leakage current without affecting other process steps.

In some embodiments, the maximum thickness of the isolation structure 200 may be the initial thickness of the third substrate 113, and the thickness of the isolation structure 200 may range from 1-100nm. The width of the isolation structure 200 along the XX direction may range from 1 to 100nm.

In an embodiment of the present application, the material of the isolation structure 200 is an insulating material, for example, the isolation structure 200 is a low-k dielectric material.

As one example, the low-k dielectric material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, doped silicon nitride, and doped silicon oxide.

In the embodiment of the present application, the material of the inner side wall 206 may be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride and air, where the material of the inner side wall 206 is air, and the position of the inner side wall 206 may be formed into an air cavity by using the air cavity to achieve the function of the inner side wall 206.

As an example, the material of the high-k dielectric layer 150 may be one or a combination of HfO₂、HfSiO_x、HfON、HfSiON、HfAlO_x、HfLaO_x、Al₂O₃、ZrO₂、ZrSiO_x、Ta₂O₅ or La ₂O₃.

In an embodiment of the present application, the semiconductor device further includes a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.

The second side walls 205 are disposed on a side of the channel structure away from the substrate 110, and the gate 160 is disposed between the second side walls 205. The isolation layer 207 is disposed on a side of the source electrode 131 or the drain electrode 132 away from the substrate 110, and the second sidewall 205 and the gate 160 are disposed between the isolation layers 207.

The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160, and the top dielectric layer 170 has a contact electrode 180, where the contact electrode 180 is used for electrically leading out the source 131 or the drain 132.

It can be seen that the semiconductor device provided by the present application comprises: the substrate, set up source, drain, grid and channel structure of one side of the substrate, the channel structure is located between source and drain, the channel structure includes the lamination that a plurality of nanoplates formed, the grid surrounds the nanoplate, in this way, through substrate, source, drain, grid and channel structure constitution basic GAAFET. In the present application, the substrate may include a first substrate, a second substrate, and a third substrate which are sequentially stacked, wherein the first substrate is a semiconductor material, the second substrate is an insulating material, the third substrate is also a semiconductor material, and the third substrate may be partially removed or completely removed, that is, the substrate of the present application is a semiconductor-on-insulator substrate, so that the performance of GAAFET may be optimized. The semiconductor device provided by the application comprises the isolation structure, wherein the isolation structure is arranged between the channel structure and the second substrate, and extends to the source electrode and the drain electrode in the direction parallel to the plane of the substrate, so that effective isolation is formed among the substrate, the grid electrode, the drain electrode and the source electrode, and parasitic channel leakage of the semiconductor substrate, which is near the channel structure, is prepared by utilizing the isolation structure to inhibit GAAFET on the semiconductor substrate on an insulator, thereby reducing off-state leakage current of the device under the condition of shorter grid length and improving the integral performance of the device.

Based on the semiconductor device provided in the above embodiments, the embodiments of the present application further provide a method for manufacturing a semiconductor device, and the working principle thereof is described in detail below with reference to the accompanying drawings.

Referring to fig. 7, a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the application is shown.

The manufacturing method of the semiconductor device provided by the embodiment of the application comprises the following steps:

S101, a substrate 110 is provided, and a stacked structure in which first semiconductor layers 121 and second semiconductor layers 122 are alternately stacked is formed on one side of the substrate 110, as shown with reference to fig. 8A and 8B.

In an embodiment of the present application, the substrate 110 includes a first substrate 111, a second substrate 112, and a third substrate 113 that are sequentially stacked, wherein the first substrate 111 and the third substrate 112 are semiconductor materials, such as silicon or germanium. The second substrate 112 is an insulating material, such as silicon oxide. The substrate of the present application is a semiconductor-on-insulator substrate that can improve GAAFET performance over a bulk silicon substrate that includes a heavily doped well.

In an embodiment of the present application, a stacked structure in which the first semiconductor layer 121 and the second semiconductor layer 122 are alternately stacked may be formed on one side of the substrate 110, as shown in fig. 8A and 8B, where fig. 8A is a schematic cross-sectional structure of the semiconductor device shown in fig. 2 in the YY direction, and fig. 8B is a schematic cross-sectional structure of the semiconductor device shown in fig. 2 in the XX direction, which is a direction parallel to fin lines of the fins, and the schematic cross-sectional structure of the YY direction is a direction perpendicular to the fin lines of the fins.

The first semiconductor layer 121 and the second semiconductor layer 122 may be formed using an epitaxial process.

Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be the same, for example, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon or germanium. The materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be different for different device types, for example, for a P-type semiconductor device, the material of the first semiconductor layer 121 may be silicon and the material of the second semiconductor layer 122 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium and the material of the second semiconductor layer 122 may be silicon.

In practical applications, silicon oxide may be formed on the substrate 110, and the stacked structure may be formed after removing the silicon oxide on the substrate 110 and cleaning the substrate 110.

S102, the third substrate 113 having the stacked structure and a partial thickness is etched to form the source region 101 and the drain region 102, as shown in fig. 13.

In an embodiment of the present application, the stacked structure and a portion of the thickness of the third substrate 113 may be etched to form the source region 101 and the drain region 102, where the channel region 103 is between the source region 101 and the drain region 102, and the source region 101 and the drain region 102 are formed by etching the stacked structure after etching the portion of the thickness of the third substrate 113, so that parasitic channels may be formed in the third substrate 113 in the channel region 103 later, as shown in fig. 13.

The process flow for specifically forming the source region 101 and the drain region 102 is as follows:

s1021, an inside wall transfer process, as shown with reference to fig. 9A and 9B.

In the embodiment of the present application, a self-aligned inner sidewall transfer process is adopted to form the first sidewall 201, and the material of the first sidewall 201 is silicon nitride, and the specific forming process is as follows: a layer of sacrificial layer 202 is covered on the laminated structure, the material of the sacrificial layer 202 can be polysilicon or amorphous silicon, part of the sacrificial layer 202 is etched by utilizing photoetching, silicon nitride material is deposited, and the rest of the sacrificial layer 202 is etched by adopting anisotropic etching, so that the sacrificial layer is only remained on the first side wall 201 on the laminated structure, and the first side wall 201 plays a role of a Hard Mask (Hard Mask) in the subsequent photoetching for forming fins.

S1022, fins are formed, as shown with reference to fig. 10A and 10B.

In an embodiment of the present application, the stacked structure may be etched by an etching process to form a plurality of fins distributed periodically, as shown with reference to fig. 10A and 10B. And etching by taking the first side wall 201 as a mask to form the fin with the laminated structure. The upper part of the fin is a channel region 103 formed by a laminated structure, and the lower part of the fin is a third substrate 113, so as to form the fin as shown in fig. 10A. The fin includes not only the stacked structure but also the third substrate 113. The etching process may be anisotropic etching. The fins will be used to form nano-sheets of semiconductor devices. Although fig. 10A shows one fin, it should be appreciated that any suitable number and configuration of fins may be used in practice.

In practical summary, after forming the fin, the first sidewall 201 may be removed, and the specific etching process may be dry etching or wet etching.

S1023, dummy gate 204 is formed, as shown with reference to fig. 11A and 11B.

In an embodiment of the present application, a dummy gate stack (dummy gate) is formed on the exposed fin in a direction horizontal to the fin line, i.e., XX direction. The dummy gate stack is a multi-layered structure including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack may be formed by thermal oxidation, chemical vapor deposition, sputtering, and the like. The dummy gate stack spans the stack structure at the upper portion of the fin, and a plurality of dummy gates are periodically distributed along the fin line direction. The material of dummy gate 204 may be polysilicon or amorphous silicon. The material of the hard mask layer may be oxide, carbide, organic, etc.

S1024, a second sidewall 205 is formed, as shown in fig. 12.

In the embodiment of the present application, the second sidewalls 205 may be respectively disposed on two sides of the dummy gate stack along the fin line direction, that is, the XX direction, where the thicknesses of the second sidewalls 205 on two sides are the same, as shown in fig. 12, and fig. 12 is a schematic cross-sectional structure of the XX direction of the semiconductor device shown in fig. 2 provided in the embodiment of the present application. The material of the second sidewall 205 may be a dielectric material having isolation properties, such as silicon nitride or doped silicon oxide.

In the embodiment of the present application, after the dummy gate 204 and the second sidewall 205 are formed, the dummy gate 204 and the second sidewall 205 may be used as masks to perform source-drain etching on the third substrate 113 with the laminated structure and a part of thickness through an etching process, and specifically perform source-drain etching on the fin. After the source region 101 and the drain region 102 are formed by etching, the stacked structure is no longer provided, and the third substrate 113 with a partial thickness of the source region 101 and the drain region 102 is also etched, as shown in fig. 13, and fig. 13 is a schematic cross-sectional structure of the semiconductor device in XX direction shown in fig. 2 according to the embodiment of the present application.

S1025, a concave structure 401 is formed, as shown with reference to fig. 14.

In the embodiment of the present application, the first semiconductor layer 121 in the stacked structure located in the channel region 103 is selectively etched in the first direction, that is, in the XX direction, in the direction parallel to the plane of the substrate 110, that is, only the first semiconductor layer 121 is etched, the second semiconductor layer 122 is not damaged, the portion of the first semiconductor layer 121 that is missing from the second semiconductor layer 122 in the XX direction is recessed inward to form a concave structure 401, that is, a pull-back etching is performed, and a portion of the first semiconductor layer 121 is etched away from the source region 101 and the drain region 102 toward the channel region 103, and referring to fig. 14, fig. 14 is a schematic cross-sectional structure in the XX direction of the semiconductor device shown in fig. 2 provided in the embodiment of the present application.

S1026, a protection sidewall 501 is formed, as shown in fig. 15A and 15B.

In the embodiment of the present application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the periphery of the stacked structure, i.e., the fin, in the channel region 103, so as to form a protection sidewall 501, where the protection sidewall 501 covers the dummy gate 204, the second sidewall 205, the sidewall of the stacked structure, and the third substrate 113.

The protective sidewalls 501 in the source region 101 and the drain region 102 are then etched away using an anisotropic etching process, exposing the third substrate 113 in the source region 101 and the drain region 102, as shown with reference to fig. 16A and 16B.

S103, etching to remove the third substrate 113 located in the source region 101 and the drain region 102, and etching to remove all or part of the third substrate 113 along a direction toward the channel region 103 on a plane parallel to the substrate 110, thereby forming the recess 502.

In an embodiment of the present application, the third substrate 113 located in the source region 101 and the drain region 102 may be etched away using an etching process, and in particular, the third substrate 113 located in the source region 101 and the drain region 102 may be etched away using an anisotropic etching process. In the process of etching to remove the third substrate 113 located in the source region 101 and the drain region 102, since the protection sidewall 501 covers the third substrate 113 located in the channel region 103, the third substrate 113 located in the channel region 103 may be retained, as shown in fig. 17, and fig. 17 is a schematic cross-sectional structure of the semiconductor device in XX direction shown in fig. 2 according to the embodiment of the present application.

On a plane parallel to the substrate 110, all of the third substrate 113 or part of the third substrate 113 is etched away in a direction towards the channel region 103, forming a recess 502. Specifically, an isotropic etching process may be used, where the etching depth is determined according to the shape of the pre-designed isolation structure 200.

A first possible implementation manner is to etch and remove all the third substrate 113, that is, the channel region 102 does not have the third substrate 113, and a groove 502 is formed between the second substrate 112 and the stacked structure, as shown in fig. 18, and fig. 18 is a schematic cross-sectional structure of the semiconductor device in XX direction shown in fig. 2 according to the embodiment of the present application.

A second possible implementation is to remove part of the third substrate 113, leave part of the thickness of the third substrate 113 in the channel region 102, the third substrate 113 being in contact with the second substrate 112, and have a recess 502 between the third substrate 113 and the stack, i.e. the third substrate 113 and the stack are not in direct contact. Along the XX direction, the groove 502 penetrates through the laminated structure, and referring to fig. 19, fig. 19 is a schematic cross-sectional structure of the XX direction of the semiconductor device shown in fig. 2 according to the embodiment of the application.

A third possible implementation is to remove part of the third substrate 113. The third substrate 113 remains in the channel region 102 at full thickness, the surface of the third substrate 113 is in contact with the stack structure and the second substrate 112, respectively, and the sidewalls of the third substrate 113 are flush with the sidewalls of the stack structure. The recess 502 is formed by surrounding the protection sidewall 501, the third substrate 113 and the second substrate 112, and referring to fig. 20, fig. 20 is a schematic cross-sectional view of the semiconductor device in XX direction shown in fig. 2 according to the embodiment of the present application. The groove 502 includes a first groove having an opening toward one of the source region 101 and the drain region 102 and a second groove having an opening toward the other of the source region 101 and the drain region 102, and the first groove and the second groove are of a symmetrical structure.

And S104, filling the grooves 502 with insulating materials to form the isolation structures 200, as shown in reference to FIGS. 21-23.

In an embodiment of the present application, after the recess 502 is etched, the recess 502 may be filled with an insulating material, and the insulating material outside the recess 502 may be removed by anisotropic etching to form the isolation structure 200. Specific processes for filling the insulating material may be physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD) and atomic layer deposition (Atomic Layer Deposition, ALD).

The morphology of the grooves 502 is different, and the morphology of the isolation structure 200 obtained by filling is also different.

In a first possible implementation manner, the recess 502 formed by the third substrate 113 is completely removed, the surface of the isolation structure 200 formed by filling the insulating material is respectively in contact with the stacked structure and the second substrate 112, the sidewalls of two sides of the isolation structure 200 are respectively in contact with the source 131 and the drain 132 formed subsequently, at this time, the isolation structure 200 is an integral structure, and referring to fig. 21, fig. 21 is a schematic cross-sectional structure in the XX direction of the semiconductor device shown in fig. 2, that is, in a direction perpendicular to the plane of the substrate 110, the sidewalls of the isolation structure 200 and the sidewalls of the protection sidewall 501 are flush.

A second possible implementation is to remove a portion of the recess 502 formed by the third substrate 113. The surface of the isolation structure 200 formed by filling the insulating material is contacted with the stacked structure, the third substrate 113 is covered by the isolation structure 200, and the sidewalls of the two sides of the isolation structure 200 are respectively contacted with the source electrode 131 and the drain electrode 132 formed subsequently, at this time, the isolation structure 200 is an integrated structure, and referring to fig. 22, fig. 22 is a schematic cross-sectional structure in the XX direction of the semiconductor device shown in fig. 2, which is provided in the embodiment of the present application, in a direction perpendicular to the plane of the substrate 110, and the sidewalls of the isolation structure 200 are flush with the sidewalls of the protection sidewall 501.

A third possible implementation is to remove a portion of the recess 502 formed by the third substrate 113, including the first recess and the second recess. And filling insulating materials in the first groove and the second groove respectively to form a first isolation structure and a second isolation structure respectively. For example, a first isolation structure is disposed between the third substrate 113 and the source region 101, and a second isolation structure is disposed between the third substrate 113 and the drain region 102, as shown in fig. 23, and fig. 23 is a schematic cross-sectional view of the semiconductor device in XX direction shown in fig. 2 according to an embodiment of the present application.

In an embodiment of the present application, whether the isolation structure 200 is a unitary structure or comprises 2 structures, the isolation structure 200 is disposed between the stacked structure and the second substrate 112, and the isolation structure 200 comprises 2 portions, a first isolation portion 210 and a second isolation portion 220, wherein the first isolation portion 210 is located on a side of the second isolation portion 220 away from the substrate 110, that is, the first isolation portion 210 is closer to the gate 160 and the second isolation portion 220 is closer to the second substrate 112.

The first isolation portion 210 includes a second sidewall away from the channel region 103 in a direction parallel to the plane of the substrate 110, the second isolation portion 220 includes a third sidewall away from the channel region 103, the second sidewall and the third sidewall are not flush in a direction perpendicular to the plane of the substrate 110, the third sidewall is flush with a sidewall of the protection sidewall 501, and the third sidewall is disposed on a side of the second sidewall near the source region 101 or the drain region 102. That is, the second isolation portion 220 protrudes toward the source region 101 or the drain region 102 as compared to the first isolation portion 210, thereby causing the isolation structure 200 to extend toward the source region 101 or the drain region 102.

In the embodiment of the present application, after the groove 502 is filled with the insulating material and the isolation structure 200 is formed by self-aligned etching, the protection sidewall 501 may be etched to form the inner sidewall 206 between the adjacent second semiconductor layers 122, where the inner sidewall 206 is flush with the second semiconductor layers 122 in the direction perpendicular to the plane of the substrate 110. That is, the concave structure 401 formed by S1025 is filled by the inner side wall 206, and the material of the inner side wall 206 may be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride and air, wherein the material of the inner side wall 206 is air, and an air cavity can be formed at the position where the inner side wall 206 is located, and the air cavity is utilized to reach the inner side wall 206.

In the process of removing part of the protection sidewall 501, the isolation structure 200 maintains the original shape, so that after the formation of the inner sidewall 206, the portion of the second isolation portion 220 protruding toward the source region 101 or the drain region 102 is exposed, as shown in fig. 24-26, and fig. 24-26 are schematic cross-sectional views of the semiconductor device in XX direction shown in fig. 2 according to the embodiment of the present application.

S105, a source 131 and a drain 132 are formed in the source region 101 and the drain region 102, respectively, as shown in fig. 27 to 29.

In the embodiment of the present application, after the source region 101 and the drain region 102 are etched to form the stacked structure and the isolation structure 200 is formed, the source 131 and the drain 132 may be formed in the source region 101 and the drain region 102 respectively by using an epitaxial process, and the isolation structure 200 extends to the source 131 and the drain 132 in a direction parallel to a plane of the substrate 110, as shown in fig. 27, 28 and 29B, and fig. 27, 28 and 29B are schematic cross-sectional structures of the semiconductor device XX direction shown in fig. 2 provided in the embodiment of the present application.

Specifically, the source and drain materials may be different for different types of semiconductor devices, and the source and drain material is source 131 or drain 132 is P-doped silicon germanium, such as boron doped silicon germanium, siGe, for P-type semiconductor devices: B. for N-type semiconductor devices, the source and drain materials are N-type doped silicon, such as phosphorus doped silicon or phosphorus doped silicon carbide, i.e., si: p or SiC: p.

In an embodiment of the present application, after forming the source electrode 131 and the drain electrode 132, the dummy gate 204 may be removed, as shown with reference to fig. 27, 28, and 29B.

In an embodiment of the present application, an isolation layer 207 may be deposited on the surfaces of the dummy gate 204, the source electrode 131, and the drain electrode 132, to prevent an interconnection short between the dummy gate 204 and the source electrode 131 or the drain electrode 132 in a subsequent step, and the isolation layer 207 may be subjected to a chemical mechanical polishing process to planarize it. Then, as shown in fig. 27, 28 and 29B, the dummy gate 204 formed of the foregoing polysilicon or amorphous silicon is etched or etched away, that is, the dummy gate 204 is removed, by a selective etching or etching process.

S106, the first semiconductor layer 121 is replaced with the gate electrode 160, as shown with reference to fig. 27 to 29.

In an embodiment of the present application, the first semiconductor layer 121 may be replaced with a gate electrode 160, as shown with reference to fig. 27 to 29.

The specific process flow is as follows:

S1061, the first semiconductor layer 121 of the channel region 103 is removed, as shown with reference to fig. 27 to 29.

In an embodiment of the present application, the first semiconductor layer 121 of the channel region 103 may be removed, i.e., a nano-sheet channel release process may be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, as shown with reference to fig. 27-29.

Specifically, the first semiconductor layer 121 in the stacked structure of the channel region 103 may be selectively etched to perform the nano-sheet channel release. That is, the stacked structure exposed by the fins is processed, the first semiconductor layer 121 of each layer is removed, the first semiconductor layer 121 is a sacrificial layer, and the nano-sheets formed by the second semiconductor layer 122 are released.

In embodiments of the present application, there are several possible implementations of the nanoplatelet channel release for different types of devices:

in a first possible implementation, for both P-type and N-type semiconductor devices, the material of the first semiconductor layer 121, i.e., the sacrificial layer, is silicon germanium, which is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nano-sheet stack device. An etchant that selectively etches silicon germanium at a faster rate relative to silicon may be used in the selective removal process.

In a second possible implementation, for P-type semiconductor devices, the material of the first semiconductor layer 121, i.e., the sacrificial layer, is silicon, and the silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon germanium, to form a silicon germanium stacked nano-sheet stack device. An etchant that selectively etches silicon at a faster rate relative to silicon germanium may be used in the selective removal process.

In a third possible implementation, for an N-type semiconductor device, the material of the first semiconductor layer 121, i.e., the sacrificial layer, is silicon germanium, and the silicon germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nano-sheet stack device. An etchant that selectively etches silicon germanium at a faster rate relative to silicon may be used in the selective removal process.

At S1062, a high-k dielectric layer 150 is formed on the surface of the second semiconductor layer 122, as shown with reference to fig. 30-32.

In an embodiment of the present application, after the first semiconductor layer 121 is removed, a high-k dielectric layer 150 may be further formed on the surface of the second semiconductor layer 122, and the high-k dielectric layer 150 surrounds the surface of the second semiconductor layer 122. Specifically, the material of the high-k dielectric layer 150 may be HfO₂、HfSiO_x、HfON、HfSiON、HfAlO_x、HfLaO_x、Al₂O₃、ZrO₂、ZrSiO_x、Ta₂O₅ or one or a combination of several La ₂O₃.

In an embodiment of the present application, high-k dielectric layer 150 may further include an interface oxide layer (IL) (not shown).

S1063, filling the gate 160 in the plurality of gaps to be filled 402, as shown with reference to fig. 30-32.

In the embodiment of the present application, after the nano-sheet channel release is performed, the plurality of gaps 402 to be filled are formed between the plurality of second semiconductor layers 122, and the gate 160 may be filled in the plurality of gaps 402 to be filled, and the gate 160 surrounds the second semiconductor layers 122, so as to form a gate-all-around structure. The stack of the plurality of second semiconductor layers 122 forms a channel structure, i.e., a nanoplate channel of the semiconductor device, as shown with reference to fig. 30-32.

In an embodiment of the present application, the gate electrode 160 may further include a diffusion barrier layer, a work function layer, a conductive filling layer, and the like (not shown).

In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 may cover the space after the isolation layer 207 and the dummy gate 204 are removed, and the gate 160 covered with the isolation layer 207 may be subjected to chemical mechanical polishing and planarization.

In an embodiment of the present application, after forming gate 160, a dielectric deposition may be performed on top of the semiconductor device away from substrate 110 to form a top dielectric layer 170, as shown with reference to fig. 3-6.

In the embodiment of the present application, contact hole etching is performed in the top dielectric layer 170, etching is performed to the surface of the source electrode 131 or the drain electrode 132, a metal material is deposited in the contact hole, and a contact electrode 180 of the source electrode 131 or the drain electrode 132 is formed, as shown in fig. 3 to 6, and then, a multi-layer subsequent interconnection and passivation protection process is completed.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for structural embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and reference is made to the description of method embodiments for relevant points.

The foregoing is merely a preferred embodiment of the present application, and the present application has been disclosed in the above description of the preferred embodiment, but is not limited thereto. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, the semiconductor device comprising:

A gate surrounding the nanoplatelets.

2. The semiconductor device of claim 1, wherein one side of the isolation structure is in contact with the source and the other side of the isolation structure is in contact with the drain in a direction parallel to the plane of the substrate.

3. The semiconductor device according to claim 2, wherein the substrate includes a third substrate which is located on a side of the second substrate away from the first substrate, the third substrate and the source and the drain do not overlap, and a material of the third substrate is a semiconductor material;

4. The semiconductor device according to claim 1, wherein the substrate includes a third substrate which is located on a side of the second substrate away from the first substrate, the third substrate and the source and the drain do not overlap, and a material of the third substrate is a semiconductor material; the isolation structure comprises a first isolation structure and a second isolation structure;

5. The semiconductor device of claim 4, wherein the first isolation structure and the second isolation structure comprise a first sidewall proximate the channel structure in a direction parallel to the plane of the substrate, the first sidewall and the sidewall of the channel structure being flush in a direction perpendicular to the plane of the substrate.

6. The semiconductor device according to any one of claims 1 to 5, wherein the isolation structure includes a first isolation portion and a second isolation portion, the first isolation portion being located on a side of the second isolation portion remote from the substrate;

7. The semiconductor device of any of claims 1-5, wherein the isolation structure is a low-k dielectric material.

8. A method of manufacturing a semiconductor device, the method comprising:

filling insulating materials in the grooves to form isolation structures;

9. The method of manufacturing according to claim 8, wherein the etching to remove the third substrate located in the source region and the drain region, etching to remove all or part of the third substrate in a direction toward the channel region on a plane parallel to the substrates, forming a recess includes:

10. The method of manufacturing of claim 9, wherein prior to etching away the third substrate at the source region and the drain region, the method further comprises: