CN117059573A - Method for forming semiconductor structure - Google Patents
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- CN117059573A CN117059573A CN202210497866.2A CN202210497866A CN117059573A CN 117059573 A CN117059573 A CN 117059573A CN 202210497866 A CN202210497866 A CN 202210497866A CN 117059573 A CN117059573 A CN 117059573A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein a plurality of channel structures and a plurality of pseudo gate structures crossing the channel structures are formed on the substrate, active drain doping areas are formed in the channel structures at two sides of the pseudo gate structures, and an interlayer dielectric layer covering the active drain doping areas is formed at the side parts of the pseudo gate structures; the substrate comprises a plurality of device unit areas and partition areas positioned between the device unit areas, and the device unit areas and the partition areas are arranged along the extending direction of the channel structure; removing the pseudo gate structure in the device unit area, and forming a gate opening in the interlayer dielectric layer in the device unit area; filling a gate material layer in the gate opening; removing the pseudo gate structure and the channel structure which are positioned in the partition area to form a partition opening; and filling the partition opening with a partition structure. The embodiment of the invention forms the partition structure so as to realize isolation between adjacent device unit areas, and is also beneficial to enlarging a process window for forming the partition structure.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the improvement of the density and the integration level of the semiconductor device, the gate size of the planar transistor is also shorter and shorter, the control capability of the conventional planar transistor on the channel current is weakened, a short channel effect occurs, the leakage current is increased, and the electrical performance of the semiconductor device is finally affected.
To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as: fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
However, as semiconductor device dimensions continue to shrink, the distance between adjacent field effect transistors also shrinks. To prevent bridging (Bridge) between adjacent devices, fabrication techniques of single diffusion barrier isolation structures (Single diffusion break isolation structures, DDB isolation structures) have been introduced to achieve the isolation of adjacent device cells.
However, the process window currently forming the partition structure is small.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, forming a partition structure so as to realize isolation between adjacent device unit areas, and is also beneficial to enlarging a process window for forming the partition structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a plurality of channel structures and a plurality of pseudo gate structures crossing the channel structures are formed on the substrate, active drain doping regions are formed in the channel structures at two sides of the pseudo gate structures, and interlayer dielectric layers covering the active drain doping regions are formed at the side parts of the pseudo gate structures; the substrate comprises a plurality of device unit areas and partition areas positioned among the device unit areas, and the device unit areas and the partition areas are arranged along the extending direction of the channel structure; removing the pseudo gate structure in the device unit area, and forming a gate opening in the interlayer dielectric layer in the device unit area; filling a gate material layer in the gate opening; removing the pseudo gate structure and the channel structure which are positioned in the partition area to form a partition opening; and filling a partition structure in the partition opening.
Optionally, the method for forming the semiconductor structure further includes: forming a hard mask layer on top of the dummy gate structure in the isolation region after providing the substrate and before removing the dummy gate structure in the device cell region; in the step of forming the gate material layer, the gate material layer is further formed on the interlayer dielectric layer at the side part of the hard mask layer; after forming the gate material layer and before removing the dummy gate structure in the isolation region, the hard mask layer is removed.
Optionally, the step of forming the gate material layer includes: filling an initial gate material layer in the gate opening, wherein the initial gate material layer is also formed on the interlayer dielectric layer and covers the hard mask layer; and taking the top surface of the hard mask layer as a stop position, carrying out first planarization treatment on the initial gate material layer, and taking the rest initial gate material layer as the gate material layer.
Optionally, the first planarization process includes a chemical mechanical planarization process.
Optionally, the material of the hard mask layer includes one or more of silicon nitride, aluminum oxide, aluminum nitride and carbon doped silicon nitride.
Optionally, the process of removing the hard mask layer includes an isotropic etching process.
Optionally, the isotropic etching process includes one or both of a dry etching process and a wet etching process.
Optionally, in the step of filling the gate opening with a gate material layer, the gate material layer is further formed on the interlayer dielectric layer; the step of filling the partition opening with the partition structure comprises the following steps: filling a dielectric material layer in the partition opening, wherein the dielectric material layer is also formed on the grid material layer; and taking the top surface of the interlayer dielectric layer as a stop position, carrying out second planarization treatment on the gate material layer and the dielectric material layer, wherein the rest gate material layer is used as a gate structure, and the rest dielectric material layer is used as a partition structure.
Optionally, the step of performing a second planarization process on the gate material layer and the dielectric material layer includes: taking the top surface of the grid electrode material layer as a stop position, and performing first sub-planarization treatment on the dielectric material layer; and taking the top surface of the interlayer dielectric layer as a stop position, and performing second sub-planarization treatment on the dielectric material layer and the gate material layer.
Optionally, the process of the second planarization treatment includes a chemical mechanical planarization process.
Optionally, in the step of providing a substrate, the substrate further has a plurality of discrete protrusions formed thereon; the channel structure is positioned on the protruding part; an isolation layer surrounding the convex part is also formed on the substrate; the dummy gate structure is positioned on the isolation layer and spans the channel structure; the interlayer dielectric layer is positioned on the isolation layer at the side part of the pseudo gate structure; in the step of forming the partition opening, the partition opening also penetrates through a part of the thickness of the partition region by the boss.
Optionally, the step of forming the gate material layer includes: forming a gate dielectric layer at the bottom and the side wall of the gate opening; forming a work function layer on the gate dielectric layer; an electrode material layer filling the gate opening is formed on the work function layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the pseudo gate structure positioned in the device unit area is removed, a gate opening is formed in the interlayer dielectric layer positioned in the device unit area, after the gate material layer is filled in the gate opening, the pseudo gate structure and the channel structure positioned in the partition area are removed to form a partition opening, and then the partition opening is filled with a partition structure which is used as a single diffusion partition (Single Diffusion Break, SDB) isolation structure, so that the partition between adjacent device unit areas can be realized; in addition, since the material of the dummy gate structure is different from that of the gate material layer, the dummy gate structure and the gate material layer have a higher etching selection ratio, so that the requirement on alignment deviation (Overlay shift) for forming the partition opening can be reduced by removing the dummy gate structure and the channel structure located in the partition region after the gate material layer is formed, and the process window for forming the partition structure is correspondingly increased.
Drawings
Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the process window for forming the partition structure is small.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a plurality of channel structures and a plurality of pseudo gate structures crossing the channel structures are formed on the substrate, active drain doping regions are formed in the channel structures at two sides of the pseudo gate structures, and interlayer dielectric layers covering the active drain doping regions are formed at the side parts of the pseudo gate structures; the substrate comprises a plurality of device unit areas and partition areas positioned among the device unit areas, and the device unit areas and the partition areas are arranged along the extending direction of the channel structure; removing the pseudo gate structure in the device unit area, and forming a gate opening in the interlayer dielectric layer in the device unit area; filling a gate material layer in the gate opening; removing the pseudo gate structure and the channel structure positioned in the partition area after the gate material layer is formed, so as to form a partition opening; and filling a partition structure in the partition opening.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the pseudo gate structure positioned in the device unit area is removed, a gate opening is formed in the interlayer dielectric layer positioned in the device unit area, after the gate material layer is filled in the gate opening, the pseudo gate structure and the channel structure positioned in the partition area are removed to form a partition opening, and then the partition opening is filled with a partition structure which is used as a single diffusion partition (Single Diffusion Break, SDB) isolation structure, so that the partition between adjacent device unit areas can be realized; in addition, since the material of the dummy gate structure is different from that of the gate material layer, the dummy gate structure and the gate material layer have a higher etching selection ratio, so that the requirement on alignment deviation (Overlay shift) for forming the partition opening can be reduced by removing the dummy gate structure and the channel structure located in the partition region after the gate material layer is formed, and the process window for forming the partition structure is correspondingly increased.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, which shows a cross-sectional view along the extending direction of a channel structure, a substrate (not shown) is provided, a plurality of channel structures 110 and a plurality of dummy gate structures 120 crossing the channel structures 110 are formed on the substrate, source and drain doped regions 140 are formed in the channel structures 110 at both sides of the dummy gate structures 120, and an interlayer dielectric layer 150 covering the source and drain doped regions 140 is formed at the side of the dummy gate structures 120; the substrate includes a plurality of device cell regions I and partition regions II between the device cell regions I, the device cell regions I and the partition regions II being aligned along an extension direction of the channel structure 110.
The substrate is used for providing a process platform for a subsequent process.
In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is monocrystalline silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. The substrate can also be a silicon-on-insulator substrate or other types of substrates such as a germanium-on-insulator substrate.
The device unit area I is used for forming a device unit. As an example, the device Cell area I is a Standard Cell (Standard Cell).
And the partition area II is used for realizing partition between adjacent device units.
In this embodiment, in the step of providing the substrate, a plurality of discrete protruding portions (not shown) are further formed on the substrate.
The bosses are used to support the channel structure 110. The raised portions also serve to form an isolation layer to provide space so that the isolation layer can surround the raised portions and expose the channel structure 110, and to enable the isolation layer to isolate the substrate from subsequently formed gate structures.
In this embodiment, the protruding portion and the substrate are of an integral structure, and the protruding portion and the substrate are made of the same material and are all made of silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
The channel structure 110 is used to provide a conductive channel of a field effect transistor.
In this embodiment, the channel structure 110 is located on the protruding portion.
In this embodiment, the materials of the channel structure 110 include: single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. In this embodiment, the material of the channel structure 110 is monocrystalline silicon.
In this embodiment, a fin field effect transistor (FinFET) is formed as an example. In the fin field effect transistor, the gate structure spans across the fin portion and covers part of the top and the side wall of the fin portion, and the gate structure can control the fin portion from three sides, so that the control capability of the gate structure on a channel is improved, short channel effect is restrained, and the performance of a device is improved.
Correspondingly, the channel structure is a fin portion, and the fin portion is used for providing a conducting channel of the fin field effect transistor. In this embodiment, the fin portion and the protruding portion are of an integral structure, and the fin portion and the protruding portion are made of the same material.
In other embodiments, the channel structure may be other types of channel structures when forming other types of field effect transistors, respectively.
For example: when forming a fully-enclosed Gate (GAA) transistor or a nano-sheet field effect transistor (nanosheet field effect transistor, NSFET), the channel structure is suspended at intervals on the protruding portion, the channel structure includes one or more channel layers suspended at intervals in sequence, and the stacking direction of the channel layers is perpendicular to the surface of the substrate. The channel layer is used to provide a conductive channel for a fully surrounding gate transistor or a nanoflake field effect transistor.
In the step of providing the substrate, a sacrificial layer is further formed between the channel structure and the protruding portion or between adjacent channel layers in the channel structure, the sacrificial layer is used for supporting the channel layers, so that a process foundation is provided for the space suspension arrangement of the channel layers to be realized later, and the sacrificial layer is further used for occupying space positions for the gate structure to be formed later.
In this embodiment, an isolation layer 115 surrounding the protruding portion is further formed on the substrate. The isolation layer 115 exposes the channel structure 110.
The isolation layer 115 is used to isolate adjacent raised portions and also to isolate the substrate from subsequently formed gate structures.
In this embodiment, the material of the isolation layer 115 is silicon oxide. The material of the isolation layer may also be other insulating materials, such as: one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon germanium oxide, boron nitride, boron carbonitride, and silicon germanium oxide.
The dummy gate structure 120 is used to occupy a spatial position for subsequent gate structure formation.
In this embodiment, the dummy gate structure 120 is located on the isolation layer 115 and spans the channel structure 110. Specifically, in this embodiment, the dummy gate structure 120 spans across the fin portion and covers a portion of the top and a portion of the sidewall of the fin portion.
In this embodiment, the dummy gate structure 120 includes a dummy gate oxide layer (not shown) and a dummy gate layer on the dummy gate oxide layer.
As one example, the material of the dummy gate oxide layer includes one or more of silicon oxide, silicon oxynitride, and silicon nitride.
As an example, the material of the dummy gate layer includes polysilicon.
In this embodiment, a sidewall 130 is further formed on the sidewall of the dummy gate structure 120.
The side wall 130 is used for protecting the side wall of the dummy gate structure 120, and the side wall 130 is also used for defining the formation position of the source-drain doped region 140.
The material of the side wall 130 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the side wall 130 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 130 is a single-layer structure, and the material of the side wall 130 is silicon nitride.
The source-drain doped regions 140 are used to provide a source of carriers during operation of the device.
In this embodiment, the source-drain doped region 140 includes a stress layer doped with ions, and the source-drain doped region 140 is further configured to provide stress to the channel, thereby improving carrier mobility of the channel.
Specifically, when forming the NMOS transistor, the material of the source-drain doped region 140 is a stress layer doped with N-type ions, where the material of the stress layer includes Si or SiC, and the stress layer provides a tensile stress effect for the channel region of the NMOS transistor, so As to facilitate improving the carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions.
When forming a PMOS transistor, the material of the source-drain doped region 140 is a stress layer doped with P-type ions, where the material of the stress layer includes Si or SiGe, and the stress layer provides a compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, where the P-type ions are B ions, ga ions, or In ions.
In this embodiment, the source-drain doped regions 140 are located in fin portions at two sides of the dummy gate structure 120.
The interlayer dielectric layer 150 is used to isolate adjacent devices from each other. In this embodiment, the interlayer dielectric layer 150 is formed on the isolation layer on the side of the dummy gate structure.
Thus, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.
Referring to fig. 2, the method for forming the semiconductor structure further includes: after providing the substrate, a hard mask layer 160 is formed on top of the dummy gate structure 120 at the isolation region II.
The hard mask layer 160 is used for protecting the dummy gate structure 120 located in the isolation region II in the subsequent steps of removing the dummy gate structure 120 located in the device cell region II to form a gate opening and filling a gate material layer in the gate opening.
For this purpose, the hard mask layer 160 is made of a material having etching selectivity to the dummy gate structure 120 and the gate material layer, so as to ensure the protection of the hard mask layer 160 on the dummy gate structure 120 located in the isolation region II.
In this embodiment, the material of the hard mask layer 160 includes one or more of silicon nitride, aluminum oxide, aluminum nitride and carbon doped silicon Nitride (NDC). As an example, the material of the hard mask layer 160 is silicon nitride.
In this embodiment, the step of forming the hard mask layer 160 includes: forming a hard mask material layer (not shown) on the interlayer dielectric layer 150 to cover the dummy gate structure 120; and removing the hard mask material layer located in the device unit area I, and reserving the residual hard mask material layer located on the dummy gate structure 120 of the isolation area II as the hard mask layer 160.
In this embodiment, the process of forming the hard mask material layer includes a chemical vapor deposition process. The chemical vapor deposition process has high process compatibility and low process cost.
In this embodiment, an anisotropic etching process is used to remove the hard mask material layer located in the device unit area I. As an example, the anisotropic etching process is a dry etching process. The pattern transfer precision and the etching efficiency of the dry etching process are high.
In this embodiment, during the process of forming the hard mask layer 160, the hard mask layer 160 also covers a portion of the top of the interlayer dielectric layer, so as to reduce the requirement for an overlay shift (overlay shift) of the forming process of the hard mask layer 160, and further increase the process window for forming the hard mask layer 160.
Referring to fig. 3, the dummy gate structure 120 located in the device cell region I is removed, and a gate opening 170 is formed in the interlayer dielectric layer 150 located in the device cell region I.
The gate opening 170 is used to provide a spatial location for forming a gate structure.
In this embodiment, the gate opening 170 spans across the fin and exposes a portion of the top and a portion of the sidewalls of the fin.
In this embodiment, one or both of a dry etching process and a wet etching process are used to remove the dummy gate structure 120 located in the device cell area I.
Referring to fig. 4-5, a gate material layer 180 is filled in the gate opening 170.
The gate material layer 180 is used for subsequent formation of a gate structure.
In this embodiment, in the step of forming the gate material layer 180, the gate material layer 180 is further formed on the interlayer dielectric layer 160 at the side of the hard mask layer 160, so that in the step of removing the hard mask layer 160 and the dummy gate structure 120 of the isolation region II, the gate material layer 180 located on the interlayer dielectric layer 160 can protect the top of the interlayer dielectric layer 160.
In addition, the gate material layer 180 is further formed on the interlayer dielectric layer 160 at the side of the hard mask layer 160, so that the top surface of the semiconductor structure is two film layers of the gate material layer 180 and the hard mask layer 160, and in the subsequent process of removing the hard mask layer 160, the process of removing the hard mask layer 160 only needs to have an etching selection ratio between the hard mask layer 160 and the gate material layer 180, thereby reducing the difficulty of the subsequent process of removing the hard mask layer 160.
Similarly, after the hard mask layer 160 is removed later, in the step of removing the dummy gate structure 120 of the isolation region II, the exposed film layer of the semiconductor structure is less in kind, which is also beneficial to reducing the difficulty of removing the dummy gate structure 120 located in the isolation region II.
In this embodiment, the gate material layer is used to form a metal gate structure (Metal Gate Structure); the step of forming the gate material layer 180 includes: forming a gate dielectric layer (not shown) at the bottom and sidewalls of the gate opening 170; forming a work function layer (not shown) on the gate dielectric layer; an electrode material layer (not shown) filling the gate opening is formed on the work function layer.
In this embodiment, the gate material layer is further formed on the interlayer dielectric layer 150 at the side of the hard mask layer 160, so that the exposed top surface of the gate material layer is a single electrode material layer, which makes the exposed types of the semiconductor structure less, and is further beneficial to further reducing the difficulty in the subsequent process of removing the hard mask layer 160 and removing the dummy gate structure 120 located in the isolation region II.
The gate dielectric layer is used to electrically insulate the work function layer and the electrode material layer from the channel structure 110.
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer. The high-k gate dielectric layer is made of a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer is HfO 2 . In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer. Wherein the material of the gate oxide layer comprises one or two of silicon oxide and silicon oxynitride.
The work function layer is used for adjusting the work function of the metal gate structure, so that the effect of adjusting the threshold voltage of the transistor is achieved. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer comprises one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
The electrode material layer is used as an electrode and is used for leading out the electricity of the metal gate structure, so that the metal gate structure is electrically connected with an external circuit.
In this embodiment, the electrode material layer is made of W. In other embodiments, the material of the electrode material layer may also be Al, cu, ag, au, pt, ni or Ti, etc.
Specifically, in this embodiment, the step of forming the gate material layer 180 includes:
as shown in fig. 4, an initial gate material layer 175 is filled in the gate opening 170, and the initial gate material layer 175 is further formed on the interlayer dielectric layer 150 and covers the hard mask layer 160.
The initial gate material layer 175 is used for subsequent formation of gate material layers.
Specifically, a gate dielectric layer is conformally covered on the bottom and sidewalls of the gate opening 170, and the gate dielectric layer is also conformally covered on the interlayer dielectric layer 150 and the hard mask layer 160; conformally covering a work function layer on the gate dielectric layer; a layer of electrode material filling the gate opening 170 is formed on the work function layer.
As shown in fig. 5, the initial gate material layer 175 is subjected to a first planarization process with the top surface of the hard mask layer 160 as a stop position, and the remaining initial gate material layer 175 is used as the gate material layer 180.
And taking the top surface of the hard mask layer 160 as a stop position, performing a first planarization treatment on the initial gate material layer 175, so that the top surface flatness of the gate material layer 180 can be improved while removing the initial gate material layer 175 higher than the top surface of the hard mask layer 160 to expose the hard mask layer 160, thereby being beneficial to improving the top surface flatness of the subsequently formed gate structure.
In this embodiment, the first planarization process includes a chemical mechanical planarization process. The chemical mechanical planarization process is a global planarization process, has higher planarization efficiency, and is beneficial to improving the surface flatness of the planarized film, so that the chemical mechanical planarization process is selected to be beneficial to removing the initial gate material layer 175 higher than the top surface of the hard mask layer 160, improving the surface flatness of the gate material layer 180 and the hard mask layer 160, and meeting the requirements of high planarization, low surface roughness and low defects of the surface of the gate material layer 180, so that a flat top surface is provided for the subsequent process, thereby facilitating the subsequent process.
In this embodiment, the fin field effect transistor is formed as an example.
In other embodiments, for example: when forming a fully-surrounding Gate (GAA) transistor or a nano-sheet field effect transistor (nanosheet field effect transistor, NSFET), the method of forming a semiconductor structure further includes, when a sacrificial layer is further formed between the channel structure and the raised portion or between adjacent ones of the channel layers in the channel structure: after the gate opening is formed and before the gate material layer is filled in the gate opening, the sacrificial layer is removed, and a through groove is formed, wherein the through groove is communicated with the gate opening.
And removing the sacrificial layer, thereby realizing the interval suspension arrangement of the channel layer.
Correspondingly, in the step of forming the gate material layer, the gate material layer is also filled in the through groove, and the gate material layer surrounds the channel layer.
Referring to fig. 6, after the gate material layer 180 is formed, the hard mask layer 160 is removed.
The hard mask layer 160 is removed to expose the top surface of the dummy gate structure 120 in the isolation region II, thereby facilitating subsequent removal of the dummy gate structure 120 in the isolation region II.
In this embodiment, the process of removing the hard mask layer 160 includes an isotropic etching process.
As an example, the isotropic etching process includes one or both of a dry etching process and a wet etching process.
Referring to fig. 7, the dummy gate structure 120 and the channel structure 110 located in the isolation region II are removed to form an isolation opening 190.
The partition openings 190 are used to provide spatial locations for forming the partition structure.
In this embodiment, since the materials of the dummy gate structure 120 and the gate material layer 180 are different, the dummy gate structure 120 and the gate material layer 180 have a higher etching selectivity ratio, so that by removing the dummy gate structure 120 and the channel structure 110 in the isolation region II after forming the gate material layer 180, the requirement on the alignment deviation (Overlay shift) of forming the isolation opening 190 can be reduced, and the process window of forming the isolation structure can be correspondingly increased.
In this embodiment, the gate material layer 190 is further located on the interlayer dielectric layer 150 at the side of the hard mask layer 160, so that the dummy gate structure 120 located in the isolation region II can be removed by using the gate material layer as a mask, which is beneficial to reducing the probability of damage to other film layers.
In this embodiment, in the step of forming the partition opening 190, the partition opening 190 also penetrates through a part of the thickness of the partition area II by the protruding portion.
In this embodiment, one or both of a dry etching process and a wet etching process are used to remove the dummy gate structure 120 and the channel structure 110 located in the isolation region II.
Referring to fig. 8 to 10, the partition opening 190 is filled with a partition structure 200.
In this embodiment, the dummy gate structure 120 located in the device unit area I is removed, a gate opening 170 is formed in the interlayer dielectric layer 150 located in the device unit area I, and after the gate material layer 180 is filled in the gate opening 170, the dummy gate structure 120 and the channel structure 110 located in the isolation area II are removed, a partition opening 190 is formed, and then a partition structure 200 is filled in the partition opening 190, where the partition structure 200 serves as a single diffusion partition (Single Diffusion Break, SDB) isolation structure, so that a partition between adjacent device unit areas I can be achieved.
In addition, in this embodiment, by removing the dummy gate structure 120 and the channel structure 110 located in the isolation region II after the gate material layer 180 is formed, a requirement for an alignment deviation (Overlay shift) of forming the isolation opening 190 can be reduced, and a process window of forming the isolation structure 200 can be correspondingly increased.
For this reason, the material of the partition structure 200 is a dielectric material, so that the partition structure 200 has an insulating property, thereby preventing bridging between adjacent devices. Specifically, the material of the partition structure 200 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and silicon boron carbide nitride, and the partition structure 200 may have a single-layer or multi-layer structure.
In this embodiment, the partition structure 200 is a single-layer structure, and the material of the partition structure 200 is silicon oxide. Silicon oxide is an easily available insulating material, which is beneficial to reducing the cost of the partition structure 200 and improving the process compatibility, and the dielectric constant of the silicon oxide material is lower, which is beneficial to improving the isolation effect of the partition structure 200 on the adjacent device unit areas I.
In this embodiment, the step of filling the partition structure 200 in the partition opening 190 includes:
as shown in fig. 8, a dielectric material layer 210 is filled in the partition openings 190, and the dielectric material layer 210 is further formed on the gate material layer 180.
In this embodiment, the process of forming the dielectric material layer 210 includes one or more of a chemical vapor deposition process, a flow-type chemical vapor deposition process, a high aspect ratio process, an atomic layer deposition process, a spin-on process, a plasma enhanced chemical vapor deposition process, and a low pressure chemical vapor deposition process.
The process of forming the dielectric material layer 210 has higher gap filling capability, so that in the case that the opening width of the partition opening 190 is smaller than that of the prior art, the filling quality of the dielectric material layer 210 in the partition opening 190 is also improved, the probability of generating defects such as voids (Void) in the dielectric material layer 210 is reduced, the film forming quality of the partition structure 200 is correspondingly improved, and the isolation effect of the partition structure 200 on adjacent device unit areas is further improved.
As shown in fig. 9 to 10, with the top surface of the interlayer dielectric layer 150 as a stop position, the gate material layer 180 and the dielectric material layer 210 are subjected to a second planarization process, the remaining gate material layer 180 is used as a gate structure 220, and the remaining dielectric material layer 210 is used as the partition structure 200.
Wherein the gate structure 220 is used to control the on and off of the conductive channel.
In this embodiment, the gate structure 220 is a metal gate structure. The gate structure 220 includes a gate dielectric layer, a work function layer on the gate dielectric layer, and an electrode material layer on the work function layer and filling the gate opening. For detailed descriptions of the gate dielectric layer, the work function layer and the electrode material layer, please refer to the corresponding descriptions, and the detailed descriptions are omitted herein.
In this embodiment, the gate structure 220 is located on the isolation layer 115 and spans a portion of the top and a portion of the sidewalls of the fin. In other embodiments, when the channel structure includes one or more channel layers spaced apart and suspended, the gate structure spans the channel structure and surrounds the channel layer.
In this embodiment, during the process of forming the isolation structure 200, the gate material layer 180 on the top surface of the interlayer dielectric layer 150 is also removed to form the gate structure 220, so that the process of forming the isolation structure 200 is integrated with the process of forming the gate structure 220, which improves the process integration degree and the process compatibility, and is also beneficial to simplifying the process.
The process of the second planarization process includes a chemical mechanical planarization process. The chemical mechanical planarization process is a global planarization process, has high planarization efficiency, and is beneficial to improving the surface flatness of the planarized film, so that the chemical mechanical planarization process is selected to be beneficial to removing the dielectric material layer 210 and the gate material layer 180 higher than the top surface of the interlayer dielectric layer 150, and simultaneously to improving the surface flatness of the partition structure 200, the interlayer dielectric layer 150 and the gate structure 220, and further to provide a flat top surface for the subsequent process, so as to facilitate the subsequent process.
More specifically, in this embodiment, the step of performing the second planarization process on the gate material layer 180 and the dielectric material layer 210 includes: as shown in fig. 9, the dielectric material layer 210 is subjected to a first sub-planarization process with the top surface of the gate material layer 180 as a stop position; as shown in fig. 10, the second sub-planarization process is performed on the dielectric material layer 210 and the gate material layer 180 with the top surface of the interlayer dielectric layer 150 as a stop position.
In this embodiment, the first sub-planarization process and the second sub-planarization process are both chemical mechanical planarization processes.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (12)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a plurality of channel structures and a plurality of pseudo gate structures crossing the channel structures are formed on the substrate, active drain doping regions are formed in the channel structures at two sides of the pseudo gate structures, and interlayer dielectric layers covering the active drain doping regions are formed at the side parts of the pseudo gate structures; the substrate comprises a plurality of device unit areas and partition areas positioned among the device unit areas, and the device unit areas and the partition areas are arranged along the extending direction of the channel structure;
removing the pseudo gate structure in the device unit area, and forming a gate opening in the interlayer dielectric layer in the device unit area;
filling a gate material layer in the gate opening;
removing the pseudo gate structure and the channel structure which are positioned in the partition area to form a partition opening;
and filling a partition structure in the partition opening.
2. The method of forming a semiconductor structure of claim 1, further comprising: forming a hard mask layer on top of the dummy gate structure in the isolation region after providing the substrate and before removing the dummy gate structure in the device cell region;
in the step of forming the gate material layer, the gate material layer is further formed on the interlayer dielectric layer at the side part of the hard mask layer;
after forming the gate material layer and before removing the dummy gate structure in the isolation region, the hard mask layer is removed.
3. The method of forming a semiconductor structure of claim 2, wherein the step of forming the layer of gate material comprises: filling an initial gate material layer in the gate opening, wherein the initial gate material layer is also formed on the interlayer dielectric layer and covers the hard mask layer;
and taking the top surface of the hard mask layer as a stop position, carrying out first planarization treatment on the initial gate material layer, and taking the rest initial gate material layer as the gate material layer.
4. The method of forming a semiconductor structure of claim 3, wherein the process of the first planarization process comprises a chemical mechanical planarization process.
5. The method of forming a semiconductor structure of claim 2, wherein the material of the hard mask layer comprises one or more of silicon nitride, aluminum oxide, aluminum nitride, and carbon-doped silicon nitride.
6. The method of forming a semiconductor structure of claim 2, wherein the process of removing the hard mask layer comprises an isotropic etching process.
7. The method of forming a semiconductor structure of claim 6, wherein the isotropic etching process comprises one or both of a dry etching process and a wet etching process.
8. The method of forming a semiconductor structure as claimed in any one of claims 1 to 7, wherein in the step of filling a gate material layer in the gate opening, the gate material layer is further formed on the interlayer dielectric layer;
the step of filling the partition opening with the partition structure comprises the following steps: filling a dielectric material layer in the partition opening, wherein the dielectric material layer is also formed on the grid material layer; and taking the top surface of the interlayer dielectric layer as a stop position, carrying out second planarization treatment on the gate material layer and the dielectric material layer, wherein the rest gate material layer is used as a gate structure, and the rest dielectric material layer is used as a partition structure.
9. The method of forming a semiconductor structure of claim 8, wherein performing a second planarization process on the gate material layer and the dielectric material layer comprises: taking the top surface of the grid electrode material layer as a stop position, and performing first sub-planarization treatment on the dielectric material layer;
and taking the top surface of the interlayer dielectric layer as a stop position, and performing second sub-planarization treatment on the dielectric material layer and the gate material layer.
10. The method of forming a semiconductor structure of claim 8, wherein the process of the second planarization process comprises a chemical mechanical planarization process.
11. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate further has a plurality of discrete protrusions formed thereon; the channel structure is positioned on the protruding part; an isolation layer surrounding the convex part is also formed on the substrate; the dummy gate structure is positioned on the isolation layer and spans the channel structure; the interlayer dielectric layer is positioned on the isolation layer at the side part of the pseudo gate structure;
in the step of forming the partition opening, the partition opening also penetrates through a part of the thickness of the partition region by the boss.
12. The method of forming a semiconductor structure of claim 1, wherein forming the layer of gate material comprises: forming a gate dielectric layer at the bottom and the side wall of the gate opening; forming a work function layer on the gate dielectric layer; an electrode material layer filling the gate opening is formed on the work function layer.
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