CN116031301A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN116031301A CN116031301A CN202211490576.1A CN202211490576A CN116031301A CN 116031301 A CN116031301 A CN 116031301A CN 202211490576 A CN202211490576 A CN 202211490576A CN 116031301 A CN116031301 A CN 116031301A
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Abstract
The embodiment of the application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a substrate, a source electrode, a drain electrode and a channel structure, wherein the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is arranged between the source electrode and the drain electrode, the channel structure comprises a lamination formed by a plurality of nano sheets, a grid electrode surrounds the nano sheets, a cavity is arranged at least between the channel structure and the substrate, the cavity is formed by surrounding the channel structure, the source electrode, the drain electrode and the substrate, namely, the cavity is arranged below the channel structure, the source electrode and the drain electrode and is not in contact with a film layer, so that a full floating structure is formed, the gate control performance of the semiconductor device can be greatly improved, the subthreshold swing amplitude of the semiconductor device is reduced, the leakage current and parasitic capacitance are reduced, the driving current is increased, and the performance of the semiconductor device is improved.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
With the development of semiconductor technology, the feature size of integrated circuits is continuously shrinking, and the conventional tri-gate or dual-gate Fin Field effect transistor (FinFET) is limited below 3 nanometers (nm), and the Nanosheet ring gate transistor (Nanosheet-Gate all round Fin Field-Effect Transistor, nanosheet-GAAFET) breaks through the limitation of the 3nm node, so that the semiconductor device is widely focused and studied.
Nanosheet-GAAFET is a novel device with a circular gate structure and horizontal Nanoplatelets (NS) as conductive channels. In the aspect of gate control, the gate-surrounding structure has better gate control capability than a FinFET device structure, short channel effect of the device can be effectively inhibited, in the aspect of current driving, nanosheet-GAAFET has inversion carriers of 'body inversion', and the current driving performance of the device can be remarkably enhanced through the increase of effective gate width and the design of nano sheet stacking in the vertical direction.
However, the current Nanosheet-GAAFET has larger leakage current, which causes the increase of the power consumption of the device.
Disclosure of Invention
In view of the above, an object of the present application is to provide a semiconductor device and a method for manufacturing the same, which can reduce leakage current of the semiconductor device and improve performance of the semiconductor device finally manufactured.
The embodiment of the application provides a semiconductor device, which comprises:
a substrate;
the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is positioned between the source electrode and the drain electrode, and the channel structure comprises a lamination formed by a plurality of nano sheets;
a gate surrounding the nanoplatelets;
a cavity located at least between the channel structure and the substrate, the cavity being surrounded by the channel structure, the source, the drain and the substrate.
Optionally, the cavity is filled with a thermally conductive material or a cooling material.
Optionally, removing a portion of the thickness of the substrate corresponding to the channel structure using an isotropic process to form the cavity between the substrate and the channel structure.
Optionally, the semiconductor device includes a stop layer, the stop layer being located on a side of the source or the drain adjacent to the cavity.
Optionally, a high-K dielectric layer may be further disposed between the gate and the nano-sheet, and a portion of the high-K dielectric layer is located on a side of the channel structure near the cavity.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, and forming a laminated structure formed by alternately laminating a first semiconductor layer and a second semiconductor layer on one side of the substrate;
etching the laminated structure to form a source electrode region and a drain electrode region, wherein a channel region is arranged between the source electrode region and the drain electrode region;
forming a source and a drain in the source region and the drain region, respectively;
replacing the first semiconductor layer with a grid, wherein the grid surrounds the second semiconductor layer, and a channel structure is formed by a lamination formed by a plurality of second semiconductor layers;
and removing the substrate with partial thickness corresponding to the channel structure so as to form the cavity between the substrate and the channel structure.
Optionally, the removing the substrate with the partial thickness corresponding to the channel structure includes:
and removing a substrate with partial thickness corresponding to the channel structure from the target region by utilizing an isotropic process, wherein the substrate comprises a target region, and the target region surrounds the source region, the drain region and the channel region.
Optionally, before the source region and the drain region form a source and a drain, respectively, the method further comprises:
and forming a stop layer in the source electrode region and the drain electrode region.
Optionally, the replacing the first semiconductor layer with a gate includes:
removing the first semiconductor layer, and forming a plurality of gaps to be filled between the second semiconductor layers;
and filling the grid electrode in a plurality of gaps to be filled.
Optionally, before the plurality of gap-filling gates to be filled, the method further includes:
and forming a high-K dielectric layer on the surface of the second semiconductor layer.
The embodiment of the application provides a semiconductor device, which comprises a substrate, a source electrode, a drain electrode and a channel structure, wherein the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is arranged between the source electrode and the drain electrode, the channel structure comprises a lamination layer formed by a plurality of nano sheets, a grid electrode surrounds the nano sheets, a cavity is formed by surrounding the channel structure and the substrate, namely, the cavity is formed by surrounding the channel structure, the source electrode, the drain electrode and the substrate, and a film layer which is not contacted is arranged below the channel structure, so that the full floating structure is formed, the gate control performance of the semiconductor device can be greatly improved, the subthreshold swing amplitude of the semiconductor device is reduced, the leakage current and the parasitic capacitance are reduced, the driving current is increased, and the performance of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1A shows a schematic three-dimensional structure of a semiconductor device according to an embodiment of the present application;
fig. 1B, fig. 2, and fig. 1C are schematic cross-sectional structures of the semiconductor device shown in fig. 1A in various directions according to embodiments of the present application;
fig. 3A, 3B and 3C are schematic cross-sectional structures of the semiconductor device shown in fig. 1A in various directions according to embodiments of the present application;
fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 5 to 22 are schematic structural views showing a method for manufacturing a semiconductor device according to an embodiment of the present application.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
In describing embodiments of the present application in detail, the cross-sectional views illustrating the structure of the device are not to scale locally for ease of illustration, and the schematic is merely exemplary and should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
With the development of semiconductor technology, the feature size of integrated circuits is continuously shrinking, and conventional tri-Gate or dual-Gate Fin Field-Effect-Transistor (FinFET) is limited below 3 nanometers (nm), and Nanosheet Gate-all-round Fin Field-Effect-Transistor (Nanosheet-GAAFET) breaks through the limitation of the 3nm node, so that the Nanosheet Gate-GAAFET is widely focused and studied.
Nanosheet-GAAFET is a novel device with a circular gate structure and horizontal Nanoplatelets (NS) as conductive channels. In the aspect of gate control, the gate-surrounding structure has better gate control capability than a FinFET device structure, short channel effect of the device can be effectively inhibited, in the aspect of current driving, nanosheet-GAAFET has inversion carriers of 'body inversion', and the current driving performance of the device can be remarkably enhanced through the increase of effective gate width and the design of nano sheet stacking in the vertical direction.
However, a planar device with poor gate control characteristics or a bottom fin (Sub-fin) with thicker thickness exists at the bottom of the currently stacked nano-sheets, so that a larger leakage current exists in the nano-sheet-GAAFET, further, the power consumption of the device is increased, and in addition, the parasitic capacitance of the device is increased by the Sub-fin, so that the circuit speed is reduced.
Based on this, the embodiment of the application provides a semiconductor device, including the substrate, set up the source electrode of substrate one side, drain electrode and channel structure, channel structure is located between source electrode and the drain electrode, channel structure includes the stromatolite that a plurality of nano-sheets formed, the grid surrounds nano-sheet, the cavity is located at least between channel structure and the substrate, the cavity is formed by channel structure, source electrode, drain electrode and substrate surround, that is, channel structure, source electrode and drain electrode below is the cavity, there is not the rete of contact, complete floating structure has been constituted, can improve the gate accuse performance of semiconductor device by a wide margin, reduce semiconductor device subthreshold swing, reduce leakage current and parasitic capacitance, increase drive current, improve the performance of semiconductor device.
For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1A, a schematic three-dimensional structure of a semiconductor device according to an embodiment of the present application is shown.
The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, and a gate 160.
In the embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.
In the embodiment of the present application, a source 131, a drain 132, and a channel structure are disposed on one side of the substrate 110, where the channel structure is disposed between the source 131 and the drain 132, the channel structure includes a stack formed by a plurality of nano-sheets, where the channel structure is obtained by removing the first semiconductor layer 121 in the stack structure, and the stack structure is formed by alternately stacking the first semiconductor layer 121 and the second semiconductor layer 122, that is, the nano-sheets in the channel structure are the second semiconductor layer 122 in the stack structure, as shown in fig. 1B and fig. 2, where fig. 1B is a schematic cross-sectional structure in the YY direction of the semiconductor device shown in fig. 1A provided in the embodiment of the present application, fig. 2 is a schematic cross-sectional structure in the XX direction of the semiconductor device shown in fig. 1A provided in the embodiment of the present application, the schematic cross-sectional structure in the YY direction is a direction parallel to a gate line of the gate, and the schematic cross-sectional structure in the XX direction is a direction parallel to a fin line of the fin.
Specifically, the width of the nano-sheet can be 5-50nm, and the thickness of the nano-sheet can be 3-20nm.
In the embodiment of the present application, a space is provided between the plurality of nano-sheets in the channel structure, and the space is filled with the gate 160, that is, the gate 160 surrounds the nano-sheets, so as to form a ring gate structure.
In the embodiment of the present application, a cavity 200 is provided between the channel structure and the substrate 110, and referring to fig. 1C, fig. 1C is a schematic cross-sectional structure of the semiconductor device shown in fig. 1A provided in the embodiment of the present application in the CC direction, which is parallel to the YY direction, that is, fig. 1C is a cross-section of the source 131 or the drain 132 of the semiconductor device in the direction parallel to the gate line of the gate. The cavity 200 is surrounded by the channel structure, the source 131, the drain 132 and the substrate 110, i.e. the channel structure is not in contact with the substrate 110, constituting a fully floating structure. That is, the channel structure, the source 131 and the drain 132 are hollow and have no contact film layer, so that a bottom fin (Sub-fin) with a larger area does not exist under the lamination of the nano sheets, the gate control performance of the semiconductor device can be greatly improved, the subthreshold swing of the semiconductor device is reduced, the leakage current and the parasitic capacitance are reduced, the driving current is increased, and the performance of the semiconductor device is improved.
In practical applications, the source 131 or the drain 132 often adopts a (111) crystal plane in actual formation, and thus has a diamond shape when the source 131 or the drain 132 is sectioned.
Specifically, the width of the cavity may be adjusted according to practical situations, for example, 100 nm-10 μm.
In the embodiment of the application, the cavity can be filled with a heat conducting material or a cooling material, so that heat dissipation of the channel structure can be increased, and self-heating effect is improved. The cooling material may for example be in the form of microfluidic water cooling.
In an embodiment of the present application, the cavity 200 may remove the substrate 110 having a partial thickness corresponding to the channel structure using an isotropic process, that is, the substrate 110 having a partial thickness under the channel structure is hollowed out using the isotropic process to form the cavity 200.
In an embodiment of the present application, a stop layer 190 may be disposed at a side of the source electrode 131 or the drain electrode 132 near the cavity 200, and as shown in fig. 3A, 3B and 3C, it may be achieved that the source electrode 131 or the drain electrode 132 is not damaged when the substrate 110 having a partial thickness is removed using an isotropic process using the stop layer 190. The material of the stop layer 190 may be selected to be etch selective to the material of the substrate 110.
As an example, the material of the substrate 110 is silicon and the material of the stop layer 190 may be silicon germanium.
In the embodiment of the present application, a high-K dielectric layer 150 may be further disposed between the gate 160 and the nano-sheet, that is, the high-K dielectric layer 150 is disposed around the nano-sheet, as shown in fig. 3A, 3B and 3C, wherein a portion of the high-K dielectric layer 150 is located on a side of the channel structure near the cavity 200. The high-K dielectric layer 150 may be utilized to achieve that the channel structure is not damaged when the isotropic process is utilized to remove a portion of the thickness of the substrate 110. The material of the high-K dielectric layer 150 may be selected to be etch selective to the material of the substrate 110.
As an example, the material of the high-k dielectric layer 150 may be HfO 2 、HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 、Al 2 O 3 、ZrO 2 、ZrSiO x 、Ta 2 O 5 Or La (La) 2 O 3 One or a combination of several of them.
In an embodiment of the present application, the semiconductor device further includes a trench isolation 203, a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.
The shallow trench isolation 203 is disposed between different fins, and a surface of the shallow trench isolation 203 on a side away from the substrate 110 may be flush with or may be higher or lower than a surface of the stacked structure in the fins on a side close to the substrate 110. The shallow trench isolation 203 may be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to isolate the channels on adjacent fins.
The second side walls 205 are disposed on a side of the channel structure away from the substrate 110, and the gate 160 is disposed between the second side walls 205. The isolation layer 207 is disposed on a side of the source electrode 131 or the drain electrode 132 away from the substrate 110, and the second sidewall 205 and the gate 160 are disposed between the isolation layers 207.
The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160, and the top dielectric layer 170 has a contact electrode 180, where the contact electrode 180 is used for electrically leading out the source 131 or the drain 132.
Therefore, the embodiment of the application provides a semiconductor device, which comprises a substrate, a source electrode, a drain electrode and a channel structure, wherein the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is arranged between the source electrode and the drain electrode, the channel structure comprises a lamination formed by a plurality of nano sheets, a grid electrode surrounds the nano sheets, a cavity is formed by surrounding the channel structure and the substrate, namely, the cavity is formed by surrounding the channel structure, the source electrode, the drain electrode and the substrate, namely, the cavity is arranged below the channel structure, the source electrode and the drain electrode, and a film layer which is not contacted with the cavity is arranged, so that a full floating structure is formed, the gate control performance of the semiconductor device can be greatly improved, the subthreshold swing amplitude of the semiconductor device is reduced, the leakage current and the parasitic capacitance are reduced, the driving current is increased, and the performance of the semiconductor device is improved.
Based on the semiconductor device provided in the above embodiments, the embodiments of the present application further provide a method for manufacturing a semiconductor device, and the working principle thereof will be described in detail with reference to the accompanying drawings.
Referring to fig. 4, a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown.
The manufacturing method of the semiconductor device provided by the embodiment of the application comprises the following steps:
s101, a substrate 110 is provided, and a stacked structure in which first semiconductor layers 121 and second semiconductor layers 122 are alternately stacked is formed on one side of the substrate 110, as shown with reference to fig. 5A and 5B.
In the embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.
As an example, a desired well depth may be achieved by implanting impurities into the bulk silicon substrate, and annealing to form a highly doped well region. The doping type of the substrate 110 is different for different device types, wherein for P-type semiconductor devices the highly doped well region is an N-well, the implanted impurity is an N-type impurity ion, such as phosphorus (P) ion, and for N-type semiconductor devices the highly doped well region is a P-well, the implanted impurity is a P-type impurity ion, such as boron (B) ion.
In an embodiment of the present application, a stacked structure in which the first semiconductor layer 121 and the second semiconductor layer 122 are alternately stacked may be formed on one side of the substrate 110, as shown in fig. 5A and 5B, where fig. 5A is a schematic cross-sectional structure of the semiconductor device shown in fig. 1A in the YY direction, which is provided in the embodiment of the present application, and fig. 5B is a schematic cross-sectional structure of the semiconductor device shown in fig. 1A in the XX direction, which is provided in the embodiment of the present application, and the schematic cross-sectional structure of the YY direction is a direction parallel to a gate line of the gate electrode, and the schematic cross-sectional structure of the XX direction is a direction parallel to a fin line of the fin.
Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be the same, for example, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon or germanium. The materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be different for different device types, for example, for a P-type semiconductor device, the material of the first semiconductor layer 121 may be silicon and the material of the second semiconductor layer 122 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium and the material of the second semiconductor layer 122 may be silicon.
In practical applications, silicon oxide may be formed on the substrate 110, and the stacked structure may be formed after removing the silicon oxide on the substrate 110 and cleaning the substrate 110.
S102, the stacked structure is etched to form a source region 101 and a drain region 102, as shown with reference to fig. 11A and 11B.
In the embodiment of the present application, the stacked structure may be etched to form the source region 101 and the drain region 102, where the channel region 103 is between the source region 101 and the drain region 102, as shown in fig. 11A and 11B.
The process flow for specifically forming the source region 101 and the drain region 102 is as follows:
s1021, a side wall transfer process, which is shown with reference to FIG. 6A and FIG. 6B.
In the embodiment of the present application, a self-aligned sidewall transfer process is adopted to form the first sidewall 201, and the material of the first sidewall 201 is silicon nitride, and the specific forming process is as follows: a layer of sacrificial layer 202 is covered on the laminated structure, the material of the sacrificial layer 202 can be polysilicon or amorphous silicon, part of the sacrificial layer 202 is etched by utilizing photoetching, silicon nitride material is deposited, and the rest of the sacrificial layer 202 is etched by adopting anisotropic etching, so that the sacrificial layer is only remained on the first side wall 201 on the laminated structure, and the first side wall 201 plays a role of a Hard Mask (Hard Mask) in the subsequent photoetching for forming fins.
S1022, fins are formed, as shown with reference to fig. 7A and 7B.
In the embodiment of the present application, the stacked structure may be etched by an etching process to form a plurality of fins distributed periodically, as shown in fig. 7A and 7B. And etching by taking the first side wall 201 as a mask to form the fin with the laminated structure. The upper part of the fin is a channel region 103 formed by a laminated structure, and the lower part of the fin is a substrate 110, so that the fin shown in fig. 7A is formed. The fin includes not only a stacked structure but also a monocrystalline silicon structure that extends deep into the substrate 110. The etching process may be a dry etching or a wet etching, and in one embodiment a reactive ion etching may be used. The fins will be used to form nano-sheets of semiconductor devices. Although one fin is shown in fig. 7A, it should be appreciated that any suitable number and configuration of fins may be used in practice.
S1022, shallow trench isolation 203 (shallow trench isolation, STI) is formed, as shown with reference to fig. 8A and 8B.
In embodiments of the present application, shallow trench isolation 203 may be formed between different fins. Specifically, a deposition of dielectric insulating material may be performed first, followed by a planarization process, such as a CMP process, and then a selective etchback process of the dielectric insulating material to expose the fins in three dimensions, thereby forming shallow trench isolation 203 adjacent to the fins. The surface of the shallow trench isolation 203 on the side remote from the substrate 110 may be flush with or above or below the surface of the fin where the stack structure is located near the substrate 110. The shallow trench isolation 203 may be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to isolate the channels on adjacent fins.
In practical applications, the first sidewall 201 may also be removed when the shallow trench isolation 203 is formed.
S1023, dummy gate 204 is formed, as shown with reference to fig. 9A and 9B.
In embodiments of the present application, a dummy gate stack (dummy gate) is formed on the exposed fin in a direction perpendicular to the fin line, i.e., YY direction. The dummy gate stack is a multi-layered structure including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack may be formed by thermal oxidation, chemical vapor deposition, sputtering, and the like. The dummy gate stack spans the stack structure at the upper portion of the fin, and a plurality of dummy gates are periodically distributed along the fin line direction. The material of dummy gate 204 may be polysilicon or amorphous silicon. The material of the hard mask layer may be oxide, carbide, organic, etc.
S1024, a second sidewall 205 is formed, as shown in fig. 10A and 10B.
In the embodiment of the present application, the second side walls 205 may be respectively disposed at two sides of the dummy gate stack along the fin line direction, that is, XX direction, and the thicknesses of the second side walls 205 at two sides are the same. The material of the second sidewall 205 may be a dielectric material having isolation properties, such as silicon nitride or doped silicon oxide.
In the embodiment of the present application, after the dummy gate 204 and the second sidewall 205 are formed, the source-drain etching may be performed on the stacked structure by using the dummy gate 204 and the second sidewall 205 as masks through an etching process, and specifically, the source-drain etching may be performed on the fin. Wherein the source region 101 and the drain region 102 no longer have a stacked structure after being formed by etching, as shown with reference to fig. 11B.
S103, a source 131 and a drain 132 are formed in the source region 101 and the drain region 102, respectively, as shown with reference to fig. 15A and 15B.
In the embodiment of the present application, after the source region 101 and the drain region 102 are formed by etching the stacked structure, the source 131 and the drain 132 may be formed in the source region 101 and the drain region 102, respectively, as shown with reference to fig. 14A and 14B.
Specifically, the source and drain materials may be different for different types of semiconductor devices, and the source and drain materials are boron doped silicon germanium, siGe for P-type semiconductor devices: b, for N-type semiconductor devices, the source and drain materials are phosphorus doped silicon, namely Si: p.
In the embodiment of the present application, before forming the source electrode 131 and the drain electrode 132, the stop layer 190 may be further formed in the source electrode region 101 and the drain electrode region 102, and the specific process flows are as follows:
s1031, a concave structure 401 is formed, as shown with reference to fig. 12A and 12B.
In the embodiment of the present application, the first semiconductor layer 121 in the stacked structure located in the channel region 103 is selectively etched in the XX direction, that is, only the first semiconductor layer 121 is etched, the second semiconductor layer 122 is not damaged, the concave structure 401 is formed in the XX direction at the portion where the first semiconductor layer 121 is missing than the second semiconductor layer 122, that is, a pull-back etching is performed, and a portion of the first semiconductor layer 121 is etched away from the source region 101 and the drain region 102 toward the channel region 103, as shown with reference to fig. 12A and 12B.
S1032, a third sidewall 206 is formed, as shown with reference to fig. 13A and 13B.
In the embodiment of the present application, after etching the first semiconductor layer 121, a dielectric material is deposited on the stacked structure, i.e., the periphery of the fin, of the channel region 103, and the dielectric material is etched to form a third sidewall 206, where the third sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. That is, the concave structure 401 etched in S1031 is filled with the third sidewall 206, and the material of the third sidewall 206 may be silicon nitride or silicon oxide.
S1033, a stop layer 190 is formed, as shown with reference to fig. 14A and 14B.
In embodiments of the present application, the stop layer 190 may be formed using an epitaxial process, and subsequently, the stop layer 190 may be used to achieve that the source electrode 131 or the drain electrode 132 is not damaged when the substrate 110 having a partial thickness is removed using an isotropic process. The material of the stop layer 190 may be selected to be etch selective to the material of the substrate 110.
As an example, the material of the substrate 110 is silicon and the material of the stop layer 190 may be silicon germanium.
In practical applications, for P-type semiconductor devices, the source/drain material is boron doped silicon germanium, and the source 131 or the drain 132 can be directly formed at this time without using an additional process to form the stop layer 190, so that the process steps can be saved and the manufacturing cost can be reduced, and for N-type semiconductor devices, the source/drain material is phosphorus doped silicon, and the epitaxial process can be used to form the stop layer 190.
In an embodiment of the present application, after forming the source electrode 131 and the drain electrode 132, the dummy gate 204 may be removed, as shown with reference to fig. 16A and 16B.
In an embodiment of the present application, an isolation layer 207 may be deposited on the surfaces of the dummy gate 204, the source electrode 131, and the drain electrode 132, to prevent an interconnection short between the dummy gate 204 and the source electrode 131 or the drain electrode 132 in a subsequent step, and the isolation layer 207 may be subjected to a chemical mechanical polishing process to planarize it. Then, as shown in fig. 16A and 16B, the dummy gate 204 formed of the foregoing polysilicon or amorphous silicon is etched or etched away, that is, the dummy gate 204 is removed, by a selective etching or etching process.
S104, the first semiconductor layer 121 is replaced with the gate electrode 160, as shown with reference to fig. 17 to 19.
In an embodiment of the present application, the first semiconductor layer 121 may be replaced with a gate electrode 160, as shown with reference to fig. 17 to 19.
The specific process flow is as follows:
s1041, the first semiconductor layer 121 of the channel region 103 is removed, as shown with reference to fig. 17A and 17B.
In an embodiment of the present application, the first semiconductor layer 121 of the channel region 103 may be removed, i.e., a nano-sheet channel release process may be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, as shown with reference to fig. 17A and 17B.
Specifically, the first semiconductor layer 121 in the stacked structure of the channel region 103 may be selectively etched to perform the nano-sheet channel release. That is, the stacked structure exposed by the fins is processed, the first semiconductor layer 121 of each layer is removed, the first semiconductor layer 121 is a sacrificial layer, and the nano-sheets formed by the second semiconductor layer 122 are released.
In embodiments of the present application, there are several possible implementations of the nanoplatelet channel release for different types of devices:
in a first possible implementation, for both P-type and N-type semiconductor devices, the material of the first semiconductor layer 121, i.e., the sacrificial layer, is silicon germanium, which is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nano-sheet stack device. An etchant that selectively etches silicon germanium at a faster rate relative to silicon may be used in the selective removal process.
In a second possible implementation, for P-type semiconductor devices, the material of the first semiconductor layer 121, i.e., the sacrificial layer, is silicon, and the silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon germanium, to form a silicon germanium stacked nano-sheet stack device. An etchant that selectively etches silicon at a faster rate relative to silicon germanium may be used in the selective removal process.
In a third possible implementation, for an N-type semiconductor device, the material of the first semiconductor layer 121, i.e., the sacrificial layer, is silicon germanium, and the silicon germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nano-sheet stack device. An etchant that selectively etches silicon germanium at a faster rate relative to silicon may be used in the selective removal process.
S1042, a high-K dielectric layer 150 is formed on the surface of the second semiconductor layer 122, as shown in fig. 18A and 18B.
In the embodiment of the present application, after the first semiconductor layer 121 is removed, a high-K dielectric layer 150 may be further formed on the surface of the second semiconductor layer 122, and the high-K dielectric layer 150 surrounds the surface of the second semiconductor layer 122, as shown with reference to fig. 18A and 18B. Specifically, the material of the high-k dielectric layer 150 may be HfO 2 、HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 、Al 2 O 3 、ZrO 2 、ZrSiO x 、Ta 2 O 5 Or La (La) 2 O 3 One or a group of several of (C)And (5) combining.
S1043, the gate 160 is filled in the plurality of gaps to be filled 402, as shown with reference to fig. 19A and 19B.
In the embodiment of the present application, after the nano-sheet channel release is performed, the plurality of gaps 402 to be filled are formed between the plurality of second semiconductor layers 122, and the gate 160 may be filled in the plurality of gaps 402 to be filled, and the gate 160 surrounds the second semiconductor layers 122, so as to form a gate-all-around structure. The stack of the plurality of second semiconductor layers 122 forms a channel structure, i.e., a nanoplate channel of the semiconductor device, as shown with reference to fig. 19A and 19B.
In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 may cover the space after the isolation layer 207 and the dummy gate 204 are removed, and the gate 160 covered with the isolation layer 207 may be subjected to chemical mechanical polishing and planarization.
S105, the substrate 110 having a partial thickness corresponding to the channel structure is removed, as shown with reference to fig. 22A, 22B, and 22C.
In the embodiment of the present application, the substrate 110 with a partial thickness corresponding to the channel structure may be removed, that is, the substrate 110 under the channel structure and the source 131 or the drain 132 may be removed, so as to form the cavity 200 between the substrate 110 and the channel structure, form a full floating structure, and improve the performance of the semiconductor device.
Referring to fig. 21, which is a schematic top view of a semiconductor device according to an embodiment of the present application, fig. 21 shows that a substrate 110 includes a source region 101, a drain region 102, and a channel region 103, and a target region 104 is a region of the substrate 110 except for the source region 101, the drain region 102, and the channel region 103, where the target region 104 may surround the source region 101, the drain region 102, and the channel region 103.
Specifically, the isolation layer 207 may be etched from the target region 104, after forming the through hole 208, the substrate 110 located in the target region 104 may be continuously subjected to isotropic etching, and the substrate 110 having a partial thickness corresponding to the channel structure may be removed by using an isotropic process, as shown in fig. 22A, 22B and 22C.
In the embodiment of the present application, when the isotropic process is used to remove a portion of the substrate 110, the stop layer 190, the high-K dielectric layer 150, the isolation layer 207, and the shallow trench isolation 203 are not damaged because they have a high selectivity to the material of the substrate 110.
Specifically, the isotropic process may be dry etching or wet etching, for example, wet etching using TMAH solution.
In embodiments of the present application, after forming gate 160, dielectric deposition may be performed on top of the semiconductor device away from substrate 110, forming a top dielectric layer 170, as shown with reference to fig. 20A, 20B, and 20C. After the top dielectric layer 170 is formed, an isotropic process may be performed to form the cavity 200, so that the top dielectric layer 170 may be used to protect the gate 160, prevent the gate 160 from being affected when the substrate 110 is etched and removed, and improve the performance of the semiconductor device.
In the embodiment of the present application, after the cavity 200 is formed, a contact hole is etched in the top dielectric layer 170, and etched to the surface of the source electrode 131 or the drain electrode 132, a metal material is deposited in the contact hole, so as to form the contact electrode 180 of the source electrode 131 or the drain electrode 132, and as shown in fig. 3A and 3B, the multi-layer subsequent interconnection and passivation protection process is completed.
In practical applications, when removing a portion of the thickness of the substrate 110, the isolation layer 207 of the target region 104 is etched to form the via 208, and a dielectric material may be deposited by using a plasma enhanced chemical vapor deposition process, so that the etched via 208 is filled, as shown in fig. 3C.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for structural embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and reference is made to the description of method embodiments for relevant points.
The foregoing is merely a preferred embodiment of the present application, and although the present application has been disclosed in the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art may make many possible variations and modifications to the technical solution of the present application, or modify equivalent embodiments, using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application, which do not depart from the content of the technical solution of the present application, still fall within the scope of the technical solution of the present application.
Claims (10)
1. A semiconductor device, the semiconductor device comprising:
a substrate;
the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is positioned between the source electrode and the drain electrode, and the channel structure comprises a lamination formed by a plurality of nano sheets;
a gate surrounding the nanoplatelets;
a cavity located at least between the channel structure and the substrate, the cavity being surrounded by the channel structure, the source, the drain and the substrate.
2. The semiconductor device of claim 1, wherein the cavity is filled with a thermally conductive material or a cooling material.
3. The semiconductor device of claim 1, wherein a portion of the thickness of the substrate corresponding to the channel structure is removed using an isotropic process to form the cavity between the substrate and the channel structure.
4. The semiconductor device of claim 3, wherein the semiconductor device comprises a stop layer on a side of the source or the drain adjacent to the cavity.
5. The semiconductor device of claim 3, wherein a high-K dielectric layer is further disposed between the gate and the nanoplatelets, a portion of the high-K dielectric layer being located on a side of the channel structure adjacent to the cavity.
6. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate, and forming a laminated structure formed by alternately laminating a first semiconductor layer and a second semiconductor layer on one side of the substrate;
etching the laminated structure to form a source electrode region and a drain electrode region, wherein a channel region is arranged between the source electrode region and the drain electrode region;
forming a source and a drain in the source region and the drain region, respectively;
replacing the first semiconductor layer with a grid, wherein the grid surrounds the second semiconductor layer, and a channel structure is formed by a lamination formed by a plurality of second semiconductor layers;
and removing the substrate with partial thickness corresponding to the channel structure so as to form the cavity between the substrate and the channel structure.
7. The method of manufacturing according to claim 6, wherein the removing the portion of the thickness of the substrate corresponding to the channel structure comprises:
and removing a substrate with partial thickness corresponding to the channel structure from the target region by utilizing an isotropic process, wherein the substrate comprises a target region, and the target region surrounds the source region, the drain region and the channel region.
8. The method of manufacturing of claim 7, wherein prior to forming the source and drain regions, respectively, the method further comprises:
and forming a stop layer in the source electrode region and the drain electrode region.
9. The method of manufacturing of claim 6, wherein the replacing the first semiconductor layer with a gate electrode comprises:
removing the first semiconductor layer, and forming a plurality of gaps to be filled between the second semiconductor layers;
and filling the grid electrode in a plurality of gaps to be filled.
10. The method of manufacturing of claim 9, wherein prior to a plurality of the gap-fill gates to be filled, the method further comprises:
and forming a high-K dielectric layer on the surface of the second semiconductor layer.
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