CN116031301A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An embodiment of the present application provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a source, a drain, and a channel structure disposed on one side of the substrate, and the channel structure is located between the source and the drain. The channel structure includes a stack formed by a plurality of nanosheets, a gate, the gate surrounds the nanosheet, a cavity, the cavity is at least between the channel structure and the substrate, and the cavity is composed of a channel structure, a source, a drain It is formed around the substrate, that is to say, the channel structure, the source and the drain are below the cavity, and there is no contact film layer, which constitutes a fully floating structure, which can greatly improve the gate control performance of semiconductor devices and reduce the size of semiconductor devices. Device sub-threshold swing, reduce leakage current and parasitic capacitance, increase drive current, and improve the performance of semiconductor devices.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the traditional triple-gate or double-gate Fin Field-Effect Transistor (Fin Field-Effect Transistor, FinFET) is limited at nodes below 3 nanometers (nm). The Nanosheet-Gate all round Fin Field-Effect Transistor (Nanosheet-GAAFET) has broken through the limitation of the 3nm node, so it has received extensive attention and research.

Nanosheet-GAAFET is a novel device with gate-all-around structure and horizontal nanosheet (Nanosheet, NS) as the conductive channel. In terms of gate control, the ring-gate structure has better gate control capability than the FinFET device structure, which can effectively suppress the short channel effect of the device. In terms of current drive, Nanosheet-GAAFET has "body inversion" inversion current carrying Moreover, the increase of the effective gate width and the stacking design of nanosheets in the vertical direction can also significantly enhance the current driving performance of the device.

However, the leakage current of the current Nanosheet-GAAFET is relatively large, resulting in increased power consumption of the device.

Contents of the invention

In view of this, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which can reduce the leakage current of the semiconductor device and improve the performance of the final manufactured semiconductor device.

An embodiment of the present application provides a semiconductor device, and the semiconductor device includes:

Substrate;

A source electrode, a drain electrode, and a channel structure disposed on one side of the substrate, the channel structure is located between the source electrode and the drain electrode, and the channel structure includes a stack formed by a plurality of nanosheets layer;

a gate surrounding the nanosheet;

A cavity, the cavity is located at least between the channel structure and the substrate, and the cavity is formed surrounded by the channel structure, the source, the drain and the substrate.

Optionally, the cavity is used to be filled with heat conducting material or cooling material.

Optionally, an isotropic process is used to remove part of the thickness of the substrate corresponding to the channel structure, so as to form the cavity between the substrate and the channel structure.

Optionally, the semiconductor device includes a stop layer, and the stop layer is located on a side of the source or the drain close to the cavity.

Optionally, a high-K dielectric layer may also be disposed between the gate and the nanosheet, and part of the high-K dielectric layer is located on a side of the channel structure close to the cavity.

An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

providing a substrate, forming a stacked structure of alternately stacked first semiconductor layers and second semiconductor layers on one side of the substrate;

Etching the stacked structure to form a source region and a drain region, with a channel region between the source region and the drain region;

forming a source and a drain in the source region and the drain region, respectively;

replacing the first semiconductor layer with a gate, the gate surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure;

A part of the thickness of the substrate corresponding to the channel structure is removed to form the cavity between the substrate and the channel structure.

Optionally, the removing part of the thickness of the substrate corresponding to the channel structure includes:

Beginning from the target area, using an isotropic process to remove a part of the thickness of the substrate corresponding to the channel structure, the substrate includes a target area, and the target area surrounds the source region, the drain region and the the channel region.

Optionally, before forming a source and a drain in the source region and the drain region respectively, the method further includes:

A stopper layer is formed on the source region and the drain region.

Optionally, the replacing the first semiconductor layer with a gate includes:

removing the first semiconductor layer, and forming a plurality of gaps to be filled between the second semiconductor layers;

Filling gates in the plurality of gaps to be filled.

Optionally, before the plurality of gap-filling gates to be filled, the method further includes:

A high-K dielectric layer is formed on the surface of the second semiconductor layer.

An embodiment of the present application provides a semiconductor device, including a substrate, a source disposed on one side of the substrate, a drain and a channel structure, the channel structure is located between the source and the drain, and the channel structure includes a plurality of A stack of nanosheets, a gate, the gate surrounds the nanosheets, a cavity, the cavity is located at least between the channel structure and the substrate, the cavity is formed by surrounding the channel structure, the source, the drain and the substrate, That is to say, the channel structure, the source and the drain are under the cavity, and there is no contact film layer, which constitutes a fully floating structure, which can greatly improve the gate control performance of semiconductor devices, reduce the subthreshold swing of semiconductor devices, Reduce leakage current and parasitic capacitance, increase drive current, and improve performance of semiconductor devices.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

FIG. 1A shows a schematic diagram of a three-dimensional structure of a semiconductor device provided by an embodiment of the present application;

FIG. 1B, FIG. 2 and FIG. 1C are schematic cross-sectional structure diagrams in various directions of the semiconductor device shown in FIG. 1A provided by the embodiment of the present application;

Fig. 3A, Fig. 3B and Fig. 3C are schematic cross-sectional structure diagrams in various directions of the semiconductor device shown in Fig. 1A provided by the embodiment of the present application;

FIG. 4 shows a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

5 to 22 are schematic structural diagrams of a semiconductor device manufactured according to a method for manufacturing a semiconductor device provided in an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

In the following description, a lot of specific details are set forth in order to fully understand the application, but the application can also be implemented in other ways different from those described here, and those skilled in the art can do it without violating the content of the application. By analogy, the present application is therefore not limited by the specific embodiments disclosed below.

This application is described in detail in combination with schematic diagrams. When describing the embodiments of this application in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit this application. scope of protection. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the traditional triple-gate or double-gate Fin Field-Effect-Transistor (Fin Field-Effect-Transistor, FinFET) is limited at nodes below 3 nanometers (nm). Nanosheet Gate-all-round Fin Field-Effect-Transistor (Nanosheet-GAAFET) has broken through the limitation of 3nm node, so it has received extensive attention and research.

Nanosheet-GAAFET is a novel device with gate-all-around structure and horizontal nanosheet (Nanosheet, NS) as the conductive channel. In terms of gate control, the ring-gate structure has better gate control capability than the FinFET device structure, which can effectively suppress the short channel effect of the device. In terms of current drive, Nanosheet-GAAFET has "body inversion" inversion current carrying Moreover, the increase of the effective gate width and the stacking design of nanosheets in the vertical direction can also significantly enhance the current driving performance of the device.

However, there are planar devices with poor gate control characteristics or thick bottom fins (Sub-fin) at the bottom of the current stacked nanosheets, which cause a large leakage current in the Nanosheet-GAAFET, which further increases the power consumption of the device. In addition, the Sub-fin -fin also increases device parasitic capacitance, resulting in reduced circuit speed.

Based on this, an embodiment of the present application provides a semiconductor device, including a substrate, a source disposed on one side of the substrate, a drain and a channel structure, the channel structure is located between the source and the drain, and the channel structure A stack formed of a plurality of nanosheets, a gate, a gate surrounding the nanosheets, a cavity, the cavity is located at least between the channel structure and the substrate, the cavity is composed of the channel structure, the source, the drain and the substrate Surrounding formation, that is to say, the channel structure, the source and the drain below are cavities, and there is no contact film layer, which constitutes a fully floating structure, which can greatly improve the gate control performance of semiconductor devices and reduce the subthreshold of semiconductor devices swing, reduce leakage current and parasitic capacitance, increase drive current, and improve the performance of semiconductor devices.

In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1A , this figure is a schematic three-dimensional structure diagram of a semiconductor device provided by an embodiment of the present application.

The semiconductor device provided in this embodiment includes a substrate 110 , a source 131 , a drain 132 , a channel structure and a gate 160 .

In the embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may also be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate. substrate or N-type silicon substrate.

In the embodiment of the present application, a source 131, a drain 132, and a channel structure are arranged on one side of the substrate 110, wherein the channel structure is arranged between the source 131 and the drain 132, and the channel structure Including a stack formed by a plurality of nanosheets, wherein the channel structure is obtained by removing the first semiconductor layer 121 in the stack structure, and the stack structure is formed by alternately stacking the first semiconductor layer 121 and the second semiconductor layer 122, That is to say, the nanosheets in the channel structure are the second semiconductor layer 122 in the laminated structure, as shown in FIG. 1B and FIG. 2 , wherein FIG. 1B is the semiconductor device shown in FIG. 1A provided in the embodiment of the present application Fig. 2 is a schematic cross-sectional structure schematic diagram of the YY direction of the semiconductor device shown in Fig. 1A provided by the embodiment of the present application. The schematic cross-sectional structure schematic diagram of the YY direction is the direction parallel to the gate line of the gate, XX The schematic diagram of the cross-sectional structure of the direction is the direction parallel to the fin line of the fin.

Specifically, the width of the nanosheets may be 5-50 nm, and the thickness of the nanosheets may be 3-20 nm.

In the embodiment of the present application, there are gaps between the plurality of nanosheets in the channel structure, and the gaps are filled with gates 160 , that is, the gates 160 surround the nanosheets, forming a gate-all-around structure.

In the embodiment of the present application, there is a cavity 200 between the channel structure and the substrate 110, as shown in FIG. 1C, which is a CC direction cross-section of the semiconductor device shown in FIG. 1A provided by the embodiment of the present application. In the structural diagram, the CC direction is parallel to the YY direction, that is to say, FIG. 1C is obtained by taking a cross-section of the source 131 or the drain 132 of the semiconductor device in a direction parallel to the gate line of the gate. The cavity 200 is surrounded by the channel structure, the source 131 , the drain 132 and the substrate 110 , that is, the channel structure is not in contact with the substrate 110 , forming a fully floating structure. That is to say, there is a cavity under the channel structure, the source electrode 131 and the drain electrode 132, and there is no contact film layer, so that there is no bottom fin (Sub-fin) with a larger area under the stack of nanosheets. , can greatly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce the leakage current and parasitic capacitance, increase the driving current, and improve the performance of the semiconductor device.

In practical application, the source electrode 131 or the drain electrode 132 usually adopts (111) crystal plane when actually formed, so the source electrode 131 or the drain electrode 132 is in a rhombus shape when the cross section is taken.

Specifically, the width of the cavity can be adjusted according to actual conditions, for example, it is 100 nanometers-10 micrometers.

In the embodiment of the present application, the cavity may also be filled with heat conducting material or cooling material, which can increase the heat dissipation of the channel structure and improve the self-heating effect. The cooling material may, for example, be in the form of microfluidic water cooling.

In the embodiment of the present application, the cavity 200 can use an isotropic process to remove a part of the thickness of the substrate 110 corresponding to the channel structure, that is, use an isotropic process to remove a part of the thickness of the substrate 110 below the channel structure. The bottom 110 is hollowed out to form a cavity 200 .

In the embodiment of the present application, a stop layer 190 can be provided on the side of the source electrode 131 or the drain electrode 132 close to the cavity 200. Referring to FIG. 3A, FIG. 3B and FIG. 3C, the stop layer 190 can be used to achieve When removing part of the thickness of the substrate 110 by the same process, the source 131 or the drain 132 will not be damaged. The material of the stop layer 190 can be selected to have etching selectivity with the material of the substrate 110 .

As an example, the material of the substrate 110 is silicon, and the material of the stop layer 190 may be silicon germanium.

In the embodiment of the present application, a high-K dielectric layer 150 may also be provided between the gate 160 and the nanosheet, that is, the high-K dielectric layer 150 is arranged around the nanosheet, as shown in FIG. 3A, FIG. 3B and FIG. 3C, in which some The high-K dielectric layer 150 is located on a side of the channel structure close to the cavity 200 . The high-K dielectric layer 150 can be used to realize that the channel structure will not be damaged when part of the thickness of the substrate 110 is removed by an isotropic process. The material of the high-K dielectric layer 150 can be selected to have etching selectivity with the material of the substrate 110 .

As an example, the material of the high-k dielectric layer 150 can be HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , HfLaO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ or La ₂ O ₃ one or a combination of several.

In the embodiment of the present application, the semiconductor device further includes a trench isolation 203 , a second spacer 205 , an isolation layer 207 , a top dielectric layer 170 and a contact electrode 180 .

The shallow trench isolation 203 is arranged between different fins, and the surface of the shallow trench isolation 203 away from the substrate 110 can be flush with the surface of the stacked structure in the fin close to the substrate 110, or can be higher than or below the surface. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the trenches on adjacent fins.

The second sidewall 205 is disposed on a side of the channel structure away from the substrate 110 , and the gate 160 is disposed between the second sidewall 205 . The isolation layer 207 is disposed on the side of the source 131 or the drain 132 away from the substrate 110 , and the second spacer 205 and the gate 160 are disposed between the isolation layer 207 .

The top dielectric layer 170 covers the isolation layer 207 , the second spacer 205 and the gate 160 . The top dielectric layer 170 has a contact electrode 180 therein, and the contact electrode 180 is used to electrically lead out the source 131 or the drain 132 .

It can be seen that the embodiment of the present application provides a semiconductor device, including a substrate, a source disposed on one side of the substrate, a drain and a channel structure, the channel structure is located between the source and the drain, and the channel The structure includes a stack formed by a plurality of nanosheets, a gate, the gate surrounds the nanosheets, a cavity, the cavity is located at least between the channel structure and the substrate, and the cavity is composed of a channel structure, a source, a drain, and a substrate The bottom is formed around the bottom, that is to say, the channel structure, the source and the drain are below the cavity, and there is no contact film layer, which constitutes a fully floating structure, which can greatly improve the gate control performance of the semiconductor device and reduce the sub-components of the semiconductor device. Threshold swing, reducing leakage current and parasitic capacitance, increasing drive current, and improving the performance of semiconductor devices.

Based on the semiconductor device provided in the above embodiments, the embodiment of the present application also provides a method for manufacturing the semiconductor device, and its working principle will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 4 , this figure is a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application.

The method for manufacturing a semiconductor device provided in the embodiment of the present application includes the following steps:

S101 , providing a substrate 110 , and forming a stacked structure of alternately stacked first semiconductor layers 121 and second semiconductor layers 122 on one side of the substrate 110 , as shown in FIG. 5A and FIG. 5B .

In the embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may also be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate. substrate or N-type silicon substrate.

As an example, a highly doped well region can be formed by implanting impurities into the bulk silicon substrate and annealing to achieve the desired well depth. For different device types, the doping types of the substrate 110 are different. For P-type semiconductor devices, the above-mentioned highly doped well region is an N well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions, wherein for For an N-type semiconductor device, the above-mentioned highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

In the embodiment of the present application, a stacked structure consisting of alternately stacked first semiconductor layers 121 and second semiconductor layers 122 may be formed on one side of the substrate 110, as shown in FIG. 5A and FIG. 5B , wherein FIG. 5A is The embodiment of the present application provides a schematic diagram of the cross-sectional structure of the semiconductor device shown in FIG. 1A in the YY direction. FIG. 5B is a schematic diagram of the cross-sectional structure of the semiconductor device shown in FIG. 1A provided in the embodiment of the present application. The cross-sectional structure in the YY direction The schematic diagram is parallel to the direction of the gate lines of the gate, and the schematic diagram of the cross-sectional structure in the XX direction is the direction parallel to the fin lines of the fins.

Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same, for example, the material of the first semiconductor layer 121 can be silicon germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. . For different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different, for example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon.

In practical applications, silicon oxide may be formed on the substrate 110 , and the stacked structure may be formed after removing the silicon oxide on the substrate 110 and cleaning the substrate 110 .

S102 , etching the stacked structure to form a source region 101 and a drain region 102 , as shown in FIG. 11A and FIG. 11B .

In the embodiment of the present application, the stacked structure can be etched to form the source region 101 and the drain region 102, wherein the channel region 103 is between the source region 101 and the drain region 102, referring to FIG. 11A and Figure 11B shows.

The specific process flow for forming the source region 101 and the drain region 102 is as follows:

S1021, a sidewall transfer process, as shown in FIG. 6A and FIG. 6B.

In the embodiment of the present application, the self-aligned sidewall transfer process is used to form the first sidewall 201, and the material of the first sidewall 201 is silicon nitride. layer 202, the material of the sacrificial layer 202 can be polysilicon or amorphous silicon, use photolithography to pattern etch away part of the sacrificial layer 202, deposit silicon nitride material, and then use anisotropic etching to etch away the remaining sacrificial layer Layer 202, so that only the first sidewall 201 on the stacked structure remains, and the first sidewall 201 plays the role of a hard mask (Hard Mask) in the subsequent photolithography for forming fins.

S1022, forming fins, as shown in FIG. 7A and FIG. 7B.

In the embodiment of the present application, the stacked structure may be etched by an etching process to form a plurality of periodically distributed fins, as shown in FIG. 7A and FIG. 7B . Etching is performed using the first sidewall 201 as a mask to form fins with a stacked structure. Wherein, the upper part of the fin is the channel region 103 formed by the stacked structure, and the lower part of the fin is the substrate 110 , forming the fin as shown in FIG. 7A . The fin includes not only a stacked layer structure, but also a single crystal silicon structure deep into the substrate 110 . The etching process can be dry etching or wet etching, and reactive ion etching can be used in one embodiment. The fins will be used to form nanosheets of semiconductor devices. Although one fin is shown in FIG. 7A, it should be understood that any suitable number and configuration of fins may be used in practice.

S1022, forming shallow trench isolation 203 (shallow trench isolation, STI), as shown in FIG. 8A and FIG. 8B .

In an embodiment of the present application, shallow trench isolation 203 may be formed between different fins. Specifically, the dielectric insulating material can be deposited first, followed by a planarization process, such as a CMP process, and then a selective etching back process of the dielectric insulating material, so as to expose the three-dimensional fins, thereby forming shallow trenches adjacent to the fins Slot isolation 203 . The surface of the shallow trench isolation 203 away from the substrate 110 may be flush with the surface of the stacked structure in the fin close to the substrate 110 , or may be higher or lower than the surface. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the trenches on adjacent fins.

In practical application, when forming the shallow trench isolation 203 , the first spacer 201 may also be removed.

S1023, forming a dummy gate 204, as shown in FIG. 9A and FIG. 9B.

In the embodiment of the present application, a dummy gate stack (dummy gate) is formed on the exposed fins and in a direction perpendicular to the fin lines, ie in the YY direction. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204 and a hard mask layer (not shown). The dummy gate stack can be formed by thermal oxidation, chemical vapor deposition, sputtering and other processes. The dummy gate stack spans the stacked structure on the upper part of the fin, and a plurality of dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 may be polysilicon or amorphous silicon. The material of the hard mask layer can be oxide, carbide, organic matter, etc.

S1024, forming the second side wall 205, as shown in FIG. 10A and FIG. 10B.

In the embodiment of the present application, second sidewalls 205 may be respectively provided on both sides of the dummy gate stack along the fin line direction, that is, XX direction, and the second sidewalls 205 on both sides have the same thickness. The material of the second sidewall 205 may be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

In the embodiment of the present application, after the dummy gate 204 and the second spacer 205 are formed, the source and drain of the laminated structure can be etched by an etching process by using the dummy gate 204 and the second sidewall 205 as a mask, specifically The source and drain of the fins are etched. Wherein, the source region 101 and the drain region 102 no longer have a stacked structure after being formed by etching, as shown in FIG. 11B .

S103 , forming a source electrode 131 and a drain electrode 132 in the source region 101 and the drain region 102 respectively, as shown in FIG. 15A and FIG. 15B .

In the embodiment of the present application, after forming the source region 101 and the drain region 102 by etching the stacked structure, the source 131 and the drain 132 can be formed on the source region 101 and the drain region 102 respectively, referring to FIG. 14A and 14B.

Specifically, for different types of semiconductor devices, the source and drain materials may be different. For P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, that is, SiGe: B; for N-type semiconductor devices, the source The drain material is phosphorus-doped silicon, ie Si:P.

In the embodiment of the present application, before forming the source electrode 131 and the drain electrode 132, the stop layer 190 may also be formed in the source region 101 and the drain region 102, and the specific process flow is as follows:

S1031, forming a concave structure 401, as shown in FIG. 12A and FIG. 12B.

In the embodiment of the present application, along the XX direction, the first semiconductor layer 121 in the stacked structure in the channel region 103 is selectively etched, that is, only the first semiconductor layer 121 is etched, and the second The semiconductor layer 122 is not damaged, and along the XX direction, the part of the first semiconductor layer 121 missing from the second semiconductor layer 122 forms a concave structure 401, that is, pull-back etching is performed, and the first semiconductor layer 121 is etched from the source Parts of the region 101 and the drain region 102 are etched away toward the channel region 103 , as shown in FIG. 12A and FIG. 12B .

S1032, forming the third side wall 206, as shown in FIG. 13A and FIG. 13B.

In the embodiment of the present application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the stacked structure located in the channel region 103, that is, the periphery of the fin, and the dielectric material is etched to form the third sidewall 206 , the third sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110 . That is to say, the concave structure 401 caused by the S1031 etching is filled up by the third sidewall 206, and the material of the third sidewall 206 can be silicon nitride or silicon oxide.

S1033, forming a stop layer 190, as shown in FIG. 14A and FIG. 14B.

In the embodiment of the present application, the epitaxial process can be used to form the stop layer 190 , and the stop layer 190 can be used later to realize that the source 131 or the drain 132 will not be damaged when the substrate 110 is partially thickened by an isotropic process. The material of the stop layer 190 can be selected to have etching selectivity with the material of the substrate 110 .

As an example, the material of the substrate 110 is silicon, and the material of the stop layer 190 may be silicon germanium.

In practical applications, for P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, and the source electrode 131 or the drain electrode 132 can be directly formed at this time, without using an additional process to form the stop layer 190, which can save The process steps reduce the manufacturing cost. For an N-type semiconductor device, the source and drain materials are phosphorus-doped silicon, and the epitaxial process can be used to form the stop layer 190 .

In the embodiment of the present application, after the source 131 and the drain 132 are formed, the dummy gate 204 can be removed, as shown in FIG. 16A and FIG. 16B .

In the embodiment of the present application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, the source 131 and the drain 132 to prevent the interconnect short circuit between the dummy gate 204 and the source 131 or the drain 132 in subsequent steps. , and perform a chemical mechanical polishing process on the isolation layer 207 to make it planarized. Then, as shown in FIG. 16A and FIG. 16B , the aforementioned dummy gate 204 formed of polysilicon or amorphous silicon is etched or etched away through a selective etching or etching process, that is, the dummy gate 204 is removed.

S104, replace the first semiconductor layer 121 with the gate 160, as shown in FIGS. 17-19.

In the embodiment of the present application, the first semiconductor layer 121 may be replaced by the gate 160 , as shown in FIGS. 17-19 .

The specific process is as follows:

S1041 , removing the first semiconductor layer 121 of the channel region 103 , as shown in FIG. 17A and FIG. 17B .

In the embodiment of the present application, the first semiconductor layer 121 of the channel region 103 can be removed, that is, the nanosheet channel release process is performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layer 122, referring to FIG. 17A and shown in Figure 17B.

Specifically, the first semiconductor layer 121 in the stacked structure of the channel region 103 may be selectively etched to release the nanosheet channel. That is to say, the stack structure exposed by the fins is processed, and the first semiconductor layer 121 of each layer is removed, and the first semiconductor layer 121 is a sacrificial layer, and the nanosheets formed by the second semiconductor layer 122 are released.

In the embodiment of the present application, for different types of devices, there are several possible implementations for channel release of nanosheets:

In the first possible implementation mode, for P-type and N-type semiconductor devices, the first semiconductor layer 121, that is, the material of the sacrificial layer is silicon germanium, silicon germanium is selectively removed, and the second semiconductor layer 122, that is, silicon, is retained. A silicon stacked nanosheet stack device is formed. An etchant that selectively etches silicon germanium at a faster rate relative to silicon may be used in the selective removal process.

In the second possible implementation mode, for a P-type semiconductor device, the material of the first semiconductor layer 121, that is, the sacrificial layer is silicon, and the silicon is selectively removed, and the second semiconductor layer 122, that is, silicon germanium, is retained to form a silicon germanium stack. Layered nanosheet stack devices. An etchant that selectively etches silicon at a faster rate relative to silicon germanium may be used in the selective removal process.

In the third possible implementation mode, for an N-type semiconductor device, the first semiconductor layer 121, that is, the material of the sacrificial layer is silicon germanium, and the silicon germanium is selectively removed, and the second semiconductor layer 122, that is, silicon, is retained to form a silicon stack. Layered nanosheet stack devices. An etchant that selectively etches silicon germanium at a faster rate relative to silicon may be used in the selective removal process.

S1042, forming a high-K dielectric layer 150 on the surface of the second semiconductor layer 122, as shown in FIG. 18A and FIG. 18B.

In the embodiment of the present application, after removing the first semiconductor layer 121, a high-k dielectric layer 150 may be formed on the surface of the second semiconductor layer 122, and the high-k dielectric layer 150 surrounds the surface of the second semiconductor layer 122, referring to FIG. 18A and Figure 18B. Specifically, the material of the high-k dielectric layer 150 can be HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , HfLaO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ or La ₂ O ₃ one or a combination of several.

S1043, filling the gates 160 in the plurality of gaps 402 to be filled, as shown in FIG. 19A and FIG. 19B .

In the embodiment of the present application, after the release of the nanosheet channel, there are a plurality of gaps 402 to be filled between the plurality of second semiconductor layers 122, and the gate 160 can be filled in the plurality of gaps 402 to be filled, and the gate 160 Surrounding the second semiconductor layer 122, a gate-all-around structure is formed. A stack of multiple second semiconductor layers 122 forms a channel structure, that is, a nanosheet channel of a semiconductor device, as shown in FIG. 19A and FIG. 19B .

In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the removal of the isolation layer 207 and the dummy gate 204, and chemical mechanical polishing can be performed on the gate 160 covering the isolation layer 207 , for planarization.

S105 , removing part of the thickness of the substrate 110 corresponding to the channel structure, as shown in FIG. 22A , FIG. 22B and FIG. 22C .

In the embodiment of the present application, the substrate 110 corresponding to a part of the thickness of the channel structure can be removed, that is, the substrate 110 under the channel structure and the source electrode 131 or the drain electrode 132 can be removed, so as to form the substrate 110 and the channel structure The cavity 200 between them forms a fully floating structure and improves the performance of the semiconductor device.

Referring to FIG. 21 , which is a schematic top view of a semiconductor device provided by an embodiment of the present application, FIG. 21 shows that a substrate 110 includes a source region 101 , a drain region 102 and a channel region 103 , and a target region 104 The target region 104 may surround the source region 101 , the drain region 102 and the channel region 103 , being the region of the substrate 110 other than the source region 101 , the drain region 102 and the channel region 103 .

Specifically, the isolation layer 207 can be etched starting from the target region 104, and after forming the through hole 208, continue to perform isotropic etching on the substrate 110 located in the target region 104, and use an isotropic process to remove and trench The structure corresponds to the partial thickness of the substrate 110 , as shown in FIG. 22A , FIG. 22B and FIG. 22C .

In the embodiment of the present application, when using the isotropic process to remove part of the substrate 110, since the materials of the stop layer 190, the high-K dielectric layer 150, the isolation layer 207 and the shallow trench isolation 203 are all the same as those of the substrate 110 Has a high selectivity ratio, so it will not be damaged.

Specifically, the isotropic process may be dry etching or wet etching, for example, wet etching using TMAH solution.

In the embodiment of the present application, after the gate 160 is formed, dielectric deposition may be performed on the top of the semiconductor device away from the substrate 110 to form a top dielectric layer 170 , as shown in FIG. 20A , FIG. 20B and FIG. 20C . After the top dielectric layer 170 is formed, an isotropic process can be performed to form the cavity 200, so that the top dielectric layer 170 can be used to protect the gate 160, preventing the gate 160 from being affected when the substrate 110 is etched and removed, and improving the performance of the semiconductor device. performance.

In the embodiment of the present application, after the cavity 200 is formed, the contact hole is etched in the top dielectric layer 170, etched to the surface of the source electrode 131 or the drain electrode 132, and a metal material is deposited in the contact hole to form a source The contact electrode 180 of the electrode 131 or the drain 132, as shown in FIG. 3A and FIG. 3B , is subsequently completed with multi-layer subsequent interconnection and passivation protection processes.

In practical applications, when removing part of the thickness of the substrate 110, the isolation layer 207 of the target region 104 is etched to form the through hole 208, and the dielectric material can be deposited by a plasma-enhanced chemical vapor deposition process, and the etched formed The via hole 208 is filled, as shown with reference to FIG. 3C .

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for relevant parts, please refer to the part of the description of the method embodiments.

The above descriptions are only the preferred embodiments of the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person familiar with the art, without departing from the scope of the technical solution of the application, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the application, or to modify the equivalent of equivalent changes Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application that do not deviate from the content of the technical solution of the present application still fall within the protection scope of the technical solution of the present application.

Claims (10)

1. A semiconductor device, the semiconductor device comprising:

a substrate;

the source electrode, the drain electrode and the channel structure are arranged on one side of the substrate, the channel structure is positioned between the source electrode and the drain electrode, and the channel structure comprises a lamination formed by a plurality of nano sheets;

a gate surrounding the nanoplatelets;

a cavity located at least between the channel structure and the substrate, the cavity being surrounded by the channel structure, the source, the drain and the substrate.

2. The semiconductor device of claim 1, wherein the cavity is filled with a thermally conductive material or a cooling material.

3. The semiconductor device of claim 1, wherein a portion of the thickness of the substrate corresponding to the channel structure is removed using an isotropic process to form the cavity between the substrate and the channel structure.

4. The semiconductor device of claim 3, wherein the semiconductor device comprises a stop layer on a side of the source or the drain adjacent to the cavity.

5. The semiconductor device of claim 3, wherein a high-K dielectric layer is further disposed between the gate and the nanoplatelets, a portion of the high-K dielectric layer being located on a side of the channel structure adjacent to the cavity.

6. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate, and forming a laminated structure formed by alternately laminating a first semiconductor layer and a second semiconductor layer on one side of the substrate;

etching the laminated structure to form a source electrode region and a drain electrode region, wherein a channel region is arranged between the source electrode region and the drain electrode region;

forming a source and a drain in the source region and the drain region, respectively;

replacing the first semiconductor layer with a grid, wherein the grid surrounds the second semiconductor layer, and a channel structure is formed by a lamination formed by a plurality of second semiconductor layers;

and removing the substrate with partial thickness corresponding to the channel structure so as to form the cavity between the substrate and the channel structure.

7. The method of manufacturing according to claim 6, wherein the removing the portion of the thickness of the substrate corresponding to the channel structure comprises:

and removing a substrate with partial thickness corresponding to the channel structure from the target region by utilizing an isotropic process, wherein the substrate comprises a target region, and the target region surrounds the source region, the drain region and the channel region.

8. The method of manufacturing of claim 7, wherein prior to forming the source and drain regions, respectively, the method further comprises:

and forming a stop layer in the source electrode region and the drain electrode region.

9. The method of manufacturing of claim 6, wherein the replacing the first semiconductor layer with a gate electrode comprises:

removing the first semiconductor layer, and forming a plurality of gaps to be filled between the second semiconductor layers;

and filling the grid electrode in a plurality of gaps to be filled.

10. The method of manufacturing of claim 9, wherein prior to a plurality of the gap-fill gates to be filled, the method further comprises:

and forming a high-K dielectric layer on the surface of the second semiconductor layer.

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