CN117855355B - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

Info

Publication number
CN117855355B
CN117855355B CN202410239095.6A CN202410239095A CN117855355B CN 117855355 B CN117855355 B CN 117855355B CN 202410239095 A CN202410239095 A CN 202410239095A CN 117855355 B CN117855355 B CN 117855355B
Authority
CN
China
Prior art keywords
layer
sub
emitting diode
light
epitaxial wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202410239095.6A
Other languages
Chinese (zh)
Other versions
CN117855355A (en
Inventor
郑文杰
程龙
高虹
刘春杨
胡加辉
金从龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Zhao Chi Semiconductor Co Ltd
Original Assignee
Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Zhao Chi Semiconductor Co Ltd filed Critical Jiangxi Zhao Chi Semiconductor Co Ltd
Priority to CN202410239095.6A priority Critical patent/CN117855355B/en
Publication of CN117855355A publication Critical patent/CN117855355A/en
Application granted granted Critical
Publication of CN117855355B publication Critical patent/CN117855355B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025Physical imperfections, e.g. particular concentration or distribution of impurities

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a Si substrate, and a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer which are sequentially stacked on the Si substrate, wherein the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer comprises a YAlN layer and a ScAlN layer which are sequentially stacked, the second sub-layer comprises a Si doped Ga 2O3 layer and an (AlGa) 2O3 layer which are sequentially stacked, and the third sub-layer comprises a Si 3N4 layer and an Mg doped BGaN layer which are sequentially stacked. The composite buffer layer can reduce the leakage channel caused by the Si substrate and improve the quality of epitaxially grown crystals, thereby improving the luminous efficiency.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
The ultraviolet band LED has the advantages of small volume, low energy consumption, long service life, environmental protection and no toxicity, and is widely applied to the aspects of water purification, biological agent detection, sterilization, medicine and the like, thereby having wide market prospect. The light-emitting wavelength of the AlGaN material can be as short as 200nm, so the AlGaN material becomes an important material for manufacturing ultraviolet and deep ultraviolet light-emitting diodes.
The high leakage current and low breakdown voltage of the Si-substrate AlGaN-based device is still the largest short plate. At present, the performance of a device is improved mainly by increasing the thickness of a buffer layer on a Si substrate, however, the method is difficult to control, and has low yield and high cost. Moreover, the Si substrate, which is not completely insulated, provides electrons to the buffer layer, and electrons of the substrate enter the buffer layer to increase the leakage current of the buffer layer, thereby causing high leakage current of the buffer layer on the Si substrate, and further causing breakdown to easily occur, resulting in device damage.
Disclosure of Invention
The invention aims to solve the technical problem of providing the light-emitting diode epitaxial wafer, which can reduce the leakage channel caused by the Si substrate and improve the quality of epitaxially grown crystals, thereby improving the luminous efficiency.
The invention also aims to solve the technical problem of providing the preparation method of the light-emitting diode epitaxial wafer, which has simple process and high light-emitting efficiency.
In order to achieve the technical effects, the invention provides a light-emitting diode epitaxial wafer, which comprises a Si substrate, and a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer which are sequentially stacked on the Si substrate, wherein the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer comprises a YAlN layer and a ScAlN layer which are sequentially stacked, the second sub-layer comprises a Si doped Ga 2O3 layer and an (AlGa) 2O3 layer which are sequentially stacked, and the third sub-layer comprises a Si 3N4 layer and a Mg doped BGaN layer which are sequentially stacked.
As an improvement of the technical scheme, the thickness of the first sub-layer is 10 nm-40 nm, and the thickness ratio of the YAlN layer to the ScAlN layer is 1 (0.8-1.5);
The thickness of the second sub-layer is 10 nm-50 nm, and the thickness ratio of the Si-doped Ga 2O3 layer to the (AlGa) 2O3 layer is 1 (0.8-1.5);
The thickness of the third sub-layer is 10 nm-60 nm, and the thickness ratio of the Si 3N4 layer to the Mg-doped BGaN layer is 1 (0.8-1.5).
As an improvement of the technical scheme, the Al component of the first sub-layer accounts for 0.3-0.4, and the Al component gradually decreases along the epitaxial direction.
As an improvement of the technical scheme, the Si doping concentration of the Si doped Ga 2O3 layer is 5 multiplied by 10 15cm-3~7×1017cm-3; the Al component of the (AlGa) 2O3 layer accounts for 0.3-0.6, and the Al component gradually rises along the epitaxial direction.
As an improvement of the technical scheme, the Mg doping concentration of the Mg-doped BGaN layer is 5 multiplied by 10 17cm-3~7×1018cm-3, and the B component accounts for 0.01-0.1.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps of:
Providing a Si substrate, sequentially growing a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on the Si substrate, wherein the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer comprises a YAlN layer and a ScAlN layer which are sequentially stacked, the second sub-layer comprises a Si doped Ga 2O3 layer and an (AlGa) 2O3 layer which are sequentially stacked, and the third sub-layer comprises a Si 3N4 layer and an Mg doped BGaN layer which are sequentially stacked.
As an improvement of the technical scheme, the growth temperature of the first sub-layer is 700-1100 ℃, and the growth pressure is 100 Torr-300 Torr.
As an improvement of the technical scheme, the growth temperature of the second sub-layer is 600-800 ℃, and the growth pressure is 10 -5mbar~10-2 mbar.
As an improvement of the technical scheme, the growth temperature of the third sub-layer is 800-1100 ℃, and the growth pressure is 50-300 Torr.
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The embodiment of the invention has the following beneficial effects:
The composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer, wherein a YAlN layer and a ScAlN layer in the first sub-layer increase the blocking polarization height and barrier height, and meanwhile, the lattice mismatch between the Si substrate and the epitaxial layer can be gradually relieved, the generation of defects is reduced, and the electric leakage channel of electrons is effectively reduced; the Si doped Ga 2O3 layer in the second sub-layer can reduce dislocation while guaranteeing the crystal quality of the (AlGa) 2O3 layer, and the (AlGa) 2O3 layer has higher forbidden bandwidth, so that the mobility of electrons can be effectively reduced, and the generation of a leakage channel is reduced; the Si 3N4 layer in the third sub-layer further blocks dislocation extension, improves crystal quality of the epitaxial layer, and holes generated in the Mg-doped BGaN layer can neutralize part of leakage electrons and reduce migration speed of the electrons, so that photoelectric performance is improved.
Drawings
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to specific embodiments.
As shown in fig. 1, the embodiment of the invention provides a light-emitting diode epitaxial wafer, which comprises a Si substrate 1, and a composite buffer layer 2, an undoped AlGaN layer 3, an N-type AlGaN layer 4, a multiple quantum well layer 5, an electron blocking layer 6, a P-type AlGaN layer 7 and a P-type contact layer 8 which are sequentially stacked on the Si substrate 1, wherein the composite buffer layer 2 comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer comprises a YAlN layer and a ScAlN layer which are sequentially stacked, the second sub-layer comprises a Si doped Ga 2O3 layer and an (AlGa) 2O3 layer which are sequentially stacked, and the third sub-layer comprises a Si 3N4 layer and an Mg doped aan layer which are sequentially stacked. The YAlN layer and the ScAlN layer in the first sub-layer increase the blocking polarization height and barrier height, and meanwhile, the lattice mismatch between the Si substrate and the epitaxial layer can be gradually relieved, the generation of defects is reduced, and the electric leakage channel of electrons is effectively reduced; the Si doped Ga 2O3 layer in the second sub-layer can reduce dislocation while guaranteeing the crystal quality of the (AlGa) 2O3 layer, and the (AlGa) 2O3 layer has higher forbidden bandwidth, so that the mobility of electrons can be effectively reduced, and the generation of a leakage channel is reduced; the Si 3N4 layer in the third sub-layer further blocks dislocation extension, improves crystal quality of the epitaxial layer, and holes generated in the Mg-doped BGaN layer can neutralize part of leakage electrons and reduce migration speed of the electrons, so that photoelectric performance is improved.
In one embodiment, the thickness of the first sub-layer is 10nm to 40nm, and exemplary is 10nm, 15nm, 20nm, 25nm, 30nm or 40nm, but is not limited thereto. The thickness ratio of YAlN layers to ScAlN layers is 1 (0.8-1.5), and exemplary thicknesses are 1:0.8, 1:0.9, 1:1, 1:1.2, 1:1.3, or 1:1.5, but not limited thereto.
In one embodiment, the thickness of the second sub-layer is 10nm to 50nm, and exemplary is 10nm, 20nm, 25nm, 30nm, 40nm or 50nm, but not limited thereto. The thickness ratio of the Si-doped Ga 2O3 layer to the (AlGa) 2O3 layer is 1 (0.8-1.5), and exemplary is 1:0.8, 1:0.9, 1:1, 1:1.2, 1:1.3, or 1:1.5, but is not limited thereto. The arrangement of the Ga 2O3 layer reduces the lattice mismatch degree between the (AlGa) 2O3 film and the Si substrate, improves the crystallization quality of the (AlGa) 2O3 film, avoids the generation of polycrystal, and influences the quality of the subsequently grown (AlGa) 2O3 layer due to the fact that the crystallization crystal grains are large and unfavorable for the growth of the Ga 2O3 layer if the thickness is too small.
In one embodiment, the thickness of the third sub-layer is 10nm to 60nm, and is exemplified by 10nm, 20nm, 30nm, 40nm, 50nm, or 60nm, but not limited thereto. The thickness ratio of the Si 3N4 layer to the Mg doped BGaN layer is 1 (0.8-1.5), and exemplary is 1:0.8, 1:0.9, 1:1, 1:1.2, 1:1.3, or 1:1.5, but is not limited thereto.
In one embodiment, the first sub-layer has an Al composition ratio of 0.3 to 0.4, and if the Al composition ratio is less than 0.3, it is unfavorable to increase the blocking polarization height and barrier height; if the Al component is more than 0.4, the lattice quality of the subsequent growth is lowered. Preferably, the Al composition ratio is gradually reduced in the epitaxial direction, increasing the polarization height and barrier height of the barrier while improving the lattice quality of the subsequent growth.
In one embodiment, the Si doping concentration of the Si-doped Ga 2O3 layer is 5×10 15cm-3~7×1017cm-3, and Si doping can reduce the generation of threading dislocation and change the extending direction thereof, so as to reduce dislocation, if the Si doping concentration is less than 5×10 15cm-3, the blocking effect on dislocation is not strong; if the Si doping concentration is greater than 7×10 17cm-3, a decrease in crystal quality may be caused, and 5×1015cm-3、8×1015cm-3、1×1016cm-3、5×1016cm-3、1×1017cm-3、5×1017cm-3 or 7×10 17cm-3 is exemplified, but not limited thereto.
In one embodiment, the ratio of the Al component of the (AlGa) 2O3 layer is 0.3-0.6, and adding the material for forming the (AlGa) 2O3 to the Ga 2O3 layer can increase the forbidden bandwidth, effectively prevent the migration of electrons, and thus reduce the generation of leakage channels, and if the ratio of the Al component is less than 0.3, the blocking effect on electrons is not obvious; if the Al component is more than 0.6, it may cause degradation of crystal quality, and exemplary is 0.3, 0.35, 0.4, 0.45, 0.5 or 0.6, but is not limited thereto. Preferably, the Al component proportion gradually rises along the epitaxial direction, and the forbidden bandwidth is regulated and controlled by the Al component proportion, so that better lattice matching is realized, meanwhile, the mobility of electrons is further reduced, and the generation of a leakage channel is reduced.
In one embodiment, the ratio of the component B of the Mg-doped BGaN layer is 0.01-0.1, and the atoms B can fill vacancies in crystal lattices so as to release compressive stress and block dislocation line generation, and if the ratio of the component B is less than 0.01, the blocking effect on dislocation is small; if the B component is greater than 0.1, the growth of the subsequent epitaxial material is not favored, and exemplary is 0.01, 0.02, 0.05, 0.06, 0.08, or 0.1, but is not limited thereto. The Mg doping concentration of the Mg doping BGaN layer is 5 multiplied by 10 17cm-3~7×1018cm-3, holes generated by Mg doping can reduce electron migration caused by the Si substrate, reduce leakage channels, enhance antistatic capability, effectively reduce the resistivity of an epitaxial layer, reduce the working voltage of the light-emitting diode, and if the Mg doping concentration is less than 5 multiplied by 10 17cm-3, enough holes cannot be provided to reduce the electron migration caused by the Si substrate; if the Mg doping concentration is greater than 7×10 18cm-3, the quality of the crystal may be degraded, affecting the quality of the subsequent epitaxial structure, for example, but not limited to, 5×10 17cm-3、8×1017cm-3、1×1018cm-3、5×1018cm-3 or 7×10 18cm-3.
In addition to the above-described composite buffer layer structure, other layered structures of the present invention are characterized as follows:
the thickness of the undoped AlGaN layer 3 is 1-5 μm.
The thickness of the N-type AlGaN layer 4 is 1-5 mu m, and the doping concentration of Si is 1 multiplied by 10 19cm-3~5×1020cm-3.
The multiple quantum well layer 5 comprises an AlGaN quantum well layer and an AlGaN quantum barrier layer which are periodically stacked, and the stacking period is 6-12. The thickness of the AlGaN quantum well layer is 2 nm-5 nm, and the Al component accounts for 0.2-0.6; the AlGaN quantum barrier layer has a thickness of 5 nm-15 nm and an Al component ratio of 0.4-0.8.
The electron blocking layer 6 is an AlGaN electron blocking layer, the thickness is 10 nm-50 nm, and the Al component accounts for 0.4-0.8.
The thickness of the P-type AlGaN layer 7 is 100 nm-200 nm, and the doping concentration of Mg is 1 multiplied by 10 19cm-3~5×1020cm-3.
The P-type contact layer 8 is an AlGaN P-type contact layer, the thickness is 10 nm-50 nm, and the doping concentration of Mg is 5 multiplied by 10 19cm-3~5×1020cm-3.
Correspondingly, as shown in fig. 2, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
S1, providing a Si substrate;
S2, sequentially growing a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on the Si substrate; the epitaxial structure may be grown by MOCVD, MBE, PLD or VPE, but is not limited thereto. Specifically, S2 includes the following steps:
S21, growing a composite buffer layer; specifically, S21 includes the following steps:
s211, growing a first sub-layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 700-1100 ℃, the pressure is 100-300 Torr, and YAlN layers are grown; and controlling the temperature of the reaction chamber to be 700-1100 ℃ and the pressure to be 100-300 Torr, and growing ScAlN layers.
S212, growing a second sub-layer;
PLD growth is adopted, the temperature of a reaction chamber is controlled to be 600-650 ℃, the pressure is controlled to be 10 -5mbar~10-2 mbar, the laser pulse frequency is controlled to be 2-3 Hz, the laser energy density is 1.5J/cm 2~2.5J/cm2, the target material is Ga 2O3, the Ga 2O3 layer is grown by laser irradiation, then the target material is changed into Si, the laser irradiation is carried out, then the target material is changed into Ga 2O3, the laser irradiation is repeated for 2-10 cycles, and the Si doped Ga 2O3 layer is grown; PLD growth is adopted, the temperature of a reaction chamber is controlled to be 610-800 ℃, the pressure is controlled to be 10 -5mbar~10- 2 mbar, the laser pulse frequency is controlled to be 2-3 Hz, the laser energy density is controlled to be 1.5J/cm 2~2.5J/cm2, the target material is Ga 2O3 with the Al content of 12% in atomic ratio, and a (AlGa) 2O3 layer is grown.
S213, growing a third sub-layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 800-1000 ℃, the pressure is controlled to be 100-300 Torr, NH 3 is introduced as an N source, siH 4 is introduced as an Si source, and a Si 3N4 layer is grown; controlling the temperature of the reaction chamber to be 800-1100 ℃, controlling the pressure to be 50-300 Torr, introducing NH 3 as an N source, introducing TEB as a B source, introducing TMGa as a Ga source, introducing CP 2 Mg as an Mg source, and growing the Mg-doped BGaN layer.
S22, growing an undoped AlGaN layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1000-1300 ℃, the pressure is controlled to be 50-500 Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, and TMAL is introduced as an Al source.
S23, growing an N-type AlGaN layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1000-1300 ℃, the pressure is controlled to be 50-500 Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and SiH 4 is introduced as an N-type doping source.
S24, growing a multi-quantum well layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 850-950 ℃, the pressure is controlled to be 50-300 Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and an AlGaN quantum well layer is grown; controlling the temperature of the reaction chamber to be 950-1050 ℃, controlling the pressure to be 50-300 Torr, introducing NH 3 as an N source, introducing TMGa as a Ga source, introducing TMAL as an Al source, and growing an AlGaN quantum barrier layer; and repeatedly stacking the periodically grown AlGaN quantum well layer and the AlGaN quantum barrier layer.
S25, growing an electron blocking layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1000-1100 ℃, the pressure is controlled to be 100-300 Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and CP 2 Mg is introduced as a P-type doping source.
S26, growing a P-type AlGaN layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1000-1100 ℃, the pressure is controlled to be 100-600 Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and CP 2 Mg is introduced as a P-type doping source.
S27, growing a P-type contact layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1000-1100 ℃, the pressure is controlled to be 100-600 Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and CP 2 Mg is introduced as a P-type doping source.
The invention is further illustrated by the following specific examples.
Example 1
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a Si substrate, and a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer which are sequentially laminated on the Si substrate.
The composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer, wherein the first sub-layer comprises YAlN layers and ScAlN layers which are sequentially stacked, the thickness of the YAlN layer is 4nm, and the Al component ratio is 0.3; the ScAlN layer had a thickness of 6nm and an Al component ratio of 0.3. The second sub-layer comprises a Si-doped Ga 2O3 layer and an (AlGa) 2O3 layer which are sequentially stacked, wherein the thickness of the Si-doped Ga 2O3 layer is 4nm, the thickness of the Si-doped concentration 5×10 16cm-3;(AlGa)2O3 layer is 6nm, and the Al component ratio is 0.5. The third sub-layer comprises a Si 3N4 layer and a Mg-doped BGaN layer which are sequentially stacked, and the thickness of the Si 3N4 layer is 4nm; the thickness of the Mg-doped BGaN layer is 6nm, the B component ratio is 0.05, and the Mg doping concentration is 1 multiplied by 10 18cm-3.
The undoped AlGaN layer has a thickness of 2 μm.
The thickness of the N-type AlGaN layer is 2 μm, and the doping concentration of Si is 2.5X10 19cm-3.
The multi-quantum well layer is composed of AlGaN quantum well layers and AlGaN quantum barrier layers which are alternately stacked, and the cycle number is 9. The thickness of the AlGaN quantum well layer is 3.5nm, and the in component ratio is 0.45; the AlGaN quantum barrier layer had a thickness of 11nm and an Al component ratio of 0.55.
The electron blocking layer is AlGaN electron blocking layer with thickness of 30nm and Al component ratio of 0.65.
The thickness of the P-type AlGaN layer is 150nm, and the doping concentration of Mg is 5 multiplied by 10 19cm-3.
The P-type contact layer is an AlGaN P-type contact layer, the thickness is 20nm, and the doping concentration of Mg is 1 multiplied by 10 20cm-3.
The preparation method of the LED epitaxial wafer comprises the following steps:
S1, providing a Si substrate;
And S2, sequentially growing a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on the Si substrate. Specifically, S2 includes the following steps:
S21, growing a composite buffer layer; specifically, S21 includes the following steps:
s211, growing a first sub-layer;
MOCVD is adopted for growth, the temperature of the reaction chamber is controlled to be 1000 ℃, the pressure is controlled to be 200Torr, and YAlN layers are grown; the reaction chamber temperature was controlled at 1000℃and the pressure at 200Torr to grow ScAlN layers.
S212, growing a second sub-layer;
PLD growth is adopted, the temperature of a reaction chamber is controlled to be 600 ℃, the pressure is controlled to be 10 -3 mbar, the laser pulse frequency is 2.5Hz, the laser energy density is 2J/cm 2, the target is Ga 2O3, the Ga 2O3 layer is grown by laser irradiation, then the target is changed into Si, the laser irradiation is carried out, then the target is changed into Ga 2O3, the laser irradiation is carried out, 8 cycles are repeated, and the Si doped Ga 2O3 layer is grown; PLD growth is adopted, the temperature of a reaction chamber is controlled to be 700 ℃, the pressure is controlled to be 10 -3 mbar, the laser pulse frequency is 2.5Hz, the laser energy density is 2J/cm 2, the target material is Ga 2O3 with the Al content of 12% in atomic ratio, and a (AlGa) 2O3 layer is grown.
S213, growing a third sub-layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 900 ℃, the pressure is controlled to be 150Torr, NH 3 is introduced as an N source, siH 4 is introduced as an Si source, and a Si 3N4 layer is grown; controlling the temperature of the reaction chamber to 900 ℃, controlling the pressure to 100Torr, introducing NH 3 as an N source, introducing TEB as a B source, introducing TMGa as a Ga source, introducing CP 2 Mg as an Mg source, and growing the Mg-doped BGaN layer.
S22, growing an undoped AlGaN layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1200 ℃, the pressure is controlled to be 100Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, and TMAL is introduced as an Al source.
S23, growing an N-type AlGaN layer;
MOCVD growth is adopted, the temperature of a reaction chamber is controlled to be 1200 ℃, the pressure is controlled to be 100Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and SiH 4 is introduced as an N type doping source.
S24, growing a multi-quantum well layer;
MOCVD growth is adopted, the temperature of a reaction chamber is controlled to be 900 ℃, the pressure is controlled to be 200Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and an AlGaN quantum well layer is grown; controlling the temperature of the reaction chamber to 1000 ℃, controlling the pressure to be 200Torr, introducing NH 3 as an N source, introducing TMGa as a Ga source, introducing TMAL as an Al source, and growing an AlGaN quantum barrier layer; and repeatedly stacking the periodically grown AlGaN quantum well layer and the AlGaN quantum barrier layer.
S25, growing an electron blocking layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1050 ℃, the pressure is controlled to be 200Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and CP 2 Mg is introduced as a P-type doping source.
S26, growing a P-type AlGaN layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1050 ℃, the pressure is controlled to be 200Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and CP 2 Mg is introduced as a P-type doping source.
S27, growing a P-type contact layer;
MOCVD growth is adopted, the temperature of the reaction chamber is controlled to be 1050 ℃, the pressure is controlled to be 200Torr, NH 3 is introduced as an N source, TMGa is introduced as a Ga source, TMAL is introduced as an Al source, and CP 2 Mg is introduced as a P-type doping source.
Example 2
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the thickness of YAlN layers in the first sub-layer is 20nm; the ScAlN layers had a thickness of 20nm. The thickness of the Si-doped Ga 2O3 layer in the second sub-layer is 25nm; the thickness of the (AlGa) 2O3 layer was 25nm. The thickness of the Si 3N4 layer in the third sub-layer is 30nm; the thickness of the Mg-doped BGaN layer is 30nm. The remainder was the same as in example 1.
Example 3
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 2 in that the Al composition ratio in the first sub-layer gradually decreases from 0.4 to 0.3 along the epitaxial direction. The remainder was the same as in example 2.
Example 4
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 3 in that the Al composition ratio of the (AlGa) 2O3 layer in the second sub-layer gradually increases from 0.3 to 0.6 in the epitaxial direction. The remainder was the same as in example 3.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that the composite buffer layer does not include the first sub-layer; accordingly, the preparation step of the first sub-layer is also not included in the preparation method. The remainder was the same as in example 1.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that the composite buffer layer does not include the second sub-layer; accordingly, the second sub-layer preparation step is also not included in the preparation method. The remainder was the same as in example 1.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that the composite buffer layer does not include a third sub-layer; accordingly, the preparation step of the third sub-layer is also not included in the preparation method. The remainder was the same as in example 1.
Performance test:
The light emitting diode epitaxial wafers prepared in examples 1 to 4 and comparative examples 1 to 3 were fabricated into 10mil×24mil chips and subjected to performance test with the same LED spot tester at 120mA/60mA of current, and the results are shown in table 1.
TABLE 1 results of LED Performance test
As can be seen from the table, the adoption of the composite buffer layer structure can effectively improve the luminous brightness of the LED and reduce the working voltage.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The utility model provides a light emitting diode epitaxial wafer, its characterized in that includes the Si substrate and stacks gradually in compound buffer layer, undoped AlGaN layer, N type AlGaN layer, multiple quantum well layer, electron blocking layer, P type AlGaN layer and P type contact layer on the Si substrate, compound buffer layer includes first sublayer, second sublayer and third sublayer, first sublayer is including stack gradually YAlN layers and ScAlN layers, the second sublayer is including Si doped Ga 2O3 layer and (AlGa) 2O3 layer that stacks gradually, the third sublayer is including Si 3N4 layer and Mg doped aN layer that stacks gradually.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the thickness of the first sub-layer is 10 nm-40 nm, and the thickness ratio of the YAlN layer to the ScAlN layer is 1 (0.8-1.5);
The thickness of the second sub-layer is 10 nm-50 nm, and the thickness ratio of the Si-doped Ga 2O3 layer to the (AlGa) 2O3 layer is 1 (0.8-1.5);
The thickness of the third sub-layer is 10 nm-60 nm, and the thickness ratio of the Si 3N4 layer to the Mg-doped BGaN layer is 1 (0.8-1.5).
3. The light-emitting diode epitaxial wafer of claim 1, wherein the first sub-layer has an Al composition ratio of 0.3 to 0.4, and the Al composition ratio gradually decreases in the epitaxial direction.
4. The light emitting diode epitaxial wafer of claim 1, wherein the Si doped Ga 2O3 layer has a Si doping concentration of 5 x10 15cm-3~7×1017cm-3; the Al component of the (AlGa) 2O3 layer accounts for 0.3-0.6, and the Al component gradually rises along the epitaxial direction.
5. The led epitaxial wafer of claim 1, wherein the Mg doped BGaN layer has a Mg doping concentration of 5 x 10 17cm-3~7×1018cm-3 and a B component ratio of 0.01 to 0.1.
6. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 5, and is characterized by comprising the following steps:
Providing a Si substrate, sequentially growing a composite buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on the Si substrate, wherein the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer comprises a YAlN layer and a ScAlN layer which are sequentially stacked, the second sub-layer comprises a Si doped Ga 2O3 layer and an (AlGa) 2O3 layer which are sequentially stacked, and the third sub-layer comprises a Si 3N4 layer and an Mg doped BGaN layer which are sequentially stacked.
7. The method of manufacturing a light-emitting diode epitaxial wafer according to claim 6, wherein the growth temperature of the first sub-layer is 700 ℃ to 1100 ℃ and the growth pressure is 100torr to 300torr.
8. The method of manufacturing a light-emitting diode epitaxial wafer according to claim 6, wherein the growth temperature of the second sub-layer is 600 ℃ to 800 ℃ and the growth pressure is 10 -5mbar~10-2 mbar.
9. The method of manufacturing a light-emitting diode epitaxial wafer according to claim 6, wherein the growth temperature of the third sub-layer is 800 ℃ to 1100 ℃ and the growth pressure is 50torr to 300torr.
10. A light emitting diode, characterized in that the light emitting diode comprises the light emitting diode epitaxial wafer according to any one of claims 1 to 5.
CN202410239095.6A 2024-03-04 2024-03-04 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Active CN117855355B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410239095.6A CN117855355B (en) 2024-03-04 2024-03-04 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410239095.6A CN117855355B (en) 2024-03-04 2024-03-04 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Publications (2)

Publication Number Publication Date
CN117855355A CN117855355A (en) 2024-04-09
CN117855355B true CN117855355B (en) 2024-05-14

Family

ID=90544304

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410239095.6A Active CN117855355B (en) 2024-03-04 2024-03-04 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Country Status (1)

Country Link
CN (1) CN117855355B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112750691A (en) * 2021-01-18 2021-05-04 西安电子科技大学 Nitrogen polar surface GaN material and homoepitaxial growth method
TW202247461A (en) * 2021-02-12 2022-12-01 美商雷森公司 Rare-earth iii-nitride n-polar hemt
CN117293240A (en) * 2023-09-26 2023-12-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117613167A (en) * 2024-01-24 2024-02-27 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112750691A (en) * 2021-01-18 2021-05-04 西安电子科技大学 Nitrogen polar surface GaN material and homoepitaxial growth method
TW202247461A (en) * 2021-02-12 2022-12-01 美商雷森公司 Rare-earth iii-nitride n-polar hemt
CN117293240A (en) * 2023-09-26 2023-12-26 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117613167A (en) * 2024-01-24 2024-02-27 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Also Published As

Publication number Publication date
CN117855355A (en) 2024-04-09

Similar Documents

Publication Publication Date Title
CN116314514B (en) LED epitaxial wafer, preparation method thereof and LED
CN116581217B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116825918B (en) Light-emitting diode epitaxial wafer and preparation method thereof
CN217641376U (en) LED epitaxial wafer and LED chip
CN117239025B (en) GaN-based green light LED epitaxial wafer, preparation method thereof and LED
CN117613167B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117253950B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116525734A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117525232B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN109103312B (en) Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof
CN116960248B (en) Light-emitting diode epitaxial wafer and preparation method thereof
CN115863503B (en) Deep ultraviolet LED epitaxial wafer, preparation method thereof and deep ultraviolet LED
CN116504894A (en) GaN-based LED epitaxial wafer, growth process thereof and LED
CN116014041A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117855355B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117276435B (en) LED epitaxial wafer, preparation method thereof and LED
CN118039760B (en) Deep ultraviolet LED epitaxial wafer, preparation method thereof and LED chip
CN116825917B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117810324B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117810325B (en) High-light-efficiency light-emitting diode epitaxial wafer and preparation method thereof
CN117936670A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN118522833A (en) LED epitaxial wafer, preparation method thereof and LED
CN118572003A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117712247A (en) GaN-based LED epitaxial wafer and preparation method thereof
CN118099307A (en) High-light-efficiency LED epitaxial wafer, preparation method thereof and high-light-efficiency LED

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant