CN117850538A - S-band signal direct frequency synthesis device and method - Google Patents
S-band signal direct frequency synthesis device and method Download PDFInfo
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Abstract
The invention discloses a direct frequency synthesis device and a direct frequency synthesis method for S-band signals, wherein the device comprises the following components: the device comprises an FPGA chip unit, a high-speed data converter unit, a power management unit, a clock management unit, a balun unit and a band-pass filter unit. The invention synthesizes S-band signals directly in frequency, has high output frequency, the modulator is realized in a high-speed data converter in a digital way, LO and DAC inputs do not need to be calibrated to a quadrature modulator to restrain LO leakage and interference images, the device only has one analog low-pass filter for filtering data conversion images, the device has excellent spurious performance indexes, the device synthesizes RF signals directly in frequency, does not need to use traditional up-conversion or down-conversion with an analog radio link, the hardware quantity needing to be deployed is greatly reduced, the spurious of the whole device is low, the hardware circuit is simple, the cost is low, the volume is small, the size is far smaller than that of the same type of products, and the device can well meet the requirements of practical application.
Description
Technical Field
The invention belongs to the technical field of frequency agile radars, and particularly relates to a direct frequency synthesis device and method for S-band signals.
Background
At present, a baseband signal source device in a frequency synthesizer in the technical fields of agile radars, electronic reactance and analog simulation is relatively mature, and the implementation mode mainly comprises two modes. The first method adopts an FPGA+DAC (Digital to analog converter, digital-to-analog converter) to construct a DDS (Direct Digital Synthesis, signal generator) with amplitude modulation and phase modulation, completes real-time calculation of various modulation signals such as frequency, pulse width, repetition frequency, amplitude, pulse modulation parameters and the like of radar signals in each simulation period according to set frequency, pulse width, repetition frequency and pulse modulation, generates a Pulse Description Word (PDW) data stream of the required radar signals, adopts an arbitrary waveform generation technology to control the broadband DDS, and realizes the generation of radar signal patterns. The advantage of this approach is that the baseband signal output frequency is high, but the spurious index is poor. The second scheme adopts an FPGA+DDS chip, the FPGA can directly control a phase register, an amplitude register and a frequency register through a parallel data port mode of the DDS chip, radar pulse modulation signals of various types can be simply realized, excellent spurious performance indexes can be obtained, but the output frequency range of the scheme is limited, and the output frequency of the DDS chip commonly used in the market at present is generally not more than 1.2GHz.
Disclosure of Invention
In order to solve the technical problems, the invention provides a direct frequency synthesis device and a direct frequency synthesis method for S-band signals, and the device has the advantages of small volume, high integration level and low cost.
The invention adopts the technical scheme that: an S-band signal direct frequency synthesizing apparatus comprising: the device comprises an FPGA chip unit, a high-speed data converter unit, a power management unit, a clock management unit, a balun unit and a band-pass filter unit.
The power management unit is respectively connected with the FPGA chip unit and the high-speed data converter unit; the clock management unit is respectively connected with the FPGA chip unit and the high-speed data converter unit; the FPGA chip unit is connected with the high-speed data converter unit; the high-speed data converter unit is connected with the balun unit; the balun unit is connected with the band-pass filter unit.
The FPGA chip unit comprises: baseband data generator module, JESD204B high speed serial interface.
The high-speed data converter unit, i.e. a high-speed DAC, comprises: JESD204B high-speed serial interface, digital processing path module, DAC core module.
The power management unit includes: singlechip, switching power supply, linear regulator LDO.
The clock management unit includes: power divider, quad divider, clock fan-out buffer.
Further, in the FPGA chip unit, the baseband data generator module includes: an in-phase data generator and a quadrature data generator.
The in-phase data generator and the quadrature data generator are both based on an 8-path parallel DDS technology of an XILINX FPGA, and continuous change of a plurality of DDS control words is realized in an interpolation mode by instantiating 8 serial DDS IP cores.
The JESD204B high-speed serial interface uses a CDR clock recovery technology, a data interface clock is not needed, no channel offset exists, and the highest transmission rate can reach 12.5Gbps.
Further, in the high-speed data converter unit, the digital processing path module includes: a bypass, 2x or 3x selectable interpolator, three 2x interpolation half-band filters, a FIR85 interpolation filter, a frequency tuning word NCO.
The FIR85 interpolation filter works at 90% bandwidth, adopts a four-channel switch architecture of a DAC, and samples data on the rising edge or the falling edge of a DAC clock.
The frequency tuning word NCO is a completely orthogonal 48-bit NCO, and no mirror frequency offset of an input data signal is realized.
The DAC kernel module adopts a four-switch architecture.
Wherein, the high-speed data converter model is AD9164. The JESD204B high-speed serial interface is consistent with the JESD204B high-speed serial interface in the FPGA chip unit.
Further, the power management unit controls the time sequence by controlling enabling signals of 1 DCDC and 8 LDOs through a singlechip, the CPU core is 51 series, 18 IOs are provided with internal oscillators, and the package is only TSSOP20.
Wherein, the singlechip model is N76E003AT20. The power management unit provides 1V, 1.2V, 1.8V and 3.3V with controllable time sequence for the FPGA chip unit; the high-speed data converter units are provided with 1.2V, 2.5V and 3.3V with controllable timing.
Further, in the clock management unit, the clock management unit generates 5 paths of homologous clock signals, including two paths of SYSREF signals, one path of ref clock, one path of device clock and one path of dac clock.
The power divider is of the type SIPS121SP4, and divides input external reference signals into two paths of reference 1 and reference 2, wherein the reference 1 is output to the balun unit, and the reference 2 is output to the four-frequency divider. The frequency divider model is SID027SP3. The clock fan-out buffer model is AD9508.
Further, the balun unit converts the single-ended signal reference 1 into a differential signal dac clock as a reference clock signal of the high-speed data converter unit AD9164. The passband range of the band-pass filter unit is 2 GHz-3 GHz, and the in-band insertion loss is less than or equal to 2dB.
The invention also provides a direct frequency synthesis method of the S-band signal, which comprises the following specific steps:
s1, starting a singlechip to work after a power management unit is powered on, sequentially generating an enabling signal 5 and an enabling signal 7, an enabling signal 6 and an enabling signal 9, an enabling signal 8, an enabling signal 1, an enabling signal 3, an enabling signal 4 and an enabling signal 2 at intervals of 1ms, controlling DCDC and LDO, and generating a time sequence controllable voltage signal to a high-speed data converter unit and an FPGA chip unit;
the enabling signals 5 to 9 control the power-on time sequence of the high-speed data converter unit; and the enabling signals 1 to 4 control the power-on time sequence of the FPGA chip unit.
S2, the clock management unit converts an external reference clock signal into five paths of differential clock signals;
wherein the dac clock is used as a reference clock signal for the high-speed data converter unit; the SYSREF1 signal acts as the master timing reference in the JESD204B link of the high speed data converter unit; the SYSREF2 signal is used as a main time sequence reference of the FPGA chip unit; the ref clock signal is used as a reference clock of a JESD204B IP core used by the FPGA chip unit, and is configured to be 300MHz through capacitive alternating current coupling to a special clock pin of a GT transceiver of the FPGA chip unit; the device clock signal is the global clock of the FPGA.
The frequency of the dac clock signal is 4.8GHz; the SYSREF1 signal and the SYSREF2 signal have a frequency of 3.125MHz; the frequency of the ref clock signal is 300MHz; the device clock signal frequency is 300MHz.
S3, utilizing logic resources of an FPGA chip unit to generate digital baseband data, and encoding according to a working mode of a JESD204B high-speed serial interface in the FPGA chip unit;
the baseband data generator module in the FPGA chip unit instantiates 8 serial DDS IP cores, the clock of each DDS IP core is 300MHz, the data rate is 2.4GHz, and any frequency modulation and phase modulation pulse baseband signal with the bandwidth of 1.2GHz is generated.
S4, transmitting digital baseband data generated by logic resources of the FPGA chip unit in the step S3 to a high-speed data converter unit through a JESD204B high-speed serial interface in the FPGA chip module unit, and establishing a JESD204B link;
the JESD204B link establishment includes: code set synchronization, initializing channel alignment sequences and user data.
The SYNC signal is used for synchronization signal, when the high-speed data converter AD9164 pulls the SYNC signal low, it marks that the link starts to be established, and when 4 consecutive K codes are received, the code group synchronization is completed, and the next stage is entered to initialize the channel alignment sequence.
SERDES Lane Rate of JESD204B high-speed serial interface in the FPGA chip unit and the high-speed data converter unit is set to 8Gbps, FDAC frequency of the high-speed data converter AD9164 is 4.8GHz, and interpolation is 2. Remaining SERDES parameters: l:8, 8; m:2; f:1, a step of; s:2; k:32; n:16.
s5, based on the step S4, the high-speed data converter unit outputs a differential signal to the balun unit, the balun unit converts the differential signal output by the high-speed data converter AD9164 into a single-ended signal, and the single-ended signal is filtered by the band-pass filter unit to synthesize an S-band signal;
the FDAC frequency of the high-speed data converter AD9164 is 4.8GHz, and an FIR85 interpolation filter is used in the chip to filter data interpolation. The frequency of the frequency tuning word NCO is configured to be 1.8GHz, and the generated in-phase data and quadrature data are respectively subjected to digital up-conversion with the in-phase data and the quadrature data of the digital baseband. In-phase data passes through IDAC, quadrature data passes through Q DAC, and IDAC and Q DAC quadrature modulation are output.
The invention has the beneficial effects that: the device of the invention comprises: the device comprises an FPGA chip unit, a high-speed data converter unit, a power management unit, a clock management unit, a balun unit and a band-pass filter unit. The invention synthesizes S-band signals directly in frequency range of 2 GHz-3 GHz, has high output frequency, the modulator is realized in the high-speed data converter in a digital mode, LO and DAC inputs do not need to be calibrated to the quadrature modulator to inhibit LO leakage and interference images, the device only has one analog low-pass filter to filter data conversion images, the device has excellent spurious performance indexes, the device directly synthesizes RF signals in frequency, does not need to use traditional up-conversion or down-conversion with an analog radio link, greatly reduces the hardware quantity required to be deployed, has low spurious (the bandwidth is more than or equal to 1.2GHz, the spurious is more than or equal to 65 dBc), has simple hardware circuit, low cost, small volume and far smaller size than the same type products, is only 102 x 67 x 18mm3, and can well meet the requirements of practical application.
Drawings
Fig. 1 is a block diagram of an S-band signal direct frequency synthesizer according to the present invention.
Fig. 2 is a schematic block diagram of an 8-way parallel DDS in an embodiment of the present invention.
FIG. 3 is a block diagram of a power management unit system according to an embodiment of the present invention.
FIG. 4 is a block diagram of a system of clock management units according to an embodiment of the invention.
Detailed Description
The invention is further described below with reference to the drawings and examples.
As shown in fig. 1, an S-band signal direct frequency synthesizing apparatus of the present invention includes: the device comprises an FPGA chip unit, a high-speed data converter unit, a power management unit, a clock management unit, a balun unit and a band-pass filter unit.
The power management unit is respectively connected with the FPGA chip unit and the high-speed data converter unit; the clock management unit is respectively connected with the FPGA chip unit and the high-speed data converter unit; the FPGA chip unit is connected with the high-speed data converter unit; the high-speed data converter unit is connected with the balun unit; the balun unit is connected with the band-pass filter unit.
The FPGA chip unit comprises: baseband data generator module, JESD204B high speed serial interface.
The high-speed data converter unit, i.e. a high-speed DAC, comprises: JESD204B high-speed serial interface, digital processing path module, DAC core module.
The power management unit includes: singlechip, switching power supply, linear regulator LDO.
The clock management unit includes: power divider, quad divider, clock fan-out buffer.
In this embodiment, in the FPGA chip unit, the baseband data generator module includes: an in-phase data generator and a quadrature data generator.
The in-phase data generator and the quadrature data generator are both based on an 8-path parallel DDS technology of an XILINX FPGA, and continuous change of a plurality of DDS control words is realized in an interpolation mode by instantiating 8 serial DDS IP cores.
Fig. 2 is a schematic block diagram of an 8-channel parallel DDS, the working clock frequency of a single-channel DDS is 300mhz, the working clock frequency of the DDS is equivalently improved by the 8-channel parallel DDS, and the output bandwidth of the DDS is expanded to 2.4GHz. The 8 phase accumulators output 8 equally spaced phase codes simultaneously, thereby obtaining 8 waveform amplitude data. For any one way of phase accumulator, the phase step is 8 times the frequency control word. At the rising edge of each sampling clock, the phase accumulator can obtain 8 different phase codes, respectively from 8 different phase accumulators. Equivalent to interpolating 7 phase codes to each phase accumulator, the sampling frequency is increased by 8 times, i.e. the JESD204B data stream has a frequency of 2.4GHz.
The JESD204B high-speed serial interface uses a CDR clock recovery technology, a data interface clock is not needed, no channel offset exists, and the highest transmission rate can reach 12.5Gbps.
In this embodiment, in the high-speed data converter unit, the digital processing path module includes: a bypass, 2x or 3x selectable interpolator, three 2x interpolation half-band filters, a FIR85 interpolation filter, a frequency tuning word NCO.
The FIR85 interpolation filter works at 90% bandwidth, adopts a four-channel switch architecture of a DAC, and samples data on the rising edge or the falling edge of a DAC clock. This sampling approach samples new data at each clock edge, doubling the sampling rate of the DAC up to 12GSPS. This allows the signal image frequency to be extrapolated from fdac-fout to 2xfdac-fout, making it easier to filter the image using a filter.
The frequency tuning word NCO is a completely orthogonal 48-bit NCO, and no mirror frequency offset of an input data signal can be realized. The NCO generates a quadrature carrier for varying the center frequency of the input signal. The quadrature carrier is a pair of sine waves of the same frequency, offset by 90 °. The frequency of the orthogonal carrier is set by a frequency code. The quadrature carrier is mixed with in-phase data and quadrature data of the baseband data and then summed into the DAC cores of the quadrature and in-phase output data paths.
The DAC kernel module adopts a four-switch architecture. Only one pair of switches is used per half clock cycle, so each pair of switches will operate alternately at the clock edge, which masks the code dependent glitches that occur in existing dual switch architecture DAC cores.
Wherein, the high-speed data converter model is AD9164. The JESD204B high-speed serial interface is consistent with the JESD204B high-speed serial interface in the FPGA chip unit.
As shown in fig. 3, in the system block diagram of the power management unit, in this embodiment, the power management unit controls the timing sequence by controlling the enabling signals of 1 DCDC and 8 LDOs through a single chip microcomputer, the CPU core is 51 series, there are 18 IOs, and the power management unit is provided with an internal oscillator, and the package is only TSSOP20, and the size is small.
Wherein, the singlechip model is N76E003AT20.
Both the FPGA chip and the AD9164 have strict power-up sequences, and if the power-up sequences do not meet the requirements, the chip can work abnormally or even be damaged. The power management unit provides 1V, 1.2V, 1.8V and 3.3V with controllable time sequence for the FPGA chip unit; the high-speed data converter (AD 9164) unit is provided with 1.2V, 2.5V, and 3.3V whose timing is controllable. According to the power-on time sequence diagram of the FPGA chip and the AD9164, the singlechip sends out corresponding power control signals, so that power-on control is accurately completed.
As shown in fig. 4, in the system block diagram of the clock management unit, in this embodiment, the clock management unit generates 5 clock signals of the same source, including two SYSREF signals, one ref clock, one device clock, and one dac clock.
The SYSREF signal is used as a master timing reference in the JESD204B link to align the internal frequency division of the FPGA and AD9164 clocks, as well as to align the local multi-frame clocks of both. It must be an integer multiple of the multi-frame clock period, here 3.125MHz. The ref clock is used as a reference clock of the JESD204B IP core used by the FPGA and is configured to 300MHz by being capacitively ac-coupled to the GT transceiver dedicated clock pin of the FPGA. The device clock is the global clock of the FPGA. The dac clock is used as a reference clock for AD9164, and has a clock frequency of 4.8GHz as described above.
The external reference is a 4.8GHz clock signal, the power is divided into two paths after passing through a power divider, one path is converted into a differential clock signal dac clock through balun, and the other path generates a 1.2GHz clock signal after passing through a four-frequency divider. The clock fan-out buffer fans out the 1.2GHz clock signal by 4 paths of signals which are two paths of SYSREF signals respectively, one path of ref clock and one path of device clock. The fan-out register model AD9508, which has a 10-bit programmable divider, an integer divide ratio of 1 to 1024, up to 4 differential outputs. The FPGA controls the AD9508 chip through the SPI serial interface, so that the AD9508 chip generates 4 paths of clock signals with corresponding frequencies.
The power divider is of the type SIPS121SP4, and divides input external reference signals into two paths of reference 1 and reference 2, wherein the reference 1 is output to the balun unit, and the reference 2 is output to the four-frequency divider. The frequency divider model is SID027SP3. The clock fan-out buffer model is AD9508.
In the present embodiment, the balun unit converts the single-ended signal reference 1 into a differential signal dac clock as a reference clock signal for the high-speed data converter unit AD9164. The passband range of the band-pass filter unit is 2 GHz-3 GHz, and the in-band insertion loss is less than or equal to 2dB.
The embodiment also provides a direct frequency synthesis method of S-band signals, which comprises the following specific steps:
s1, starting a singlechip to work after a power management unit is powered on, sequentially generating an enabling signal 5 and an enabling signal 7, an enabling signal 6 and an enabling signal 9, an enabling signal 8, an enabling signal 1, an enabling signal 3, an enabling signal 4 and an enabling signal 2 at intervals of 1ms, controlling DCDC and LDO, and generating a time sequence controllable voltage signal to a high-speed data converter unit and an FPGA chip unit;
the enabling signals 5 to 9 control the power-on time sequence of the high-speed data converter unit; and the enabling signals 1 to 4 control the power-on time sequence of the FPGA chip unit.
S2, the clock management unit converts an external reference clock signal into five paths of differential clock signals;
wherein the dac clock is used as a reference clock signal for the high-speed data converter unit; the SYSREF1 signal acts as the master timing reference in the JESD204B link of the high speed data converter unit; the SYSREF2 signal is used as a main time sequence reference of the FPGA chip unit; the ref clock signal is used as a reference clock of a JESD204B IP core used by the FPGA chip unit, and is configured to be 300MHz through capacitive alternating current coupling to a special clock pin of a GT transceiver of the FPGA chip unit; the device clock signal is the global clock of the FPGA.
The frequency of the dac clock signal is 4.8GHz; the SYSREF1 signal and the SYSREF2 signal have a frequency of 3.125MHz; the frequency of the ref clock signal is 300MHz; the device clock signal frequency is 300MHz.
S3, utilizing logic resources of an FPGA chip unit to generate digital baseband data, and encoding according to a working mode of a JESD204B high-speed serial interface in the FPGA chip unit;
the baseband data generator module in the FPGA chip unit instantiates 8 serial DDS IP cores, the clock of each DDS IP core is 300MHz, the data rate is 2.4GHz, and any frequency modulation and phase modulation pulse baseband signal with the bandwidth of 1.2GHz is generated.
S4, transmitting digital baseband data generated by logic resources of the FPGA chip unit in the step S3 to a high-speed data converter unit through a JESD204B high-speed serial interface in the FPGA chip module unit, and establishing a JESD204B link;
the JESD204B link establishment includes: code set synchronization, initializing channel alignment sequences and user data.
The SYNC signal is used for synchronization signal, when the high-speed data converter AD9164 pulls the SYNC signal low, it marks that the link starts to be established, and when 4 consecutive K codes are received, the code group synchronization is completed, and the next stage is entered to initialize the channel alignment sequence.
At this stage, any channel offset can be absorbed by the FIFO memory, so that high-speed transmission of data can be ensured. In order to ensure stable operation of the AD9164 in the full temperature range, SERDES Lane Rate of JESD204B high-speed serial interface in the FPGA chip unit and the high-speed data converter unit is set to 8Gbps, FDAC frequency of the high-speed data converter AD9164 is 4.8GHz, and interpolation is 2. Remaining SERDES parameters: l:8, 8; m:2; f:1, a step of; s:2; k:32; n:16.
s5, based on the step S4, the high-speed data converter unit outputs a differential signal to the balun unit, the balun unit converts the differential signal output by the high-speed data converter AD9164 into a single-ended signal, and the single-ended signal is filtered by the band-pass filter unit to synthesize an S-band signal;
the FDAC frequency of the high-speed data converter AD9164 is 4.8GHz, and an FIR85 interpolation filter is used in the chip to filter data interpolation. The frequency of the frequency tuning word NCO is configured to be 1.8GHz, and the generated in-phase data and quadrature data are respectively subjected to digital up-conversion with the in-phase data and the quadrature data of the digital baseband. In-phase data passes through IDAC, quadrature data passes through Q DAC, and IDAC and Q DAC quadrature modulation are output.
In summary, the baseband data generator generates two orthogonal paths of IQ data, and after passing through the high-speed data converter, the S-band signal is synthesized. The power management unit provides various paths of voltage signals with controllable time sequence. The device can directly synthesize S-band signals without up-conversion or down-conversion links in the traditional sense, saves a large number of hardware circuits, saves a large space and has a size far smaller than that of the same type of products. In addition, have the advantage of two kinds of current baseband signal source devices concurrently, when output frequency is high, can guarantee outstanding spurious performance. The baseband signal source device adopting the technology has the advantages of small volume, high integration level and low price, and is suitable for large-scale, miniaturized and frequency synthesizer components.
The foregoing examples merely illustrate embodiments of the invention and are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of the invention should be assessed as that of the appended claims.
Claims (7)
1. An S-band signal direct frequency synthesizing apparatus comprising: the device comprises an FPGA chip unit, a high-speed data converter unit, a power supply management unit, a clock management unit, a balun unit and a band-pass filter unit;
the power management unit is respectively connected with the FPGA chip unit and the high-speed data converter unit; the clock management unit is respectively connected with the FPGA chip unit and the high-speed data converter unit; the FPGA chip unit is connected with the high-speed data converter unit; the high-speed data converter unit is connected with the balun unit; the balun unit is connected with the band-pass filter unit;
the FPGA chip unit comprises: a baseband data generator module, JESD204B high speed serial interface;
the high-speed data converter unit, i.e. a high-speed DAC, comprises: JESD204B high-speed serial interface, digital processing path module, DAC core module;
the power management unit includes: the system comprises a singlechip, a switching power supply and a linear voltage regulator LDO;
the clock management unit includes: power divider, quad divider, clock fan-out buffer.
2. The S-band signal direct frequency synthesizing apparatus according to claim 1, wherein in the FPGA chip unit, the baseband data generator module comprises: an in-phase data generator, a quadrature data generator;
the in-phase data generator and the quadrature data generator are both based on an 8-path parallel DDS technology of an XILINX FPGA, and continuous change of a plurality of DDS control words is realized in an interpolation mode by instantiating 8 serial DDS IP cores;
the JESD204B high-speed serial interface uses a CDR clock recovery technology, a data interface clock is not needed, no channel offset exists, and the highest transmission rate can reach 12.5Gbps.
3. The S-band signal direct frequency synthesizing apparatus according to claim 1, wherein in the high-speed data converter unit, the digital processing path module comprises: a bypass, a 2x or 3x selectable interpolator, three 2x interpolation half-band filters, a FIR85 interpolation filter, a frequency tuning word NCO;
the FIR85 interpolation filter works at 90% bandwidth, adopts a four-channel switch architecture of a DAC, and samples data on the rising edge or the falling edge of a DAC clock;
the frequency tuning word NCO is a completely orthogonal 48-bit NCO, so that no mirror frequency offset of an input data signal is realized;
the DAC kernel module adopts a four-switch architecture;
the model of the high-speed data converter is AD9164; the JESD204B high-speed serial interface is consistent with the JESD204B high-speed serial interface in the FPGA chip unit.
4. The direct frequency synthesizer of S-band signals according to claim 1, wherein the power management unit controls the timing sequence by controlling the enabling signals of 1 DCDC and 8 LDOs through a single chip microcomputer, the CPU core is 51 series, 18 IOs are provided with internal oscillators, and the package is TSSOP20 only;
wherein the model of the singlechip is N76E003AT20; the power management unit provides 1V, 1.2V, 1.8V and 3.3V with controllable time sequence for the FPGA chip unit; the high-speed data converter units are provided with 1.2V, 2.5V and 3.3V with controllable timing.
5. The direct frequency synthesizer of S-band signals according to claim 1, wherein in the clock management unit, the clock management unit generates 5 homologous clock signals, including two SYSREF signals, one ref clock, one device clock and one dac clock;
the power divider is of the type SIPS121SP4, and divides input external reference signals into two paths of reference 1 and reference 2, wherein the reference 1 is output to the balun unit, and the reference 2 is output to the four-frequency divider; the frequency divider model is SID027SP3; the clock fan-out buffer model is AD9508.
6. An S-band signal direct frequency synthesizing apparatus according to claim 1, wherein the balun unit converts single-ended signal reference 1 into differential signal dac clock as a reference clock signal of the high-speed data converter unit AD9164; the passband range of the band-pass filter unit is 2 GHz-3 GHz, and the in-band insertion loss is less than or equal to 2dB.
7. A direct frequency synthesis method of S-band signals comprises the following specific steps:
s1, starting a singlechip to work after a power management unit is powered on, sequentially generating an enabling signal 5 and an enabling signal 7, an enabling signal 6 and an enabling signal 9, an enabling signal 8, an enabling signal 1, an enabling signal 3, an enabling signal 4 and an enabling signal 2 at intervals of 1ms, controlling DCDC and LDO, and generating a time sequence controllable voltage signal to a high-speed data converter unit and an FPGA chip unit;
the enabling signals 5 to 9 control the power-on time sequence of the high-speed data converter unit; the enabling signals 1 to 4 control the power-on time sequence of the FPGA chip unit;
s2, the clock management unit converts an external reference clock signal into five paths of differential clock signals;
wherein the dac clock is used as a reference clock signal for the high-speed data converter unit; the SYSREF1 signal acts as the master timing reference in the JESD204B link of the high speed data converter unit; the SYSREF2 signal is used as a main time sequence reference of the FPGA chip unit; the ref clock signal is used as a reference clock of a JESD204B IP core used by the FPGA chip unit, and is configured to be 300MHz through capacitive alternating current coupling to a special clock pin of a GT transceiver of the FPGA chip unit; the device clock signal is the global clock of the FPGA;
the frequency of the dac clock signal is 4.8GHz; the SYSREF1 signal and the SYSREF2 signal have a frequency of 3.125MHz; the frequency of the ref clock signal is 300MHz; the frequency of the device clock signal is 300MHz;
s3, utilizing logic resources of an FPGA chip unit to generate digital baseband data, and encoding according to a working mode of a JESD204B high-speed serial interface in the FPGA chip unit;
the baseband data generator module in the FPGA chip unit instantiates 8 serial DDS IP cores, the clock of each DDS IP core is 300MHz, the data rate is 2.4GHz, and any frequency modulation and phase modulation pulse baseband signal with the bandwidth of 1.2GHz is generated;
s4, transmitting digital baseband data generated by logic resources of the FPGA chip unit in the step S3 to a high-speed data converter unit through a JESD204B high-speed serial interface in the FPGA chip module unit, and establishing a JESD204B link;
the JESD204B link establishment includes: code set synchronization, initializing a channel alignment sequence and user data;
the SYNC signal is used for synchronizing signal, when the high-speed data converter AD9164 pulls down the SYNC signal, it marks that the link starts to be established, when 4 continuous K codes are received, the code group synchronization is completed, and the next stage is entered to initialize the channel alignment sequence;
SERDES Lane Rate of JESD204B high-speed serial interface in the FPGA chip unit and the high-speed data converter unit is set to 8Gbps, FDAC frequency of the high-speed data converter AD9164 is 4.8GHz, and interpolation is 2; remaining SERDES parameters: l:8, 8; m:2; f:1, a step of; s:2; k:32; n:16;
s5, based on the step S4, the high-speed data converter unit outputs a differential signal to the balun unit, the balun unit converts the differential signal output by the high-speed data converter AD9164 into a single-ended signal, and the single-ended signal is filtered by the band-pass filter unit to synthesize an S-band signal;
the FDAC frequency of the high-speed data converter AD9164 is 4.8GHz, and an FIR85 interpolation filter is used in the chip to filter data interpolation; the frequency of the frequency tuning word NCO is configured to be 1.8GHz, and the generated in-phase data and quadrature data are respectively subjected to digital up-conversion with the in-phase data and the quadrature data of the digital baseband; in-phase data passes through IDAC, quadrature data passes through Q DAC, and IDAC and Q DAC quadrature modulation are output.
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