CN117807933A

CN117807933A - Signal processing method and device, chip and electronic equipment

Info

Publication number: CN117807933A
Application number: CN202211207756.4A
Authority: CN
Inventors: 张辰旸; 刘衡祁; 徐华锋; 林忱; 郭彬; 夏茂盛; 王庆华
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2024-04-02
Also published as: WO2024066950A1

Abstract

The embodiment of the application discloses a signal processing method, a device, a chip and electronic equipment, so as to improve the reliability and stability of a circuit system. The method comprises the following steps: receiving at least one input target signal, determining at least one output target signal having a logical relationship with the at least one input target signal; determining a first output target signal influenced by the currently released input target signal according to the logic relation under the condition that the release of the input target signal in the effective state is detected; and controlling the first output target signal to perform synchronous release under the clock domain of the input clock signal, and delaying output after a first number of preset clock cycles.

Description

Signal processing method and device, chip and electronic equipment

Technical Field

The present disclosure relates to the field of digital integrated circuits, and in particular, to a signal processing method, a signal processing device, a chip, and an electronic device.

Background

With rapid development and wide application of technologies such as 5G (5 th Generation Mobile Communication Technology, fifth generation mobile communication technology), image and data processing, automatic driving, etc., IC (Integrated Circuit ) products need to integrate more and more functions to meet market demands, the corresponding IC designs, especially SOC (System on Chip) Chip designs, are increasingly large in scale, and the number of integrated IPs (Intellectual Property ) is increased, so that the requirements on the design quality of the time-reset System are greatly increased.

Chip designers guarantee the normal reset function and the stability of the circuit system by designing different types of resets. In general, to ensure the normal reset function, a circuit is required to realize asynchronous reset and synchronous release. The traditional single-period synchronous release mode has high requirements on circuit implementation difficulty, hardware cost, labor cost and the like, is poor in processing, and easily causes potential metastable state to propagate in the circuit in the synchronous release process of the reset signal, so that the circuit function is abnormal. Therefore, there is a need to solve the above-mentioned technical problems in the prior art.

Disclosure of Invention

The embodiment of the application aims to provide a signal processing method, a device, a chip and electronic equipment, so as to improve the reliability and stability of a circuit system.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a signal processing method, including:

receiving at least one input target signal, determining at least one output target signal having a logical relationship with the at least one input target signal;

determining a first output target signal influenced by the currently released input target signal according to the logic relation under the condition that the release of the input target signal in the effective state is detected;

And controlling the first output target signal to perform synchronous release under the clock domain of the input clock signal, and delaying output after a first number of preset clock cycles.

In a second aspect, an embodiment of the present application provides a signal processing apparatus, including a signal processing module, a data synchronizer module, and a delay beat module, where:

the signal processing module is used for receiving at least one input target signal and determining at least one output target signal with a logic relationship with the at least one input target signal; determining a first output target signal influenced by the currently released input target signal according to the logic relation and indicating the data synchronizer module under the condition that the release of the input target signal in the effective state is detected;

the data synchronizer module is used for controlling the first output target signal to be synchronously released under the clock domain of the input clock signal and providing the first output target signal after synchronous release for the delay beating module;

the delay beating module is used for controlling the first output target signal after synchronous release to be delayed to be output after a first number of clock cycles are preset.

In a third aspect, embodiments of the present application provide a chip, the chip including a processor and a communication interface, the communication interface and the processor being coupled, the processor being configured to execute a program or instructions to implement a method according to the first aspect.

In a fourth aspect, embodiments of the present application provide an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, the program or instructions being executable by the processor to implement a method as described in the first aspect.

According to the signal processing scheme provided by the embodiment of the application, at least one output target signal can be determined according to at least one input target signal, a logic relationship between the at least one output target signal and the at least one input target signal is established, under the condition that one or more input target signals in an effective state are released, a first output target signal influenced by the currently released input target signal is determined according to the logic relationship, and after the first output target signal is controlled to be synchronously released, the operation of delaying output after a preset first number of clock cycles is added. The release of the target signal is not required to be completed within one clock period in the circuit function, so that the constraint on the target signal can be relaxed in the circuit implementation stage, and particularly, the time sequence convergence difficulty can be remarkably reduced in a scene with larger design scale and more complexity, and the circuit implementation and the related labor investment and time cost are reduced; and the final released target signal is ensured to be in a stable state by carrying out delay output on the target signal after synchronous release, so that the stability and the reliability of the circuit system are improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

fig. 1 is a schematic flow chart of a signal processing method according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a signal processing device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a reset signal processing device according to an embodiment of the present application;

fig. 4 is a flowchart of a reset signal processing method according to an embodiment of the present application;

fig. 5 is a schematic diagram of an exemplary application scenario of a reset signal processing method according to an embodiment of the present application;

fig. 6 to 11 are simulation waveform diagrams of various reset signal release conditions in the application scenario shown in fig. 5 according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

As mentioned above, SOC chip designs are increasingly demanding on clock reset systems as the scale of digital integrated circuits increases and the clock frequency increases. In general, to ensure the normal reset function, a circuit is required to realize asynchronous reset and synchronous release. Asynchronous reset means that the effect of the reset signal depends only on the reset signal itself, is irrelevant to a clock, and when the reset signal is effective, no matter what state the clock signal is in, the circuit can be reset immediately; the synchronous release refers to release of the reset signal, and is controlled by a clock, and released at a jump edge of a clock signal of a clock domain where the reset signal is located, wherein the jump edge can be a rising edge or a falling edge. Asynchronous reset can ensure that the circuit responds in time when the reset signal is asserted, without the situation that part of the circuit has entered a reset state while another part of the circuit is still operating. The synchronous release requires that the registers driven by the same clock can finish the release of the reset signal in the same clock period, so that the circuits in the same clock domain are ensured to be in the same state, and errors in the data transmission process are avoided.

The inventor finds that in the invention process, in a clock reset system, the following defects exist in the design of asynchronous reset and synchronous release:

1) Along with the increasing of chip area, the clock frequency of the design is higher and higher, and the traditional single-period synchronous release mode functionally requires all registers driven by reset signals to release the reset signals in one clock period, so that the reset signals are very strictly constrained in a circuit implementation stage, and the difficulty of timing convergence and circuit implementation and the time and labor cost required to be input are greatly increased.

2) In general, the clock signal of the driving register is kept in an open state in the whole stage of the effective and released state of the reset signal, if the asynchronous reset path is longer, when the reset signal is released, even if the reset signal is synchronously released in the clock domain where the register is located, the release of the reset signal still can be difficult to complete in one clock cycle, so that the risk of metastable state transmission exists when the reset signal is released, the register in the same clock domain can be in different states, and circuit function abnormality can be caused in serious cases.

3) The common asynchronous reset synchronous release design has only one input reset signal, and the whole circuit is controlled to reset by one reset signal, so that the control of the circuit lacks flexibility, and a part of the circuit or a single path is usually required to be reset according to actual requirements. The expansion of chip size and the increase of integrated IP also make it necessary to divide the chip into a plurality of reset domains, but the common design of the clock reset system can only reset one reset domain.

In view of the foregoing, embodiments of the present application are directed to a signal processing method and apparatus to improve reliability and stability of a circuit system. Further, flexible control of different signal domains is realized, and potential metastable state transmission risks in the signal synchronous release process are avoided.

The signal processing scheme provided by the embodiment of the application is suitable for the design of a clock reset system in an SOC chip and is used for processing reset signals; the scheme is particularly suitable for a plurality of reset domains and is applied to an SOC chip with high quality requirements on reset signals; the signal processing scheme provided by the embodiment of the application can be applied when the same or similar processing as the reset signal is performed on some control signals according to the requirements in the chip design. In the embodiment of the present application, the reset signal, the control signal, and the like are collectively referred to as a target signal.

The main technical conception of the application comprises: the signal processing scheme is designed, through delaying output of the target signal after synchronous release and turn-off control of the output clock signal (namely, the clock domain where the target signal is located after synchronous release), the target signal and a register driven by the clock domain where the target signal is located are ensured not to be in a working state before the output target signal is stable, and the risk that potential metastable state signals are transmitted in a circuit system due to release of the target signal is avoided; further, a signal processing scheme suitable for multiple signal domains is designed, one or more input target signals are supported, and the signal domains which can be controlled by the target signals can be set according to requirements, so that the independent control of partial circuits or different paths of the circuit system is realized, or all the circuits are controlled.

The signal Domain refers to a minimum circuit unit that can be controlled by a target signal, and one circuit system generally includes a plurality of signal domains, and one signal Domain may correspond to a part of a circuit or a single path in the circuit system, and illustratively, in the case that the target signal is a Reset signal, the signal Domain is a Reset Domain (Reset Domain) correspondingly. Based on the circuit design, the difficulty and cost of circuit realization are greatly reduced, and the reliability is improved.

The following describes in detail the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

Referring to fig. 1, a flowchart of a signal processing method according to an embodiment of the present application is provided, and the method may include the following steps:

s101, at least one input target signal is received, and at least one output target signal with a logic relationship with the at least one input target signal is determined.

For single signal domain scenarios, typically only one input target signal controls the entire circuit, and correspondingly only one output target signal.

In an alternative implementation, for a scenario of multiple signal domains, each of the input target signals may control one or more signal domains, each of the output target signals may control one signal domain, one output target signal corresponding to each of the signal domains may be determined according to all of the signal domains controlled by the at least one input target signal, and the logical relationship is established based on the at least one input target signal and the signal domain controlled by the at least one output target signal.

For example, assuming that, in the two input target signals, the signal domain controlled by the input target signal 1 is the signal domain 1, the signal domain 2, and the signal domain 3, and the signal domain controlled by the input target signal 2 is the signal domain 2, all the signal domains controlled by the two input target signals are the signal domain 1, the signal domain 2, and the signal domain 3; accordingly, one output target signal 1 corresponding to the signal domain 1, one output target signal 2 corresponding to the signal domain 2, and one output target signal 3 corresponding to the signal domain 3 can be determined.

Specifically, the at least one input target signal may further have a priority relationship therebetween; determining all of the input target signals affecting each of the output target signals based on at least one signal domain controlled by each of the input target signals and a signal domain controlled by each of the output target signals, and determining the logical relationship in combination with a priority relationship between the at least one input target signal; wherein the logic relationship is used for representing a logic operation relationship based on priority among all the input target signals affecting each output target signal.

S102, under the condition that the release of the input target signal in the effective state is detected, determining a first output target signal influenced by the input target signal released currently according to the logic relation.

The target signal typically includes two states: an active state and an inactive state. For the reset signal, the valid state is a state after the reset signal is validated, and is generally referred to as a reset state; the invalid state is the state after the validated reset signal is released; the reset signal may be active low or active high.

In the case that release of one or more input target signals in an active state is detected, one or more output target signals affected by the currently released input target signals can be determined according to a logic relationship between at least one input target signal and at least one output target signal. For convenience of description, in the embodiment of the present application, one or more output target signals affected by the currently released input target signal are referred to as a first output target signal.

S103, controlling the first output target signal to perform synchronous release under the clock domain of the input clock signal, and delaying output after a first number of clock cycles are preset.

The synchronous release is that the target signal is released, and is controlled by a clock, and released at the jump edge of the clock signal of the clock domain where the target signal is located, wherein the jump edge can be a rising edge or a falling edge; after controlling the first output target signal for synchronous release, the operation of delaying the output after a preset first number of clock cycles is added, that is, the target signal is not required to complete release within one clock cycle at the circuit function.

In an alternative implementation manner, after the control of the synchronous release of the first output target signal under the clock domain of the input clock signal, the output clock signal under the clock domain may be controlled to be delayed to be turned off after a preset second number of clock cycles and turned on again after a preset third number of clock cycles, where the first number is greater than the second number and less than the sum of the second number and the third number.

Specifically, under the condition that the first output target signal after synchronous release is detected, a control signal under the clock domain can be generated; the control signal is used for indicating the output clock signal to be delayed to be turned off after a second number of clock cycles and turned on again after a third number of clock cycles;

and generating a clock gating signal in the clock domain according to the control signal in the clock domain, and controlling the turn-off and turn-on of an output clock signal in the clock domain through the clock gating signal.

Specifically, the first number may be a sum of a preset first value M and a preset second value N, the second number may be the first value M, and the third number may be a sum of the second value N and a preset third value P; the first value M may be set as a number of stages of a longest register chain without a target signal input end in the register driven by the first output target signal; the second value N may be set to a clear time (remove time) between the first output target signal and the output clock signal; the third value P may be set to a recovery time (recovery time) between the first output target signal and the output clock signal.

In an alternative implementation, the method may further include the steps of:

and S104, under the condition that the input target signal in the invalid state is detected to be effective, determining a second output target signal influenced by the input target signal which is currently effective according to the logic relation.

In the case that release of one or more input target signals in an invalid state is detected, one or more output target signals affected by the currently released input target signals can be determined according to a logic relationship between at least one input target signal and at least one output target signal. For convenience of description, one or more output target signals affected by the currently released input target signal will be referred to as a second output target signal in the embodiments of the present application.

S105, controlling the second output target signal to take effect asynchronously and output the second output target signal immediately.

Asynchronous validation means that the validation of the target signal depends only on the target signal itself, is independent of the clock, and when the target signal is validated, no matter what state the clock signal is in, the circuit immediately responds to the state required by the target signal entering into validation.

Under the condition that one or more input target signals take effect, determining a second output target signal influenced by the input target signal which takes effect currently according to a logic relation, and controlling the second output target signal to take effect asynchronously and output the second output target signal immediately, so that a circuit system can respond quickly to the asynchronous effect, and high-quality target signals are ensured to be output.

According to the signal processing method provided by the embodiment of the invention, at least one output target signal can be determined according to at least one input target signal, a logic relation between the at least one output target signal and the at least one input target signal is established, under the condition that one or more input target signals in an effective state are released, a first output target signal influenced by the currently released input target signal is determined according to the logic relation, and after the first output target signal is controlled to be synchronously released, the operation of delaying output after a preset first number of clock cycles is added. The release of the target signal is not required to be completed within one clock period in the circuit function, so that the constraint on the target signal can be relaxed in the circuit implementation stage, and particularly, the time sequence convergence difficulty can be remarkably reduced in a scene with larger design scale and more complexity, and the circuit implementation and the related labor investment and time cost are reduced; and the final released target signal is ensured to be in a stable state by carrying out delay output on the target signal after synchronous release, so that the stability and the reliability of the circuit system are improved.

Further, after the first output target signal is controlled to be synchronously released, the output clock signal is controlled to be turned off after the second number of clock cycles and turned on again after the third number of clock cycles, so that the circuit driven by the clock signal and the target signal can not be in a working state before the target signal after synchronous release is not stably transmitted to all the driven registers, and abnormal circuit state is avoided.

Furthermore, when the target signal is released, on one hand, the target signal after synchronous release is delayed to be output, and on the other hand, the output clock signal is turned off, so that the potential metastable state propagation risk caused by the asynchronous relation between the target signal and the clock signal in the synchronous release process of the target signal is effectively avoided through the double-insurance design.

In addition, corresponding to the signal processing method shown in fig. 1, the embodiment of the application also provides a signal processing device. An embodiment of the present application provides a signal processing apparatus, as shown in fig. 2, including a signal processing module 201, a data synchronizer module 202, and a delay beat module 203, where:

the signal processing module 201 is configured to receive at least one input target signal, and determine at least one output target signal having a logical relationship with the at least one input target signal; in case a release of the input target signal in an active state is detected, a first output target signal affected by the currently released input target signal is determined according to the logical relation and the data synchronizer module 202 is instructed.

Specifically, in the case that the input target signal is a reset signal, the signal processing module may be a reset processing module for correspondingly processing the reset signal; in the case where the input target signal is a control signal, the signal processing module may be a control processing module for processing the control signal accordingly.

The data synchronizer module 202 is configured to control the first output target signal to perform synchronization release under a clock domain of an input clock signal, and provide the first output target signal after the synchronization release to the delay beat module 203.

The delay beating module 203 is configured to control the first output target signal after the synchronization release to delay outputting after a preset first number of clock cycles.

In an alternative implementation, the apparatus may further include: a clock gating generation unit 204 and a clock gating unit 205, wherein:

the delay beating module 203 is further configured to generate, when the first output target signal after the synchronization release is received, a control signal under the clock domain and send the control signal to the clock gating generation unit 204, where the control signal is configured to instruct the output clock signal to be delayed to be turned off after a preset second number of clock cycles and to be turned on again after a preset third number of clock cycles, where the first number is greater than the second number and less than a sum of the second number and the third number;

The clock gating generation unit 204 is configured to generate a clock gating signal in the clock domain according to the received control signal, and send the clock gating signal to the clock gating unit;

the clock gating unit 205 is configured to control the turn-off and turn-on of the output clock signal under the clock domain according to the received clock gating signal.

In an alternative implementation manner, the signal processing module 201 is further configured to, in a case where the input target signal in the inactive state is detected to be active, determine, according to the logic relationship, a second output target signal affected by the input target signal that is currently active, and instruct the data synchronizer module 202;

the data synchronizer module 202 is further configured to control the second output target signal to perform asynchronous validation, and provide the second output target signal after the asynchronous validation to the delay beat module 203;

the delay beating module 203 is further configured to control the second output target signal to be immediately output after the asynchronous effect.

In an alternative implementation, the same number of data synchronizer modules 202 and delay beat modules 203 as the number of signal domains may be provided, and each signal domain corresponds to a set of data synchronizer modules 202 and delay beat modules 203;

The signal processing module 201 is specifically configured to determine, according to all signal domains controlled by the at least one input target signal, one output target signal corresponding to each signal domain in the all signal domains, and establish the logical relationship based on the at least one input target signal and the signal domain controlled by the at least one output target signal; in the case that the first output target signal is determined, indicating a data synchronizer module 202 corresponding to a signal domain controlled by the first output target signal; wherein each of said input target signals controls at least one signal domain, and each of said output target signals controls one signal domain;

the data synchronizer module 202 is specifically configured to provide the first output target signal after the synchronization release to the corresponding delay beat module 203.

Specifically, the at least one input target signal may have a priority relationship therebetween;

the signal processing module 201 is specifically configured to determine all the input target signals affecting each of the output target signals according to at least one signal domain controlled by each of the input target signals and a signal domain controlled by each of the output target signals, and determine the logic relationship in combination with a priority relationship between the at least one input target signals; wherein the logic relationship is used for representing a logic operation relationship based on priority among all the input target signals affecting each output target signal.

Obviously, the signal processing device according to the embodiment of the present application may be used as an execution body of the signal processing method shown in fig. 1, so that the signal processing device can implement the functions implemented by the method shown in fig. 1. Since the principle is the same, the description is not repeated here.

The following describes in detail the signal processing scheme provided in the embodiment of the present application, taking the reset signal as an example.

The embodiment of the application provides a Reset signal processing scheme which can support application scenes of multiple Reset domains (Reset domains), and provides a solution with perfect functions, high reliability, low cost and small implementation difficulty for the design of a clock Reset system. On one hand, the scheme supports a plurality of input reset signals, can set a reset domain which can be controlled by the reset signals according to requirements so as to realize independent reset of different paths of a circuit or reset of all circuits, and on the other hand, the scheme ensures that a register driven by the reset signals and the clock domain in which the reset signals are positioned is not in a working state before the output reset signals are stable by carrying out delay output on the reset signals after synchronous release and carrying out turn-off control on output clock signals (namely the clock domain in which the reset signals are positioned after synchronous release), thereby avoiding the risk of transmission of potential metastable signals in a circuit system caused by release of the reset signals. Meanwhile, based on the circuit design, the difficulty and cost of circuit implementation are greatly reduced, and the reliability is improved.

An embodiment of the application provides a reset signal processing device, and a schematic structural diagram of the reset signal processing device refers to fig. 3, and the reset signal processing device includes a reset processing module, a data synchronizer module and a delay beat module, the number of which is the same as that of reset domains, a clock gating generation unit, and a clock gating unit, where each reset domain corresponds to a group of data synchronizer modules and delay beat modules.

The reset signal processing device provided by the embodiment of the application supports a plurality of input and output reset signals, supports one or more input clock signals and the same number of output clock signals, and in order to support a multi-clock domain scene, the clock gating generation unit and the clock gating unit may include a plurality of groups. Wherein:

the input reset signals are asynchronous, or priority relation can exist, the reset signal with high priority can control the reset signal with low priority, and the reset signal with low priority can only control part of the output reset signals. There is no requirement of asynchronous relation between the input clock signals and the input reset signals. The output clock signal and the input clock signal are in synchronous relation, the output reset signal and the input reset signal are in asynchronous relation, and the output clock signal are in synchronous relation.

According to the reset signal processing device provided by the embodiment of the application, aiming at the functions and scene requirements of asynchronous reset and synchronous release, a reset processing module for inputting reset signals to multiple reset domains is added, and a beating delay module, a clock gating unit and the like are used for controlling the reset signals and the clock signals. The following describes each functional module in the reset signal processing apparatus in detail:

a reset processing module, configured to receive at least one input reset signal and determine at least one output reset signal having a logical relationship with the at least one input reset signal using a combinational logic design; under the condition that the release of the input reset signal in the reset state is detected, determining a first output reset signal influenced by the input reset signal which is released currently according to the logic relation, and indicating a data synchronizer module corresponding to a reset domain controlled by the first output reset signal; determining a second output reset signal influenced by the currently validated input reset signal according to the logic relationship and indicating a data synchronizer module corresponding to a reset domain controlled by the second output reset signal under the condition that the input reset signal in an invalid state is detected to be validated (namely reset); wherein each input reset signal controls at least one reset domain, each output reset signal controls one reset domain, and different output reset signals control different reset domains.

The data synchronizer module can be a multi-stage register synchronizer, and the main function of the data synchronizer module is to realize synchronous release of an asynchronous reset signal under a designated clock domain through synchronous processing. By synchronizing the reset signal to the desired clock domain for release, the probability of metastability that may occur due to crossing the clock domain when the reset signal is released may be reduced. Specific:

the data synchronizer module is corresponding to the reset domain controlled by the first output reset signal and is used for controlling the first output reset signal to be synchronously released under the clock domain of the input clock signal and providing the first output reset signal after synchronous release for the corresponding delay beating module;

and the data synchronizer module is corresponding to the reset domain controlled by the second output reset signal and is used for controlling the second output reset signal to carry out asynchronous reset and providing the second output reset signal after asynchronous reset for the corresponding delay beating module.

The delay beating module has the function of utilizing beating logic to output a reset signal after beating by matching with the data synchronizer module, so as to realize delay output of the reset signal after synchronous release. The delay beat module supports beat stage number through parameter setting, and the delay beat number of the output clock signal turn-off, the reset signal output and the output clock signal reopening can be configured according to requirements. Through the processing of the delay beating module, as long as any reset signal is released, the output clock signal is turned off after M clock cycles, after waiting for N clock cycles, the release of the reset signal after synchronous release is completed after delay output, and after waiting for P clock cycles, the output clock signal is enabled again. Under the condition that the reset signal is released, when the delay beating module outputs the reset signal, one control signal under the corresponding clock domain is generated and sent to the clock gating generation unit, and the control signal is used for indicating that the output clock signal is delayed to be turned off after M clock cycles and turned on again after N+P clock cycles.

And the clock gating generation unit is used for generating a clock gating signal in the clock domain according to the received control signal and sending the clock gating signal to the clock gating unit, wherein the clock gating signal is used for controlling the turn-off and turn-on of the output clock signal.

The clock gating unit is used for controlling the output of the clock signal according to the received clock gating signal, and completing the delayed turn-off and the re-turn-on of the output clock signal according to the configured period number after the synchronous release of the output reset signal. The clock gating unit can support control over a plurality of output clocks, and most application scene requirements are met.

According to the reset signal processing device provided by the embodiment of the application, under the condition that a reset signal is effective (reset), the circuit system can respond to asynchronous reset quickly. Under the condition that the reset signal is released, on one hand, the reset signal which is finally output is ensured to be in a stable state by delaying and outputting the reset signal after synchronous release, and on the other hand, the output clock signal is turned off, so that the circuit which is driven by the clock signal and the reset signal can not be in a working state before the released reset signal is not stably transmitted to all the driven registers, and the abnormal state of the circuit is avoided. Through the double insurance, the potential metastable state propagation risk caused by the asynchronous relation of the reset signal and the clock signal in the synchronous release process of the reset signal is effectively avoided. Meanwhile, the output clock signal is turned off and turned on, the number of beats of the reset signal delayed output can be flexibly configured according to actual requirements, and the reset signal is not required to be released in one clock period in the circuit function, so that the constraint on the reset signal can be relaxed in the circuit implementation stage, particularly in the scene of larger and more complex design scale, the time sequence convergence difficulty can be obviously reduced, the stability and reliability of a circuit system are further ensured, and the universality, usability and portability of the SOC chip are also improved.

According to the reset signal processing device provided by the embodiment of the application, through delaying the design of outputting the reset signal after synchronous release and turning off the output clock, the difficulty and cost of circuit implementation stage timing sequence convergence and circuit design are reduced, the stability of a clock reset system is improved, and meanwhile the universality and usability of the circuit are reserved. The scheme is suitable for the design of clock reset systems of most SOC chips, and can flexibly realize the reset of all or part of circuits according to actual requirements for the support of multiple reset domains.

Referring to fig. 4, a flowchart of a reset signal processing method according to an embodiment of the present application is provided, and the method may include the following steps:

s401, at least one reset signal is input into a reset processing module, wherein the at least one input reset signal is in an asynchronous relationship.

S402, the reset processing module performs first processing on at least one input reset signal and outputs at least one processed reset signal, wherein at least one output reset signal is in an asynchronous relationship, and at least one input reset signal and at least one output reset signal have a logic relationship, and the logic relationship is established according to actual needs.

The reset signals of the outputs processed by the reset processing module control different reset domains, each input reset signal can realize the control of all reset domains or one or more reset domains, the input reset signals can also have priority, and each reset signal output by the reset processing module can realize the control of one reset domain. The number of the reset signals output by the reset processing module is equal to the number of the reset domains controlled by all the input reset signals, and the logic relation is determined according to the reset domains controlled by the input reset signals, the priority and the reset domains controlled by the output reset signals.

And outputting a reset signal processed by the reset processing module, and subsequently carrying out secondary processing by the data synchronizer module and the delay beating module.

S403, detecting whether one or more input reset signals in an invalid state are valid (namely resetting), if yes, executing step S404, and if not, executing step S406.

S404, the reset processing module determines one or more output reset signals (which may be called second output reset signals) affected by the input reset signals currently in effect according to the logic relation, and instructs the corresponding data synchronizer module.

And S405, the data synchronizer module and the delay beating module respond immediately, namely control the second output reset signal to take effect asynchronously and output immediately, so as to ensure that the second output reset signal is timely and effective.

S406, detecting whether one or more input reset signals in a reset state are released, and if so, executing step S407.

S407, the reset processing module determines one or more output reset signals (which may be referred to as first output reset signals) affected by the currently released input reset signals according to the logic relationship, and instructs the corresponding data synchronizer module.

S408, the data synchronizer module synchronously releases the first output reset signal under the clock domain of the input clock signal.

Specifically, the data synchronizer module performs beat processing to synchronize the asynchronous reset signal to the clock domain of the input clock signal.

S409, the reset signal after the synchronous release of the data synchronizer module is subjected to beat processing by the delay beat module, and an output reset signal and a control signal for controlling the output clock signal switch are generated.

Specifically, the delay beating module sequentially performs operations such as controlling the output clock signal to turn off after M clock cycles according to the configured parameters, outputting the reset signal after synchronous release after N clock cycles, and controlling the output clock signal to be turned on again after P clock cycles (i.e. after waiting for stable output of the reset signal). Ensuring that the output reset signal is already in a steady state and avoiding that registers driven by the output clock signal and the reset signal will remain in operation while the reset signal is potentially metastable.

It should be noted that, there is no strict timing relationship between S403 and S406, and the numbering is only for convenience of description.

Next, an exemplary description is given of a reset signal processing scheme provided in the embodiment of the present application.

Referring to fig. 5, a typical application scenario of a reset signal processing method according to an embodiment of the present application is provided. In the present embodiment, it is assumed that 3 input reset signals hw_rst_b, top_sw_rst_b, and local_sw_rst_b,2 input clock signals clk_in_1x and clk_in_2x having a 2-frequency-multiplication relationship, and finally 2 output reset signals top_sw_rst_sync_b and local_sw_rst_sync_b, and 2 output clock signals clk_out_1x and clk_out_2x are used. In the application scene, the following functional modules in the reset signal processing device are needed to be used, wherein the functional modules comprise a reset processing module, two groups of data synchronizer modules, a delay beating module, two groups of clock gating generating units and a clock gating unit.

The reset processing module performs a first step of processing on the 3 input reset signals, and determines a logical relationship between the 2 output reset signals and the 3 input reset signals by using combinational logic. The specific logic operation relation based on priority between the output reset signal and the input reset signal is as follows:

top_sw_rst_sync_b＝hw_rst_b&top_sw_rst_b；

local_sw_rst_sync_b＝hw_rst_b&top_sw_rst_b&local_sw_rst_b；

As described above, in the inputted reset signal, hw_rst_b is a reset source for resetting the entire circuit system; top_sw_rst_b is a reset source of the reset configuration path, is influenced by hw_rst_b, and if hw_rst_b is in a reset state, top_sw_rst_b is also necessarily in the reset state, otherwise; local_sw_rst_b is the reset source of the reset data path, is affected by hw_rst_b and top_sw_rst_b, and if hw_rst_b and top_sw_rst_b are in the reset state, then local_sw_rst_b must also be in the reset state, and vice versa.

When either of hw_rst_b and top_sw_rst_b is reset active, both top_sw_rst_sync_b and local_sw_rst_sync_b remain in the reset state, and clk_out_1x clock and clk_out_2x clock remain active. When only the local_sw_rst_b reset is valid, only the local_sw_rst_sync_b remains in the reset state, and the top_sw_rst_sync_b is not affected.

The data synchronizer module can be a 1-bit-wide multi-stage register synchronizer for realizing the synchronous release of the reset signal. After the reset signal is released, the data is subjected to multistage register beating, a high-level signal which is in the same clock domain as the input clock signal is output, and the high-level signal is used as the reset signal after synchronous release and is provided for a delay beating module for further processing. The beat count of the register is designed according to the requirement of MTBF (Mean Time Between Failures, mean time between failure) to ensure that the output reset signal is not in a metastable state.

The delay beat module can beat the signal output by the data synchronizer module for the second time. After the input signal is beaten at the M level, 2 branches are generated from the beaten signal at the time, logic operation is carried out on the signal of one branch, N-level beaten is carried out on the signal of the other unprocessed branch, and the beaten signal at the time can be used as a reset signal finally output. And finally, continuously performing P-level beating, performing secondary operation on the signals after beating and the signals which are independently processed after the previous M-level beating, and sending the signals after operation to the 2 clock gating generation units as control signals.

The clock gating generation unit carries out reprocessing on the control signal output by the delay beating module, and generates a clock gating signal for the clock gating unit. If a plurality of output reset signals are released under the same clock domain, the clock gating signals are generated by control signals output by all delay beating modules. In this embodiment, the control signals output by the 2 delay beat modules all participate in the generation of the clock gating signals, so that any one of the output reset signals is released, and the clock gating signals can be pulled down and 2 output clock signals can be turned off in M clock cycles after the release of the reset signals. And only after the release of m+n+p clock cycles is completed for 2 output reset signals, the clock gating signal will be pulled up again and 2 output clock signals are turned on again. In the embodiment shown in fig. 5, the clock gating generation unit 1 controls clk_out_1x, where 2 control signals output by the delay beat module are directly used, and the clock gating generation unit 2 beats the input control signal by 1 beat under the clock domain of clk_in_2x, and then outputs the control signal as the clock gating signal.

The clock gating unit outputs clk_out when the clock gating signal is high level, and turns off clk_out when the clock gating signal is low level, and the 2 clock gating units are standard units and have the same functions.

Thus, when hw_rst_b and top_sw_rst_b are released, the delay beating modules 1 and 2 ensure that the clock gating signal is turned off after M clock cycles, meanwhile, the output clock clk_out_1x is turned off, and after waiting for one clock cycle of clk_in_2x, clk_out_2x is turned off, then N clock cycles are waited, top_sw_rst_sync_b and local_sw_rst_sync_b complete release, a released high level reset signal in a stable state is output, finally, P clock cycles are waited, clk_out_1x is turned on again, and clk_out_2x is turned on again after waiting for one clock cycle of clk_in_2x. Where the value of M depends on the number of stages of the longest register chain without reset segments in the design driven by the output reset signal. The value of N represents the removal time (clear time) between the output reset signal and the output clk_out for setting the multi-cycle hold constraint between the two. Typically the rst_sync_n delay is large, the clk_out delay is small, the hold constraint is small, and this value can be small. The value of P represents the recovery time between the output reset signal and clk_out for setting the multi-cycle setup constraint between the two, depending on the number and distribution range of the reset signal driving logic, etc.

In order to further explain the present embodiment, a simulation waveform diagram of various reset signal release conditions in the application scenario shown in fig. 5 is listed herein, and signal waveforms at various key points in the embodiment are shown in fig. 6 to 11, and signal names correspond to the signal names shown in fig. 5.

Fig. 6 shows a situation where the 3 input reset signals are released successively, and it can be seen that when all of the 3 input reset signals are asserted, all of the 2 output reset signals are in a reset state. According to the logic relationship between the reset signals described above, if only hw_rst_b is released, 2 output reset signals are still in the reset state, and the output clock signal is normally output. And M clk_in_1x clock cycles after top_sw_rst_b is also released, clk_out_1x is turned off, N clk_in_1x clock cycles are waited, top_sw_rst_sync_b is released, P clk_in_1x clock cycles are waited, and clk_out_1x is turned on again. clk_out_2x turns off after clk_out_1x turns off and waits for 1 clk_out_2x clock cycle, and turns back on after clk_out_1x turns back on and waits for 1 clk_out_2x clock cycle. It is noted that when hw_rst_b and top_sw_rst_b are released, local_sw_rst_b is still in the reset state, local_sw_rst_sync_b is still in the reset state, after local_sw_rst_b is released, clk_out_1x and clk_out_2x re-perform the above-described actions, and local_sw_rst_sync_b is released after m+n clk_in_1x clock cycles after local_sw_rst_b is released.

Fig. 7, 8 and 9 show simulated waveforms of hw_rst_b, top_sw_rst_b and local_sw_rst_b when released individually. It can be seen that when hw_rst_b and top_sw_rst_b are in effect independently, top_sw_rst_sync_b and local_sw_rst_sync_b are in reset state, and after the input reset signal is released, waiting for m+n clk_in_1x clock cycles, top_sw_rst_sync_b and local_sw_rst_sync_b are released. When only the local_sw_rst_b is in the reset state, and both the hw_rst_b and the top_sw_rst_b are in the invalid state, only the local_sw_rst_sync_b signal is in the reset state, and the top_sw_rst_sync_b is not reset, which means that the local_sw_rst_b is not controlled to the top_sw_rst_sync_b, and the priority relation of the input reset signal is consistent. After the local_sw_rst_b is released, waiting for m+n clk_in_1x clock cycles, the local_sw_rst_sync_b completes the release. Here the behavior of clk_in_1x and clk_in_2x is identical to that described above.

Fig. 10 depicts a scenario when hw_rst_b, top_sw_rst_b, and local_sw_rst_b are released simultaneously. It can be seen that when the 3 input reset signals are all asserted, top_sw_rst_sync_b and local_sw_rst_sync_b are both in the reset state, after the 3 input reset signals are released simultaneously, m+n clk_in_1x clock cycles are waited, and the 2 output reset signals are all released. Here the behavior of clk_in_1x and clk_in_2x is identical to that described above.

Fig. 11 depicts the case where hw_rst_b, top_sw_rst_b, and local_sw_rst_b are released in succession only when clk_in_1x is input, and it can be seen from comparison with fig. 6 that the actions of top_sw_rst_sync_b, local_sw_rst_sync_b, and clk_out_1x are completely identical to those of fig. 6 except that clk_out_2x has no output clock.

According to the reset signal processing method, clock turn-off and delay beating operations are added, and the reset signal is not required to be released within one clock period in the circuit function, so that the constraint on the reset signal can be relaxed in the circuit implementation stage, particularly in the scene of large and complex design scale, the time sequence convergence difficulty can be remarkably reduced, and the circuit implementation and related labor investment and time cost are reduced.

According to the reset signal processing method, by turning off the output clock signal, the circuits driven by the clock signal and the reset signal can be prevented from being in a working state before the released reset signal is not stably transmitted to all the driven registers, and abnormal circuit states are avoided. Through the double insurance, the potential metastable state propagation risk caused by the asynchronous relation of the reset signal and the clock signal in the synchronous release process of the reset signal is effectively avoided.

The reset signal processing method provided by the embodiment of the application can output high-quality reset signals and improve the stability and reliability of the system. The system may respond quickly to asynchronous resets when the reset signal is asserted. When the reset signal is released, on one hand, the reset signal after synchronous release is delayed and shot to ensure that the finally released reset signal is in a stable state, and on the other hand, the output clock signal is turned off, so that the clock and a circuit driven by reset can not be in a working state before the released reset signal is not stably transmitted to all the driven registers, and abnormal circuit state is avoided.

The reset signal processing method provided by the embodiment of the application is simple in design, good in usability and universality, and suitable for the design of clock reset systems of most SOC chips.

Optionally, as shown in fig. 12, the embodiment of the present application further provides an electronic device 1200, including a processor 1201 and a memory 1202, where the memory 1202 stores a program or an instruction that can be executed on the processor 1201, and the program or the instruction implement each step of the signal processing method described above when executed by the processor 601, and achieve the same technical effect, so that repetition is avoided, and no further description is given here.

It should be noted that, the electronic device in the embodiment of the present application includes a mobile electronic device and a non-mobile electronic device.

The embodiment of the application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled with the processor, and the processor is used for running a program or an instruction, so as to implement each process of the signal processing method embodiment, and achieve the same technical effect, so that repetition is avoided, and no redundant description is provided here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the embodiment of the signal processing method, and the same technical effects can be achieved, so that repetition is avoided, and no further description is given here.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.

The embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the embodiments of the signal processing method described above, and achieve the same technical effects, and are not repeated herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solutions of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), comprising several instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the methods described in the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims

1. A signal processing method, comprising:

2. The method according to claim 1, wherein the method further comprises:

after the first output target signal is controlled to be synchronously released under the clock domain of the input clock signal, the output clock signal under the clock domain is controlled to be delayed to be turned off after a second number of preset clock cycles and to be turned on again after a third number of preset clock cycles, wherein the first number is larger than the second number and smaller than the sum of the second number and the third number.

3. The method according to claim 2, wherein said controlling the output clock signal under the clock domain to be turned off after a preset second number of clock cycles and to be turned back on after a preset third number of clock cycles, in particular comprises:

Generating a control signal in the clock domain under the condition that the first output target signal after synchronous release is detected; the control signal is used for indicating the output clock signal to be delayed to be turned off after a second number of clock cycles and turned on again after a third number of clock cycles;

4. A method according to claim 2 or 3, characterized in that the first number is the sum of a preset first value M and a second value N, the second number is the first value M, and the third number is the sum of the second value N and a preset third value P;

the first value M is set as the series of the longest register chain without the target signal input end in the register driven by the first output target signal; the second value N is set as a clearing time removal time between the first output target signal and the output clock signal; the third value P is set as a recovery time between the first output target signal and the output clock signal.

5. A method according to any one of claims 1 to 3, further comprising:

determining a second output target signal influenced by the currently effective input target signal according to the logic relation under the condition that the input target signal in an invalid state is detected to be effective;

and controlling the second output target signal to take effect asynchronously and output immediately.

6. A method according to any one of claims 1 to 3, wherein each of the input target signals controls at least one signal domain;

the receiving at least one input target signal, determining an output target signal having a logical relationship with the at least one input target signal, comprises:

determining an output target signal corresponding to each signal domain in all signal domains according to all signal domains controlled by the at least one input target signal, and establishing the logic relationship based on the at least one input target signal and the signal domains controlled by the at least one output target signal; wherein each of the output target signals controls a signal domain.

7. The method of claim 6, wherein the at least one input target signal has a priority relationship therebetween;

Establishing the logic relationship based on the signal domain controlled by the at least one input target signal and the at least one output target signal specifically comprises:

determining all of said input target signals affecting each of said output target signals according to at least one signal domain controlled by each of said input target signals and a signal domain controlled by each of said output target signals, and determining said logical relationship in combination with a priority relationship between said at least one input target signal; wherein the logic relationship is used for representing a logic operation relationship based on priority among all the input target signals affecting each output target signal.

8. The utility model provides a signal processing device which characterized in that includes signal processing module, data synchronizer module and delay beat the module, wherein:

9. The apparatus of claim 8, further comprising a clock gating generation unit and a clock gating unit, wherein:

the delay beating module is further configured to generate a control signal in the clock domain and send the control signal to the clock gating generation unit when the first output target signal after the synchronization release is received, where the control signal is used to instruct the output clock signal to be delayed to be turned off after a preset second number of clock cycles and to be turned on again after a preset third number of clock cycles, and the first number is greater than the second number and less than a sum of the second number and the third number;

the clock gating generation unit is used for generating a clock gating signal in the clock domain according to the received control signal and sending the clock gating signal to the clock gating unit;

The clock gating unit is used for controlling the turn-off and turn-on of the output clock signal under the clock domain according to the received clock gating signal.

10. The device according to claim 8 or 9, wherein,

the signal processing module is further configured to determine, according to the logic relationship, a second output target signal affected by the currently valid input target signal and instruct the data synchronizer module when the input target signal in an invalid state is detected to be valid;

the data synchronizer module is further used for controlling the second output target signal to take effect asynchronously and providing the second output target signal after the second output target signal takes effect asynchronously to the delay beating module;

the delay beating module is further used for controlling the second output target signal to be output immediately after the asynchronization is effective.

11. The apparatus according to claim 8 or 9, wherein the same number of data synchronizer modules and delay beat modules as the number of signal domains are provided, each signal domain corresponding to a set of data synchronizer modules and delay beat modules;

the signal processing module is specifically configured to determine an output target signal corresponding to each signal domain in all signal domains according to all signal domains controlled by the at least one input target signal, and establish the logic relationship based on the at least one input target signal and the signal domain controlled by the at least one output target signal; under the condition that the first output target signal is determined, indicating a data synchronizer module corresponding to a signal domain controlled by the first output target signal; wherein each of said input target signals controls at least one signal domain, and each of said output target signals controls one signal domain;

The data synchronizer module is specifically configured to provide the first output target signal after the synchronization release to a corresponding delay beating module.

12. A chip comprising a processor and a communication interface, the communication interface and the processor being coupled, the processor being configured to execute programs or instructions to implement the method of any one of claims 1 to 7.

13. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor for implementing the method of any one of claims 1 to 7.