CN115882863A - System and method for fast switching of multiple clock domains - Google Patents
System and method for fast switching of multiple clock domains Download PDFInfo
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Abstract
A system for fast switching of multiple clock domains, comprising: the trigger generation module is configured to generate and output trigger signals and trigger indication signals of different configurations based on the external trigger request and the internal timing trigger request; a mask module configured to generate and output a clock domain selection signal and a mask signal based on the trigger indication signal and the configuration parameter; an analog module configured to generate and output an analog result based on the plurality of level signals and the trigger signal; a preprocessing module configured to generate and output a preprocessing result based on the simulation result; and the filtering module comprises a plurality of filters positioned in different clock domains and is configured to generate a filter reset signal based on the clock domain signal, the clock domain selection signal and the mask signal, control the filters to sample and filter the preprocessing result, and output a valid result by the filters positioned in the triggered clock domain signal. The application also provides a method for rapidly switching the multiple clock domains, which realizes the rapid switching of the trigger belonging to different clock domains.
Description
Technical Field
The present application relates to the field of chip design, and in particular, to a system and method for fast switching between multiple clock domains.
Background
In the digital-analog interaction module, acquisition clocks of analog signals need to be frequently switched, as shown in fig. 1, in the existing scheme, a trigger generation module performs different configurations on the analog module and triggers the analog module to work, the analog module returns a corresponding result after being triggered, the result is synchronously processed and synchronized to a clock domain of a controller, a sampling result is processed under the clock domain of the controller, and finally the processed result is synchronized to different trigger clock domains and returned. Analog signals are sampled and processed in a digital-analog interactive module, and the synchronous processing of a clock domain is required to be frequently performed. Thus, in the case of frequent trigger switching, the delay can be large, which can result in the trigger having switched, but the resulting signal is still the residual result of the previous trigger.
Disclosure of Invention
In order to solve at least one problem existing in the prior art, an object of the present application is to provide a system and a method for fast switching of multiple clock domains, which can fast switch and transmit triggers belonging to different clock domains, do not leave a residual result of a previous trigger, reduce the number of synchronizers used, and have low delay.
To achieve the above object, the present application provides a system for fast switching between multiple clock domains, comprising:
a trigger generation module configured to generate and output trigger signals of different configurations and trigger indication signals based on an external trigger request and an internal timing trigger request, wherein the trigger indication signals are used for controlling switching among a plurality of clock domains;
a mask module configured to generate and output a clock domain selection signal and a mask signal based on the trigger indication signal and a configuration parameter;
an analog module configured to generate and output an analog result based on a plurality of level signals and the trigger signal;
a preprocessing module configured to generate and output a preprocessing result based on the simulation result;
a filtering module including a plurality of filters located in different clock domains and configured to generate a filter reset signal based on a clock domain signal, the clock domain selection signal and the mask signal, control the filters to sample and filter the preprocessing result, wherein the filter located in the triggered clock domain signal outputs a valid result, and the filter located in the clock domain signal that is not triggered cannot output a valid result.
Further, the output end of the trigger generation module is connected with the input end of the analog module, the output end of the analog module is connected with the input end of the preprocessing module, the output end of the preprocessing module is connected with the first input end of the filtering module, the input end of the mask module is connected with the output end of the trigger generation module, and the output end of the mask module is connected with the second input end of the filtering module.
Further, the trigger generation module includes: a first selector and a first counter; the first input end of the first selector inputs the external trigger request, the second input end of the first selector is connected with the output end of the first counter, the output end of the first counter outputs the internal timing trigger request, and the output end of the first selector outputs the trigger signal and the trigger indication signal;
the first counter is used for generating an internal timing trigger request.
Further, the mask module includes a second counter, an input end of the second counter inputs the trigger indication signal, a clear end of the second counter inputs a configuration parameter, and an output end of the second counter outputs the mask signal and the clock domain selection signal.
Further, the trigger signal includes: a channel selection signal and a sampling time;
the analog module comprises one of an analog voltage comparator and an analog-to-digital converter;
the analog voltage comparator is used for comparing voltages based on a plurality of level signals and a channel selection signal to obtain a comparison result of the voltages, and outputting the comparison result as the analog result;
and the analog-to-digital converter is used for performing analog-to-digital conversion based on the plurality of level signals, the channel selection signal and the sampling time to obtain an analog-to-digital conversion result of the output voltage, and outputting the analog result.
Further, the preprocessing module comprises: the polarity inversion module, the second selector, the direct current offset compensation module and the third selector; the first input end of the second selector inputs the simulation result, one end of the polarity inverting module inputs the simulation result, the other end of the polarity inverting module is connected with the second input end of the second selector, the output end of the second selector is connected with the first input end of the third selector, one end of the direct current offset compensation module is connected with the output end of the second selector, the other end of the direct current offset compensation module is connected with the second input end of the third selector, and the output end of the third selector outputs the preprocessing result.
Further, the system further comprises: the filtering module also comprises a plurality of groups of two cascaded registers and a multi-input OR gate, wherein the two cascaded registers are asynchronously reset and synchronously released;
in each group, the clock ends of the two cascaded registers respectively input the clock domain signal, first reset signals obtained by performing logic and operation on the clock domain selection signal and the inverted mask signal are respectively used as asynchronous reset signals of the two cascaded registers to be input into the reset ends of the two cascaded registers, filter reset signals output by a second register of the two cascaded registers are used as reset signals of the filter to be input into the reset end of the filter, the clock end of the filter inputs the clock domain signal, the input end of the filter inputs the preprocessing result, and the output end of the filter is connected to the input end of the multiple input or gate;
the multiple input ends of the multiple input OR gate are connected with the output end of the filter in each group, the filter positioned in the triggered clock domain signal outputs a valid result, and the filter positioned in the clock domain signal which is not triggered can not output a valid result.
Further, the moment when the trigger indication signal is generated is taken as the first moment,
at a first moment, the triggered clock domain sends the trigger indication signal, and the trigger indication signal is positioned at the reset of a filter of the clock domain signal which is not triggered;
and at the second moment, the triggered clock domain samples the preprocessing result and filters the preprocessing result, and the filter positioned on the triggered clock domain signal outputs a valid result.
In order to achieve the above object, the present application further provides a method for fast switching between multiple clock domains, including:
generating and outputting trigger signals and trigger indication signals of different configurations based on the external trigger request and the internal timing trigger request, wherein the trigger indication signals are used for controlling switching among a plurality of clock domains;
generating and outputting a clock domain selection signal and a mask signal based on the trigger indication signal and the configuration parameters;
generating and outputting a simulation result based on a plurality of level signals and the trigger signal;
generating a preprocessing result based on the simulation result and outputting the preprocessing result;
and generating a filter reset signal based on the clock domain signal, the clock domain selection signal and the mask signal, controlling the filter to sample and filter the preprocessing result, wherein the filter positioned in the triggered clock domain signal outputs a valid result, and the filter positioned in the clock domain signal which is not triggered can not output a valid result.
In order to achieve the above object, the present application further provides a chip on which the system for fast switching of multiple clock domains as described above is integrated.
In order to achieve the above object, the present application also provides a circuit board including the chip as described above.
In order to achieve the above object, the present application further provides a vehicle device, including the chip as described above.
To achieve the above object, the present application further provides an electronic device, which includes a memory and a processor, wherein the memory stores computer instructions, and the processor is configured to execute the instructions to perform the steps of the method for fast switching between multiple clock domains as described above.
To achieve the above object, the present application further provides a computer readable storage medium, on which computer instructions are stored, and when the computer instructions are executed, the steps of the method for fast switching between multiple clock domains as described above are executed.
According to the system and the method for multi-clock domain fast switching, the filtering module and the mask module are added, so that the trigger belonging to different clock domains can be fast switched and transmitted, the residual result of the previous trigger cannot be left, the using number of synchronizers is reduced, the response is fast, and the time delay is low.
Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the present application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a block diagram of a system architecture for clock domain switching in the prior art;
FIG. 2 is a block diagram of a system architecture for fast multi-clock domain switching according to an embodiment of the present application;
FIG. 3 is a block diagram of a trigger generation module according to an embodiment of the present application;
FIG. 4 is a block diagram of a masking module according to one embodiment of the present application;
FIG. 5 is a block diagram of a preprocessing module according to one embodiment of the present application;
FIG. 6 is a block diagram of a filtering module according to an embodiment of the present application;
FIG. 7 is a block diagram of a filtering module according to another embodiment of the present application;
FIG. 8 is a timing diagram according to the embodiment of FIG. 7 of the present application;
FIG. 9 is a block diagram of a filtering module according to another embodiment of the present application;
FIG. 10 is a timing diagram according to the embodiment of FIG. 9 of the present application;
FIG. 11 is a flowchart of a method for fast switching of multiple clock domains according to one embodiment of the present application;
FIG. 12 is a diagram illustrating a chip structure according to an embodiment of the present disclosure;
FIG. 13 is a schematic diagram of a circuit board structure according to an embodiment of the present application;
fig. 14 is a schematic structural diagram of a vehicle machine according to an embodiment of the application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the references to "first", "second", etc. in this application are only used for distinguishing different devices, modules, units or data, and are not used for limiting the order or interdependence of the functions performed by these devices, modules, units or data.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise. "plurality" is to be understood as two or more.
ACMP: analog comparator simulates a comparator.
ADC: analog-to-digital converter, analog-to-digital converter.
DC offset: direct Current offset, dc offset voltage.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
Fig. 2 is a block diagram of a system structure for fast switching between multiple clock domains according to an embodiment of the present application, and as shown in fig. 2, the system for fast switching between multiple clock domains of the present embodiment includes: a trigger generation module 11, a mask module 12, a simulation module 13, a preprocessing module 14, and a filtering module 15. The clock domain is associated with a clock signal. Wherein the content of the first and second substances,
a trigger generation module 11 configured to generate trigger signals of different configurations and trigger indication signals and clock domain selection signals based on the external trigger request and the internal timing trigger request and send the trigger signals to the analog module 13, and send the trigger indication signals to the mask module 12, wherein the trigger indication signals are used for controlling switching among a plurality of clock domains;
a mask module 12 configured to generate a clock domain selection signal and a mask signal based on the trigger indication signal and a configuration parameter and transmit the clock domain selection signal and the mask signal to the filtering module;
an analog module 13 configured to generate an analog result based on the plurality of level signals and the trigger signal and send the analog result to the preprocessing module 14;
a preprocessing module 14 configured to generate and output a preprocessing result based on the simulation result;
a filtering module 15, including a plurality of filters located in different clock domains, configured to generate a filter reset signal based on the clock domain signal, the clock domain selection signal and the mask signal, the filter reset signal controlling the filters to sample and filter the preprocessing result, the filters located in the triggered clock domain signal outputting a valid result, the filters located in the non-triggered clock domain signal failing to output a valid result, and the result being masked.
Specifically, the output end of the trigger generation module 11 is connected to the input end of the analog module 13, the output end of the analog module 13 is connected to the first input end of the preprocessing module 14, the output end of the preprocessing module 14 is connected to the first input end of the filtering module 15, the input end of the mask module 12 is connected to the output end of the trigger generation module 11, and the output end of the mask module 12 is connected to the second input end of the filtering module 15.
Further, as shown in fig. 3, in an embodiment of the present application, the trigger generating module 11 includes: a first selector and a first counter; a first input end of the first selector inputs an external trigger request, a second input end of the first selector is connected with an output end of the first counter, an output end of the first counter outputs the internal timing trigger request, and an output end of the first selector outputs the trigger signal and the trigger indication signal;
the first counter is used for generating an internal timing trigger request, for example, an internal timer can be set, and a trigger indication signal is generated at regular time; or the trigger condition and the trigger configuration are preset, and the counter is timed to cycle when the time is up.
In the embodiment of the application, an external trigger request or an internal trigger request can be selected.
Specifically, the trigger signal includes: a channel selection signal and a sampling time;
further, as shown in fig. 4, in an embodiment of the present application, the mask module 12 includes a second counter, an input end of the second counter inputs the trigger indication signal, a clear end of the second counter inputs a configuration parameter, and an output end of the second counter outputs the clock domain selection signal and the mask signal.
The mask signal is used for shielding invalid simulation results and extracting simulation results of a desired time period.
Specifically, the trigger indication signal controls the clock domain selection signal, for example, when one trigger indication signal is generated, the clock domain selection signal is inverted from a low level to a high level, and then the next trigger indication signal is generated, the clock domain selection signal is inverted from a high level to a low level, or when the first trigger indication signal is generated, the clock domain selection signal is changed from 00 to 01, when the second trigger indication signal is generated, the clock domain selection signal is changed from 01 to 11, and then the third trigger indication signal is generated, the clock domain selection signal is changed from 11 to 10.
Further, in the embodiment of the present application, the analog module 13 has multiple implementation manners, for example, an analog voltage comparator or an analog-to-digital converter can be used for implementation;
if the analog voltage comparator ACMP is adopted, specifically, voltage comparison is carried out based on a plurality of level signals and channel selection signals to obtain a comparison result of voltage, and the comparison result is output as the analog result; for example: the analog end inputs 16 levels, the digital end inputs a channel selection signal, 2 channels are selected from the 16 channels, and finally the comparison result of the voltage is output, if the voltage of the 1 st channel is larger than that of the 2 nd channel, a high level is output as the analog result, and if the voltage of the 2 nd channel is larger than that of the 1 st channel, a low level is output as the analog result.
If the analog-to-digital converter ADC is adopted, specifically, analog-to-digital conversion is performed based on a plurality of level signals, channel selection signals and sampling time to obtain an analog-to-digital conversion result of the output voltage, which is output as the analog result, for example, 16 levels are input at the analog end, the channel selection signals are input at the digital end, 1 path is selected from 16 paths, and finally, the analog-to-digital conversion result of the voltage is output.
In the embodiment of the present application, the external trigger request and the internal timing trigger request may be configured in advance, for example: the number of the analog voltage comparators is 16, and the analog voltage comparators are divided into 3 external triggers and 1 internal trigger, wherein the first external trigger is selected from 5 to 8, the second external trigger is selected from 9 to 12, the third external trigger is selected from 13 to 16, and the internal trigger is selected from 1 to 4.
Further, as shown in fig. 5, in an embodiment of the present application, the preprocessing module 14 includes: the polarity inversion module, the second selector, the direct current offset compensation module and the third selector; the first input end of the second selector inputs the simulation result, one end of the polarity inverting module inputs the simulation result, the other end of the polarity inverting module is connected with the second input end of the second selector, the output end of the second selector is connected with the first input end of the third selector, one end of the direct current offset compensation module is connected with the output end of the second selector, the other end of the direct current offset compensation module is connected with the second input end of the third selector, and the output end of the third selector outputs the preprocessing result.
And the polarity inverting module is used for inverting all the obtained simulation results.
And the direct current offset compensation module is used for compensating the DC offset and adding or subtracting a compensation value from the obtained simulation result.
The polarity inverting module of the preprocessing module 14 is for ACMP, the dc offset compensation module is for ADC, and it is equivalent to adapt to multiple analog devices by using the same circuit, and the preprocessing module 14 selects one of the sub-modules according to the analog module 13, specifically: when the analog module 13 employs ACMP, the second selector of the preprocessing module 14 selects the polarity inverting module to invert all the analog results to obtain the preprocessing result, and when the analog module 13 employs ADC, the third selector of the preprocessing module 14 selects the dc offset compensation module to add or subtract the compensation value to the analog result to obtain the preprocessing result.
Further, as shown in fig. 6, in the embodiment of the present application, the filtering module 15 includes not only a plurality of filters 151 (N filters: filter0, filter1.. Filtnn), but also a plurality of sets of two cascaded registers 152 (N sets) and a multi-input or gate 153, where the two cascaded registers are asynchronously reset and synchronously released.
In each group, the clock terminals of the two cascaded registers 152 respectively input the clock domain signal (clk 0, clk1.. Klkn.), the clock domain selection signal (clk _ domain _ switch0, clk _ domain _ switch1.. Klkn.. Clk _ domain _ switch) and the inverted mask signal are logically and-operated to obtain a first reset signal, the first reset signal is respectively input to the reset terminals of the two cascaded registers 152 as asynchronous reset signals of the two cascaded registers 152, the filter reset signal (filter 0_ rst _ b, filter1_ rst _ b.. Rskn. Filter _ b) output by the second register of the two cascaded registers 152 is input to the reset terminals of the filter 151 as the reset signal of the filter 151, each of the plurality of filters 151 has the clock terminal input the clock domain signal (0, clk1.. Klkn.) and the input terminal of the plurality of filters 151 is connected to the input terminal or the output terminal of the multi-stage gate 153;
a plurality of inputs of the multiple-input or gate 153 are connected to an output of each of the plurality of filters 151, and an output of the multiple-input or gate 153 outputs a valid result: the filter at the clock domain signal that is triggered outputs a valid result (O _ fnl _ result), and the filter at the clock domain signal that is not triggered cannot output a valid result.
At the same time, only one filter is in a non-reset state, and the effective result of the filter is output; except for the active filter, the remaining filters are in a reset state, masked, and output a "0".
In the embodiment of the application, the moment of generating the trigger indication signal is taken as the first moment,
at a first moment, the triggered clock domain sends the trigger indication signal, and the trigger indication signal is positioned at the reset of a filter of the clock domain signal which is not triggered;
and at the second moment, the triggered clock domain samples the preprocessing result and filters the preprocessing result, and the filter positioned on the triggered clock domain signal outputs a valid result.
The following is an example of a two clock domain switch embodiment.
FIG. 7 is a block diagram of a preprocessing module according to another embodiment of the present application. As shown in fig. 7, the filtering module includes a multi-input or gate, a first set of two cascaded registers, a second set of two cascaded registers, a first filter and a second filter, wherein a clock terminal of the first filtering module inputs a first clock domain signal, and a clock terminal of the second filtering module inputs a second clock domain signal;
the clock ends of the two cascaded registers of the first group are respectively input with the first clock domain signal, a first clock domain selection signal and a first reset signal obtained after the inverted mask signal is logically AND-ed are respectively input from the asynchronous reset ends of the two cascaded registers, the output end of the second register of the two cascaded registers is connected with the first input end of the first filter, the second input end of the first filter is input with the preprocessing result, and the output end of the first filter is connected with the first input end of the multiple-input OR gate;
the clock ends of the two cascaded registers of the second group are respectively input with the second clock domain signal, a second clock domain selection signal and a second reset signal obtained after logical AND of the inverted mask signal are respectively input from asynchronous reset ends of the two cascaded registers, output ends of the two cascaded registers are connected with a first input end of a second filter, a second input end of the second filter is input with the preprocessing result, and an output end of the second filter is connected to a second input end of the multiple-input OR gate;
the filter at the clock domain signal that is triggered outputs a valid result, and the filter at the clock domain signal that is not triggered cannot output a valid result.
Specifically, when a trigger request is received, a trigger generation module generates a trigger signal and sends the trigger signal to an analog module, and simultaneously sends a trigger indication signal (trigger) to a mask module, the mask module generates a mask signal (ana _ data _ vld) and a clock domain selection signal (clk _ domain _ switch) according to the trigger indication signal (trigger) and sends the mask signal and the clock domain selection signal (clk _ domain _ switch) to a filter module, the trigger indication signal (trigger) can control the conversion of the clock domain selection signal (clk _ domain _ switch), the clock domain selection signal (clk _ domain _ switch) and the inverted mask signal (ana _ data _ vld) perform logic and ' on ' and ' to obtain a signal, and the signal is used as a reset signal of two cascaded registers, and filter reset signals (flip 1_ rst _ b) and (flip 2_ rst _ b) output by output ends of two groups of two registers are used as reset end inputs of a register in a filter; after receiving the trigger signal, the simulation module returns a simulation result and sends the simulation result to the preprocessing module, the preprocessing module obtains a preprocessing result (ana _ sig) through combinational logic processing, the preprocessing result is sent to the filtering module, the filtering module performs sampling and filtering processing on the preprocessing result, and finally an effective result O _ fnl _ result is output.
As shown in fig. 7, the two registers in each group are asynchronously reset and synchronously released, the clock domain selection signal clk _ domain _ switch and the inverted ana _ data _ vld perform logic and, then, the generated reset signal is used as the asynchronous reset input of the two cascade registers, and the filter reset signals filter0_ rst _ b and filter1_ rst _ b generated by the two cascade registers in the two groups are respectively sent to the filter0 and filter1. Thus, as a result of clk0 clock domain, filter1 will be in reset state, and only filter0 will be in working state; similarly, as a result of clk1 clock domain, filter0 will be in reset state, and only filter1 will be in working state; and finally, performing logical OR processing on the results of the two filters through a multi-input OR gate, and outputting a final effective result O _ fnl _ result. With this structure, O _ fnl _ result can be output only by the filter located in the triggered clock domain, and the filter located in the non-triggered clock domain cannot output the result, and the result is masked.
Fig. 8 is a waveform diagram illustrating two clock domain switching. As shown in fig. 8, at time T1, a trigger request is received, clk0 clock domain sends trigger1, clk _ domain _ switch0 goes low, at this time, the reset of filter1 is set immediately, that is, filter1_ rst _ b goes low, and the output result of filter1 is cut off; at time T2, the clk0 clock domain may sample the analog result output by the analog module and output stably as an effective result of the clk0 clock domain; at the time of T3, a triggering request is received, a new trigger2 is sent by the clk1 clock domain, the clk _ domain _ switch1 becomes high level, at the moment, the reset of the filter0 is immediately started, namely the filter0_ rst _ b becomes low level, and the output result of the filter0 is intercepted; at time T4, the clk1 clock domain may sample the analog result output by the analog module and output stably as an effective result of the clk1 clock domain; at the time of T5, a new trigger3 is sent by the clk0 clock domain, clk _ domain _ switch0 becomes low level, at this time, the reset of filter1 is set up immediately, that is, filter1_ rst _ b becomes low level, and the output result of filter1 is cut off; at time T6, clock clk0 may be sampled to the pre-processed result and stable as a valid result O _ fnl _ result of clk0 clock domain.
A specific embodiment of three clock domain switching is illustrated below.
FIG. 9 is a block diagram of a preprocessing module according to another embodiment of the present application. As shown in fig. 9, the filtering module includes a multi-input or gate, a first set of two cascaded registers, a second set of two cascaded registers, a third set of two cascaded registers, a first filter, a second filter, and a second filter, wherein a clock terminal of the first filtering module inputs a first clock domain signal, a clock terminal of the second filtering module inputs a second clock domain signal, and a clock terminal of the third filtering module inputs a third clock domain signal;
the clock ends of the two cascaded registers of the first group are respectively input with the first clock domain signal, a first clock domain selection signal and a first reset signal obtained after the inverted mask signal is subjected to logical AND are respectively input from asynchronous reset ends of the two cascaded registers, the output ends of the two cascaded registers are connected with a first input end of a first filter, a second input end of the first filter is input with the preprocessing result, and the output end of the first filter is connected with a first input end of the multiple-input OR gate;
the clock ends of the two cascaded registers of the second group are respectively input with the second clock domain signal, a second clock domain selection signal and a second reset signal obtained after the inverted mask signal is subjected to logical AND are respectively input from asynchronous reset ends of the two cascaded registers, the output ends of the two cascaded registers are connected with a first input end of a second filter, a second input end of the second filter is input with the preprocessing result, and the output end of the second filter is connected to a second input end of the multiple-input OR gate;
the clock ends of the two cascaded registers of the third group respectively input the third clock domain signal, a third clock domain selection signal and a third reset signal obtained after the inverted mask signal is logically AND-ed are respectively input from asynchronous reset ends of the two cascaded registers, the output end of a second register of the two cascaded registers is connected with the first input end of a third filter, the second input end of the third filter inputs the preprocessing result, and the output end of the third filter is connected to the third input end of the multiple-input OR gate;
the filter at the clock domain signal that is triggered outputs a valid result, and the filter at the clock domain signal that is not triggered cannot output a valid result.
Specifically, when a trigger request is received, a trigger generation module generates a trigger signal and sends the trigger signal to an analog module, and at the same time, sends a trigger indication signal (trigger) to a mask module, the mask module generates a mask signal (ana _ data _ vld) and a clock domain selection signal (clk _ domain _ switch) according to the trigger indication signal (trigger), and sends the mask signal and the clock domain selection signal (clk _ domain _ switch) to a filter module, the trigger indication signal (trigger) can control the conversion of the clock domain selection signal (clk _ domain _ switch), the clock domain selection signal (clk _ domain _ switch) and the mask signal (ana _ data _ vld) after inversion are logically anded to serve as reset signals of two cascaded registers, and the filter signals (flip 0_ rst _ b), (flip 1_ rst _ b) and (flip 2_ b) output by the output ends of the three sets of two cascaded registers serve as reset end inputs of an rst register in a filter; after receiving the trigger signal, the simulation module returns a simulation result and sends the simulation result to the preprocessing module, the preprocessing module obtains a preprocessing result (ana _ sig) through combinational logic processing, the preprocessing result is sent to the filtering module, the filtering module performs sampling and filtering processing on the preprocessing result, and finally an effective result O _ fnl _ result is output.
As shown in fig. 9, the two registers in each group are asynchronously reset and synchronously released, the clock domain selection signal clk _ domain _ switch and the inverted mask signal ana _ data _ vld are logically anded to generate a reset signal, which is used as the asynchronous reset input of the two cascade registers, and the filter reset signals filter0_ rst _ b, filter1_ rst _ b and filter2_ rst _ b generated by the two cascade registers in the two groups are respectively sent to the filters filter0, filter1 and filter2. Thus, as a result of clk0 clock domain, filter1 and filter2 are in reset state, and only filter0 is in working state; similarly, as a result of clk1 clock domain, filter0 and filter2 will be in reset state, and only filter1 will be in working state; as a result of clk2 clock domain, filter0 and filter1 are in reset state, and only filter2 is in working state; and finally, performing logical OR processing on the results of the three filters through a multi-input OR gate, and outputting a final effective result. With this structure, only the filter in the triggered clock domain can output the valid result O _ fnl _ result, and the filter in the non-triggered clock domain cannot output the result, and the result is masked.
Fig. 10 is a waveform diagram illustrating switching of three clock domains. As shown in fig. 10, at time T1, when a trigger request is received, clk0 clock domain sends trigger1, clk _ domain _ switch0 becomes 2' b00, and at this time, the reset of filter1 and filter2 is immediately started, that is, filter1_ rst _ b and filter2_ rst _ b become low, and the output results of filter1 and filter2 are cut off; at time T2, the clk0 clock domain may sample the analog result output by the analog module and output stably as an effective result of the clk0 clock domain; at time T3, a trigger request is received, a new trigger2 is sent by the clk1 clock domain, clk _ domain _ switch1 becomes 2' b01, at this time, the reset of the filter0 and the filter2 is immediately started, that is, the filter0_ rst _ b and the filter2_ rst _ b become low level, and the output results of the filter0 and the filter2 are stopped; at the time of T4, the clk1 clock domain can sample the simulation result output by the simulation module and stably output as the effective result of the clk1 clock domain; at time T5, a new trigger3 is sent by the clk2 clock domain, clk _ domain _ switch2 becomes 2' b10, at this time, the reset of filter0 and filter1 is immediately started, that is, filter0_ rst _ b and filter1_ rst _ b become low, and the output results of filter0 and filter1 are stopped; at time T6, clock clk2 may sample the pre-processed result and output O _ fnl _ result as a valid result of clk2 clock domain, stable.
According to the system for rapidly switching the multiple clock domains, the filtering module and the mask module are added, so that the triggers belonging to different clock domains can be rapidly switched and transmitted, the residual result of the previous trigger cannot be left, the using number of synchronizers is reduced, the response is rapid, and the time delay is low.
Example 2
Fig. 11 is a flowchart of a method for fast switching between multiple clock domains according to an embodiment of the present application, and the method for fast switching between multiple clock domains is described in detail below with reference to fig. 11.
In step 301, generating and outputting trigger signals with different configurations and trigger indication signals based on an external trigger request and an internal timing trigger request, wherein the trigger indication signals are used for controlling switching among a plurality of clock domains;
in particular, the trigger indication signal controls the switching of the clock domain selection signal.
Specifically, the triggering request includes: an external trigger request and an internal timing trigger request.
In step 302, a clock domain selection signal and a mask signal are generated and output based on the trigger indication signal and the configuration parameters.
In step 303, generating and outputting a simulation result based on a plurality of level signals and the trigger signal;
in step 304, generating and outputting a preprocessing result based on the simulation result;
specifically, the combinatorial logic processing specifically includes: polarity inversion and DC offset compensation.
In step 305, a filter reset signal is generated based on the clock domain signal, the clock domain selection signal and the mask signal, the filter is controlled to sample and filter the preprocessing result, the filter in the triggered clock domain signal outputs a valid result, and the filter in the non-triggered clock domain signal cannot output a valid result.
It should be noted that the explanation of the system for fast switching between multiple clock domains in the foregoing embodiment is also applicable to the method for fast switching between multiple clock domains in the foregoing embodiment, and details are not described here.
In summary, according to the method for fast switching between multiple clock domains in the embodiment of the present application, by adding the filtering module and the mask module, the triggers belonging to different clock domains can be fast switched and transmitted without leaving a residual result of the previous trigger, and the number of used synchronizers is reduced, so that the response is fast and the delay is low.
Example 3
Fig. 12 is a schematic diagram of a chip structure according to an embodiment of the present application. Referring to fig. 12, the chip 40 has the multi-clock domain fast switching system 10 integrated thereon as described above.
Example 4
Fig. 13 is a schematic diagram of a circuit board structure according to an embodiment of the present application. Referring to fig. 13, the circuit board 50 includes the chip 40 thereon as described above.
Example 5
Fig. 14 is a schematic structural diagram of a vehicle machine according to an embodiment of the application. Referring to fig. 14, the cart machine 60 includes the chip 40 as described above.
Example 6
In an embodiment of the present application, there is also provided an electronic device, including: a memory having stored therein computer instructions and a processor configured to execute the instructions to perform the steps of the method of multi-clock domain fast handoff of the above embodiments.
Example 7
In one embodiment of the present application, there is also provided a computer-readable storage medium, which may be included in the system described in the above embodiment; or may exist separately and not be assembled into the system. The computer-readable storage medium carries one or more computer instructions which, when executed, implement the steps of the multi-clock domain fast handover method of the above embodiments.
In embodiments of the present application, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Those of ordinary skill in the art will understand that: although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention as defined in the appended claims. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (14)
1. A system for fast switching between multiple clock domains, comprising:
a trigger generation module configured to generate and output trigger signals and trigger indication signals of different configurations based on an external trigger request and an internal timing trigger request, wherein the trigger indication signals are used for controlling switching among a plurality of clock domains;
a mask module configured to generate and output a clock domain selection signal and a mask signal based on the trigger indication signal and a configuration parameter;
an analog module configured to generate and output an analog result based on a plurality of level signals and the trigger signal;
a preprocessing module configured to generate and output a preprocessing result based on the simulation result;
a filtering module including a plurality of filters located in different clock domains and configured to generate a filter reset signal based on a clock domain signal, the clock domain selection signal and the mask signal, control the filters to sample and filter the preprocessing result, wherein the filter located in the triggered clock domain signal outputs a valid result, and the filter located in the clock domain signal that is not triggered cannot output a valid result.
2. The system of claim 1, wherein an output of the trigger generation module is connected to an input of the analog module, an output of the analog module is connected to an input of the preprocessing module, an output of the preprocessing module is connected to a first input of the filtering module, an input of the mask module is connected to an output of the trigger generation module, and an output of the mask module is connected to a second input of the filtering module.
3. The system of claim 2, wherein the trigger generation module comprises: a first selector and a first counter; the first input end of the first selector inputs the external trigger request, the second input end of the first selector is connected with the output end of the first counter, the output end of the first counter outputs the internal timing trigger request, and the output end of the first selector outputs the trigger signal and the trigger indication signal;
the first counter is used for generating an internal timing trigger request.
4. The system according to claim 1, wherein the mask module comprises a second counter, an input terminal of the second counter inputs the trigger indication signal, a clear terminal of the second counter inputs a configuration parameter, and an output terminal of the second counter outputs the mask signal and the clock domain selection signal.
5. The system of claim 1, wherein the trigger signal comprises: a channel selection signal and a sampling time;
the analog module comprises one of an analog voltage comparator and an analog-to-digital converter;
the analog voltage comparator is used for comparing voltages based on a plurality of level signals and a channel selection signal to obtain a comparison result of the voltages, and outputting the comparison result as the analog result;
and the analog-to-digital converter is used for performing analog-to-digital conversion based on the plurality of level signals, the channel selection signal and the sampling time to obtain an analog-to-digital conversion result of the output voltage, and outputting the analog result.
6. The system of claim 1, wherein the pre-processing module comprises: the polarity inversion module, the second selector, the direct current offset compensation module and the third selector; the first input end of the second selector inputs the simulation result, one end of the polarity inverting module inputs the simulation result, the other end of the polarity inverting module is connected with the second input end of the second selector, the output end of the second selector is connected with the first input end of the third selector, one end of the direct current offset compensation module is connected with the output end of the second selector, the other end of the direct current offset compensation module is connected with the second input end of the third selector, and the output end of the third selector outputs the preprocessing result.
7. The system of claim 1, wherein the filtering module further comprises a plurality of sets of two cascaded registers and a multi-input or gate, the two cascaded registers being asynchronously reset and synchronously released;
in each group, the clock ends of the two cascaded registers respectively input the clock domain signal, a first reset signal obtained by performing logic and operation on the clock domain selection signal and the negated mask signal is respectively used as asynchronous reset signals of the two cascaded registers to be input into the reset ends of the two cascaded registers, a filter reset signal output by a second register of the two cascaded registers is used as a reset signal of the filter to be input into the reset end of the filter, the clock end of the filter inputs the clock domain signal, the input end of the filter inputs the preprocessing result, and the output end of the filter is connected to the input end of the multi-input or gate;
the multiple input ends of the multiple input OR gate are connected with the output end of the filter in each group, the filter positioned in the triggered clock domain signal outputs a valid result, and the filter positioned in the clock domain signal which is not triggered can not output a valid result.
8. The system of claim 1, wherein the first time is the time at which the trigger indication signal is generated,
at a first moment, the triggered clock domain sends the trigger indication signal, and the trigger indication signal is positioned at the reset of a filter of the clock domain signal which is not triggered;
and at the second moment, the triggered clock domain samples the preprocessing result and filters the preprocessing result, and the filter positioned on the triggered clock domain signal outputs a valid result.
9. A method for fast switching of multiple clock domains comprises the following steps:
generating and outputting trigger signals and trigger indication signals of different configurations based on the external trigger request and the internal timing trigger request, wherein the trigger indication signals are used for controlling switching among a plurality of clock domains;
generating and outputting a clock domain selection signal and a mask signal based on the trigger indication signal and the configuration parameters;
generating and outputting a simulation result based on a plurality of level signals and the trigger signal;
generating a preprocessing result based on the simulation result and outputting the preprocessing result;
and generating a filter reset signal based on the clock domain signal, the clock domain selection signal and the mask signal, controlling the filter to sample and filter the preprocessing result, wherein the filter positioned in the triggered clock domain signal outputs a valid result, and the filter positioned in the clock domain signal which is not triggered can not output a valid result.
10. A chip having integrated thereon the multi-clock domain fast switching system of any one of claims 1 to 8.
11. A circuit board comprising the chip of claim 10.
12. A vehicle machine, characterized in that, the vehicle machine comprises the chip of claim 10.
13. An electronic device comprising a memory and a processor, wherein the memory has stored therein computer instructions, and the processor is configured to execute the instructions to perform the steps of the method for multi-clock domain fast switching of claim 9.
14. A computer readable storage medium having stored thereon computer instructions which, when executed, perform the method for multi-clock domain fast handoff of claim 9.
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| JP2002314424A (en) * | 2001-04-13 | 2002-10-25 | Nec Microsystems Ltd | Digital/analog converter circuit |
| CN102012717A (en) * | 2010-11-16 | 2011-04-13 | 青岛海信信芯科技有限公司 | Clock switching method and device |
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