CN117766004A - Data writing method, memory storage device and memory control circuit unit - Google Patents

Abstract

The invention provides a data writing method, a memory storage device and a memory control circuit unit. The method comprises the following steps: obtaining a writing instruction; according to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in a plurality of word lines; and selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units having voids arranged behind the target physical units in the target word line are present after the first data is written; and writing second data subsequent to the first data in the write data to the one or more further target physical units selected, wherein the one or more further target word lines are arranged subsequent to the target word lines.

Description

Data writing method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a data writing method, and more particularly, to a data writing method, a memory storage device, and a memory control circuit unit for a rewritable nonvolatile memory module.

Background

Conventionally, when performing a data writing operation on a rewritable nonvolatile memory module, the writing order adopted is specific, i.e., a plurality of physical cells in the same word line are sequentially written according to the arrangement order of the word string group. If all the physical cells of one word line are full or can no longer be written with data, the next blank word line is selected for the subsequent data writing operation.

Disclosure of Invention

The invention provides a data writing method, a memory storage device and a memory control circuit unit, which provide novel data writing sequence to reduce the operation resources consumed for generating parity correction codes and further increase the working efficiency.

An exemplary embodiment of the present invention provides a data writing method for a rewritable nonvolatile memory, wherein the rewritable nonvolatile memory module includes a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines constitute a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module includes P word lines, each word line includes M segments corresponding to M word string groups, wherein each segment of the M segments and the intersecting N bit lines constitute N memory cells corresponding to the same word string group, and the N memory cells constitute one physical cell, such that MxN memory cells of each word line constitute M physical cells corresponding to the M word string groups. The method comprises the following steps: obtaining a write instruction, wherein the write instruction is used for indicating writing of write data to the rewritable nonvolatile memory module; according to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in the P word lines; and selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units having voids arranged behind the target physical units in the target word line are present after the first data is written; and writing second data succeeding the first data in the write data to the one or more further target entity units selected.

In an example embodiment of the present invention, the step of writing the first data of the write data to the target physical cell of the target word line of the P word lines includes writing the first data to a j-th physical cell corresponding to a j-th word string group in an i-th word line, wherein the i-th word line is the target word line and the j-th physical cell is the target physical cell. In addition, writing the second data to the one or more further target physical units respectively located in the one or more further target word lines includes writing the second data to a j-th physical unit corresponding to the j-th word string group in an i+1th word line, wherein the i+1th word line is the further target word line and the j-th physical unit in the i+1th word line is the further target physical unit.

In an example embodiment of the present invention, after writing the second data, the method further comprises: writing third data which is connected with the second data in the written data into a j+1th entity unit corresponding to a j+1th word string group in the i-th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is not written with data; and writing fourth data, which is subsequent to the third data, in the writing data into a j+1th entity unit corresponding to the j+1th word string group in the i+1th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is blank.

In an example embodiment of the present invention, after writing the second data, the method further comprises: before writing third data which is connected after the second data in the written data, judging whether a (j) th entity unit which is positioned in the (i+2) th word line and corresponds to the (j) th word string group is present or not; writing the third data to a jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group in response to determining that there is the jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group; and writing the third data to the j+1th entity unit corresponding to the j+1th word string group in the ith word line in response to determining that the blank j-th entity unit corresponding to the j-th word string group in the ith+2th word line does not exist.

In an exemplary embodiment of the present invention, the plurality of word lines and the plurality of bit lines intersecting the plurality of word lines form a three-dimensional structure, wherein the plurality of bit lines are grouped into the M word line groups sequentially arranged along a first direction, the N bit lines of each word line group are sequentially arranged along a second direction and extend along a third direction, wherein the P word lines of the same word line group are sequentially arranged along the third direction and extend along the second direction, wherein the P word lines are sequentially arranged along the third direction, wherein the N bit lines of each word line group together intersect into P segments of the corresponding same word line group, each of the M word line groups belonging to the P word lines, to form the MxN memory cells within each word line, and further form the M physical cell groups of each word line group sequentially arranged along the first direction, wherein the first direction, the third direction, and the third direction are perpendicular to each other.

In an example embodiment of the present invention, wherein the step of writing the first data of the write data to the target physical cell of the target word line of the P word lines and the step of writing the second data to the one or more further target physical cells respectively located within the one or more further target word lines comprises writing the first data and the second data to a plurality of first physical cells respectively located within a plurality of first word lines arranged along the third direction corresponding to a j-th word string group.

In an exemplary embodiment of the present invention, wherein a total number of the plurality of first entity units is determined according to a ratio of data amounts required for generating parity data, the method further comprises: parity data corresponding to the first data and the second data is generated according to the written first data and second data, wherein the ratio between the sizes of the first data and the second data and the generated size of the parity data is the data amount ratio, and the total number of the plurality of first entity units is used for storing the first data and the second data.

In an example embodiment of the present invention, after writing the second data, the method further comprises: and writing third data which is connected with the second data in the written data into a plurality of second entity units which are respectively positioned in the first word lines arranged along the third direction and correspond to the j+1th word string group, wherein the third entity units which are arranged behind the first entity units along the third direction are blank.

In an example embodiment of the present invention, after writing the second data, the method further comprises: before writing third data which is subsequent to the second data in the written data, judging whether one or more third entity units which are arranged behind the first entity units along the third direction and correspond to the blank of the j-th string group exist or not; writing the third data to the blank one or more third entity units in response to determining that the blank one or more third entity units corresponding to the jth word string group arranged behind the first entity units in the third direction exist, wherein the blank one or more third entity units are respectively positioned on one or more second word lines arranged behind the first word lines in the third direction; and writing the third data to a plurality of second entity units corresponding to j+1th word string groups respectively located in the plurality of first word lines arranged along the third direction in response to determining that the one or more third entity units corresponding to the blank of the j-th word string group arranged behind the plurality of first entity units along the third direction do not exist.

In an example embodiment of the invention, the method further comprises: in response to determining that there are no one or more third entity units in the third direction that are arranged after the plurality of first entity units and that correspond to the j-th string group, backing up data stored in all entity units corresponding to the j-th string group within the P word lines and parity data corresponding to the data before writing the third data to the plurality of second entity units corresponding to the j+1th string group; and writing the third data to the plurality of second entity units corresponding to the j+1th word string group respectively located in the plurality of first word lines arranged in the third direction after backing up the data corresponding to the j-th word string group and parity data corresponding to the data.

Exemplary embodiments of the present invention provide a data writing method for a rewritable nonvolatile memory. The rewritable nonvolatile memory module comprises a plurality of physical erasing units, wherein each physical erasing unit comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module comprises P word lines, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical cells corresponding to the M word string groups. The method comprises the following steps: generating and transmitting a first write command sequence via a memory management circuit to instruct writing of first write data to a target physical erase unit of the plurality of physical erase units; generating and sending, via the memory management circuit, a second write instruction sequence to instruct writing of second write data to the target physical erase unit; writing the first writing data to a first entity address in the target entity erasing unit through a memory interface according to the first writing instruction sequence; and writing the second write data to a second physical address in the target physical erase unit according to the second write instruction sequence via the memory interface. In addition, the first word line to which the first physical address belongs is different from the second word line to which the second physical address belongs, wherein when second write data is written to the second physical address in the target physical erase unit, one or more physical addresses which are arranged behind the first physical address are arranged in the first word line, and no write command sequence for indicating the write data to the target physical erase unit is executed in a time interval between the execution of the first write command sequence and the execution of the second write command sequence.

In an exemplary embodiment of the present invention, the memory management circuit records a physical address list, wherein the data of a plurality of columns of the physical address list includes a plurality of physical address numbers corresponding to a plurality of physical addresses, a plurality of word line identifiers corresponding to the plurality of physical address numbers, and a plurality of word string group identifiers corresponding to the plurality of physical address numbers. The method further comprises the steps of: generating, via the memory management circuit, the first write instruction sequence according to a first physical address number of the plurality of physical address numbers to instruct writing of the first write data to the first physical address corresponding to the first physical address number, wherein the first physical address is a first physical unit of a first string group within a first word line corresponding to the first physical address number; and generating, via the memory management circuit, the second sequence of write instructions according to a second physical address number of the plurality of physical address numbers to instruct writing of the second write data to the second physical address corresponding to the second physical address number, wherein the second physical address is a second physical unit of a second string group within a second word line corresponding to the second physical address number, wherein the first physical address number and the second physical address number are not two consecutive physical address numbers in the physical address list.

In an exemplary embodiment of the present invention, the plurality of physical addresses corresponding to the plurality of physical address numbers in the physical address list are grouped into a plurality of groups of physical addresses according to the sequence of the corresponding plurality of word line identification codes, wherein the plurality of physical addresses in each group of physical addresses are arranged according to the sequence of the corresponding plurality of word string groups, and the plurality of physical address numbers are arranged from small to large.

An exemplary embodiment of the present invention provides a memory storage device, including: the memory control circuit unit is connected with the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The connection interface unit is used for being electrically connected to the host system. The rewritable nonvolatile memory module comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module comprises P word lines, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical units corresponding to the M word string groups. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: obtaining a write instruction, wherein the write instruction is used for indicating writing of write data to the rewritable nonvolatile memory module; according to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in the P word lines; after writing the first data, selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units which are arranged behind the target physical units are arranged in the target word line; and writing second data succeeding the first data in the write data to the one or more further target entity units selected.

An exemplary embodiment of the present invention provides a memory storage device, including: the memory control circuit unit is connected with the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The connection interface unit is used for being electrically connected to the host system. The rewritable nonvolatile memory module comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module comprises P word lines, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical units corresponding to the M word string groups. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory management circuit of the memory control circuit unit is configured to generate and send a first write command sequence to indicate writing of first write data to a target entity erasing unit of the plurality of entity erasing units, wherein the memory management circuit is further configured to generate and send a second write command sequence to indicate writing of second write data to the target entity erasing unit, wherein the memory interface of the memory control circuit unit is configured to write the first write data to a first entity address in the target entity erasing unit according to the first write command sequence, wherein the memory interface is further configured to write the second write data to a second entity address in the target entity erasing unit according to the second write command sequence, wherein a first word line to which the first entity address belongs is different from a second word line to which the second entity address belongs, wherein the first word line has a first entity address and no write command sequence arranged in the first entity address or any write command sequence after the first write command sequence is performed.

An exemplary embodiment of the present invention provides a memory control circuit unit including: host interface, memory interface and memory management circuitry. The host interface is used for being electrically connected to a host system. The memory interface is used for being electrically connected to the rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module comprises P word lines, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical units corresponding to the M word string groups. The memory management circuit is electrically connected to the host interface and the memory interface, wherein the memory management circuit is configured to: obtaining a write instruction, wherein the write instruction is used for indicating writing of write data to the rewritable nonvolatile memory module; according to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in the P word lines; after writing the first data, selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units which are arranged behind the target physical units are arranged in the target word line; and writing second data succeeding the first data in the write data to the one or more further target entity units selected.

An exemplary embodiment of the present invention provides a memory control circuit unit including: host interface, memory interface and memory management circuitry. The host interface is used for being electrically connected to a host system. The memory interface is used for being electrically connected to the rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module comprises P word lines, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical units corresponding to the M word string groups. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is configured to generate and send a first write command sequence to instruct writing of first write data to a target entity erase unit of the plurality of entity erase units, wherein the memory management circuit is further configured to generate and send a second write command sequence to instruct writing of second write data to the target entity erase unit, wherein the memory interface is configured to write the first write data to a first entity address in the target entity erase unit according to the first write command sequence, wherein the memory interface is further configured to write the second write data to a second entity address in the target entity erase unit according to the second write command sequence, wherein a first word line to which the first entity address belongs is different from a second word line to which the second entity address belongs, wherein there is a first sequence of write commands arranged in the first word line at a first entity address after the first entity address is written to the second entity address in the target entity erase unit, and wherein no blank sequence of write commands is performed in the first entity erase unit, wherein the first sequence of write commands is performed at a blank time interval.

Based on the above, the exemplary embodiments of the present invention can use the provided data writing sequences of different aspects to write the plurality of physical units corresponding to the same word string group in the plurality of word lines along the arrangement direction of the plurality of word lines, so as to save the system resources required in the process of generating parity data, and further improve the working efficiency of the memory storage device 10 and the memory control circuit 42. Meanwhile, the problem of write interference caused by a write sequence different from the traditional write sequence or the problem of data loss caused by the error of written data can be avoided.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5A is a schematic diagram of a three-dimensional memory cell array according to an example embodiment of the invention;

FIG. 5B is a schematic diagram of an equivalent circuit of a three-dimensional memory cell array according to an example embodiment of the invention;

FIG. 6 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 7 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 8A is a flowchart of a data writing method according to an example embodiment of the invention;

FIG. 8B is a flowchart of another data writing method according to an example embodiment of the invention;

FIG. 9A is a schematic diagram of a plurality of physical units corresponding to different word lines and word string groups according to an example embodiment of the invention;

FIG. 9B is a diagram of a physical address list shown in accordance with an exemplary embodiment of the present invention;

FIG. 10 is a diagram of a conventional write sequence of a physical cell according to the prior art;

FIG. 11 is a diagram illustrating a write sequence of a first aspect of a physical cell according to an example embodiment of the present invention;

FIG. 12 is a diagram illustrating a write sequence of a second aspect of a physical cell according to an example embodiment of the present invention;

FIG. 13 is a schematic diagram of a third state-like write sequence of a physical cell, according to an example embodiment of the invention;

FIG. 14 is a schematic diagram of parity data generation according to the prior art;

FIG. 15A is a schematic diagram illustrating the generation of parity data in accordance with an exemplary embodiment of the present invention;

FIG. 15B is a schematic diagram illustrating the generation of parity data in accordance with another exemplary embodiment of the present invention;

fig. 16 is a schematic diagram illustrating the generation of parity data according to another exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be electrically connected to a system bus 110.

In an exemplary embodiment, the host system 11 may be electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 may be electrically connected to the I/O device 12 via the system bus 110. For example, host system 11 may transmit output signals to I/O devices 12 or receive input signals from I/O devices 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114.

In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203 or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention.

Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded memory device 34 includes embedded memory devices of various types, such as embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or embedded multi-chip package (embedded Multi Chip Package, eMCP) memory device 342, that electrically connect the memory module directly to the substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used for electrically connecting the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. In an exemplary embodiment, the connection interface unit 41 may also be a serial advanced attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is electrically connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If a memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and one physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

In an exemplary embodiment, the memory cells in the rewritable nonvolatile memory module 43 are arranged in a three-dimensional array. However, in another exemplary embodiment, the memory cells in the rewritable nonvolatile memory module 43 are arranged in a two-dimensional array.

Fig. 5A is a schematic diagram of a three-dimensional memory cell array according to an exemplary embodiment of the present invention.

Referring to fig. 5A, the memory cell array 51 includes a plurality of memory cells 52 for storing data, a plurality of word string groups 531 to 534, and a plurality of word lines 541 to 548. The string groups 531 to 534 are independent of each other (e.g., separated from each other) and are arranged in a first direction (e.g., X-axis direction). Each of the string groups 531-534 includes a plurality of bit lines 530 that are independent of each other (e.g., separate from each other). The bit lines 530 in each string group are aligned in a second direction (e.g., Y-axis direction) and extend in a third direction (e.g., Z-axis direction). The word lines 541-548 are independent of each other (e.g., separate from each other) and stacked along a third direction.

In an example embodiment, each of the word lines 541-548 may also be considered a word line plane. Each memory cell 52 is disposed at each intersection between each bit line 530 and word lines 541-548 in the string groups 531-534.

It should be noted that the memory cell array 51 of FIG. 5A is only an example, and in other non-mentioned example embodiments, the total number of memory cells 52, the total number of word string groups 531-534, and the total number of word lines 541-548 may be different. Furthermore, in another example embodiment, one string group may include more or fewer bit lines, and one word line may also pass more or fewer string groups. Alternatively, in an exemplary embodiment, the memory cells in the rewritable nonvolatile memory module 43 may be configured in other manners, and the present invention is not limited thereto.

In other words, the rewritable nonvolatile memory module 43 includes a plurality of word lines and a plurality of bit lines intersecting the word lines, wherein intersections of the word lines and the bit lines form a plurality of memory cells for storing data. In one embodiment, each of the word lines 541-548 (a plane) arranged according to the third direction is divided into M segments according to M word string groups (e.g., 4 word string groups arranged according to the first direction in fig. 5A), and a plurality of memory cells formed in each segment can be regarded as a physical cell. Wherein each of the M segments and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit. The N, M, P is a positive integer. Furthermore, in the present exemplary embodiment, the plurality of word lines and the plurality of bit lines intersecting the plurality of word lines form a three-dimensional structure, wherein the plurality of bit lines are grouped into the M word line groups sequentially arranged along a first direction, the N bit lines of each word line group are sequentially arranged along a second direction and extend along a third direction, wherein the P word lines of the same word line group are sequentially arranged along the third direction and extend along the second direction, wherein the P word lines are sequentially arranged along the third direction, wherein the N bit lines of each word line group together intersect to P sections of the same word line group, each belonging to the P word lines, to constitute the MxN memory cells within each word line, and further constitute the M physical cells of the M word line groups sequentially arranged along the first direction within each word line, wherein the first direction, the third direction, and the third direction are perpendicular to each other.

Fig. 5B is a schematic diagram of an equivalent circuit of a three-dimensional memory cell array according to an exemplary embodiment of the present invention.

Referring to fig. 5A and 5B, transistor cells 521 (1) through 521 (n) may be located on a word line 541. Transistor cells 522 (1) -522 (n) may be located in word line 542. Transistor cells 523 (1) -523 (n) may be located in word line 543. Transistor cells 528 (1) -528 (n) may be located on word line 548. One transistor cell may be equivalent to one memory cell. String group 531 may include bit lines 531 (1) -531 (n). Bit line 531 (1) is connected in series with transistor cell 521 (1), transistor cell 522 (1), transistor cell 523 (1) … and transistor cell 528 (1). Bit line 531 (2) is connected in series with transistor cell 521 (2), transistor cell 522 (2), transistor cell 523 (2) … and transistor cell 528 (2). Bit line 531 (3) is connected in series with transistor cell 521 (3), transistor cell 522 (3), transistor cell 523 (3) … and transistor cell 528 (3). Similarly, bit line 531 (n) connects transistor cell 521 (n), transistor cell 522 (n), transistor cell 523 (n) …, and transistor cell 528 (n) in series.

The segment 551 is located on the word line 541. Segment 552 is located on word line 542. Section 553 is located in wordline 543. Similarly, segment 558 is located on word line 548. Segment 551 connects transistor cells 521 (1) through 521 (n) in series. Segment 552 is serially connected to transistor cells 522 (1) through 522 (n). Segment 553 is coupled in series with transistor cells 523 (1) to 523 (n). Segment 558 is serially connected to transistor cells 528 (1) through 528 (n). It should be noted that fig. 5B only shows a part of the components in each word line in fig. 5A, and the rest can be so on.

In the present exemplary embodiment, the total number of transistor cells connected in series in the same segment of the same word line may be equal to the total number of memory cells included in one physical cell. For example, transistor cells 521 (1) through 521 (n) are included in physical cell 561, transistor cells 522 (1) through 522 (n) are included in physical cell 562, transistor cells 523 (1) through 523 (n) are included in physical cell 563, and transistor cells 528 (1) through 528 (n) are included in physical cell 568. Taking the physical unit 561 as an example, when the data stored in the physical unit 561 is to be read, the memory states of the transistor units 521 (1) through 521 (n) can be read simultaneously; in addition, when data is to be stored in the physical unit 561, the transistor units 521 (1) through 521 (n) can be programmed simultaneously.

In an exemplary embodiment, the total number of memory cells included in each of the physical units 561-568 is equal to the total number of memory cells included in one physical programming unit. That is, in an exemplary embodiment, the physical units 561-568 are each considered as one physical programming unit. In an exemplary embodiment, at least one of the physical units 561-568 may also include a plurality of physical programming units.

Fig. 6 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention.

Referring to fig. 6, the memory control circuit unit 42 includes a memory management circuit 61, a host interface 62 and a memory interface 63. The memory management circuit 61 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 61 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 61 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 61 are implemented in firmware. For example, the memory management circuit 61 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 61 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (for example, a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 61 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 61. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 61 may also be implemented in a hardware type. For example, the memory management circuit 61 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 61 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 62 is electrically connected to the memory management circuit 61. The memory management circuit 61 may communicate with the host system 11 through a host interface 62. The host interface 62 may be used to obtain and identify instructions and data of the host system 11. For example, instructions and data of host system 11 may be transferred to memory management circuit 61 through host interface 62. In addition, the memory management circuit 61 may transfer data to the host system 11 through the host interface 62. In the present example embodiment, the host interface 62 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 62 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 63 is electrically connected to the memory management circuit 61 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 61 may access the rewritable nonvolatile memory module 43 through the memory interface 63. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 63. Specifically, if the memory management circuit 61 is to access the rewritable nonvolatile memory module 43, the memory interface 63 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 61 and transferred to the rewritable non-volatile memory module 43 via the memory interface 63. The instruction sequences may include one or more signals, or data on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 64, a buffer memory 65, and a power management circuit 66.

The error checking and correcting circuit 64 is electrically connected to the memory management circuit 61 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 61 obtains the write command from the host system 11, the error checking and correcting circuit 64 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 61 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 61 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 64 performs an error check and correction operation on the read data according to the error correction code and/or the error check code. In addition, in one embodiment, the error checking and correcting circuit 64 is further configured to generate corresponding parity data (also called as disk array parity data, RAID parity) according to the written data and the Tag (also called as disk array Tag) corresponding to the written data, so that the corresponding written data can be protected by the generated parity data.

The buffer memory 65 is electrically connected to the memory management circuit 61 and is used for temporarily storing data. The power management circuit 66 is electrically connected to the memory management circuit 61 and is used for controlling the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 61 of fig. 6 may include a flash memory management circuit.

FIG. 7 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.

Referring to FIG. 7, the memory management circuit 61 can logically group the physical units 710 (0) -710 (B) in the rewritable nonvolatile memory module 43 into a memory area 701 and a spare (spare) area 702.

The physical units 710 (0) -710 (a) in the storage area 701 are configured to store user data (e.g., user data from the host system 11 of fig. 1). For example, entity units 710 (0) -710 (a) in the storage area 701 may store valid (valid) data and/or invalid (invalid) data. The physical units 710 (a+1) -710 (B) in the spare area 702 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle zone 702. In addition, the physical cells in the spare area 702 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 702 to store the new data. In an exemplary embodiment, the free area 702 is also referred to as a free pool (free pool).

Memory management circuit 61 may configure logic units 712 (0) -712 (C) to map physical units 710 (0) -710 (a) in memory region 701. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 61 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 of fig. 1 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 61 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table to store data in the rewritable nonvolatile memory module 43 or read data from the rewritable nonvolatile memory module 43.

The memory management circuit 61 may obtain a write instruction from the host system 11 of fig. 1. The write instruction may instruct writing data to at least one logic unit. The memory management circuit 61 may implement the data writing method provided in the present exemplary embodiment to perform the corresponding data writing operation, so as to write the corresponding writing data into at least one physical unit through a specific writing sequence. After the memory management circuit 61 writes the data corresponding to the write instruction into at least one physical unit, the corresponding logical-to-physical mapping table is updated to map the at least one physical unit to the at least one logical unit.

The data writing method provided by the present exemplary embodiment is described in detail below with reference to fig. 8A to 13.

Fig. 8A is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention.

Referring to fig. 8A, in step S810, the memory control circuit unit 42 obtains a write command, wherein the write command is used to instruct to write data to the rewritable nonvolatile memory module 43. Such as a write instruction (also referred to as a host write instruction) retrieved from the host system 11, or a write instruction (e.g., a sequence of write instructions) generated by the memory control circuit unit 42.

Next, in step S820, the memory control circuit unit 42 writes the first data of the write data to the target physical unit of the target word line of the P word lines according to the write command. P is a positive integer, and the number thereof is preset according to the hardware specification of the rewritable nonvolatile memory module 43, and the present invention is not limited thereto. That is, the first data is written into a physical cell (target physical cell) in one of the word lines (target word line).

In one embodiment, the step of writing the first data in the write data to the target physical unit of the target word line in the P word lines includes the memory control circuit unit 42 writing the first data to a j-th physical unit corresponding to a j-th word string group in an i-th word line, wherein the i-th word line is the target word line, and the j-th physical unit is the target physical unit. i. j is a positive integer.

Next, in step S830, after writing the first data, when there are one or more dummy cells arranged behind the target physical cells in the target word line, one or more further target physical cells respectively located in one or more further target word lines are selected. That is, after the first data is written, one or more entity units arranged behind the target entity unit along the first direction in the target word line are still blank entity units, which can be written with data. However, at this time, the memory control circuit unit 42 does not directly select one or more of the empty physical units arranged behind the target physical unit for performing the subsequent data writing operation according to the conventional method. However, the memory control circuit unit 42 selects one or more further target physical units respectively located in one or more further target word lines to perform a subsequent data writing operation. The one or more further target word lines may be one or more word lines arranged before or after the target word line in the third direction, and the one or more further target physical cells of the one or more further target word lines are blank. For convenience of explanation, the one or more further target word lines will be described later as being arranged after the target word lines in the third direction.

Next, in step S840, the memory control circuit unit 42 writes the second data following the first data in the write data to the selected one or more further target entity units. That is, after the one or more further target entity units are selected, the memory control circuit unit 42 performs a subsequent data writing operation to write the second data to the selected one or more further target entity units.

In one embodiment, the step of writing the second data to the one or more further target physical units respectively located in the one or more further target word lines includes the memory control circuit unit 42 writing the second data to a j-th physical unit corresponding to the j-th word string group in an i+1th word line, wherein the i+1th word line is the further target word line, and the j-th physical unit in the i+1th word line is the further target physical unit.

In addition, in the present embodiment, after writing the second data, if a subsequent data writing operation is performed, the memory control circuit unit 42 writes the third data, which is subsequent to the second data, in the write data to the j+1th physical unit corresponding to the j+1th word string group in the i-th word line, where the j-th physical unit corresponding to the j-th word string group in the i+2th word line is not written with data; and writing fourth data, which is subsequent to the third data, in the writing data into a j+1th entity unit corresponding to the j+1th word string group in the i+1th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is blank.

FIG. 9A is a schematic diagram of a plurality of physical units corresponding to different word lines and word string groups according to an example embodiment of the invention.

Referring to fig. 9A, for convenience of description, the following description will be made with a rewritable nonvolatile memory module that is SLC, i.e., in this embodiment, each physical unit is 1 physical page (or programming unit). However, the data writing method provided by the invention can also be applied to TLC or other types of rewritable nonvolatile memory modules.

In addition, in this example, the number of word lines of the rewritable nonvolatile memory module is 4 (e.g., word lines WL1 to WL4 shown in fig. 9A), and the number of String groups is 4 (e.g., string groups String1 to String4 shown in fig. 9A). Each word line has 4 physical units (shown as squares) corresponding to the plurality of word string groups, and the arrangement sequence of the physical units is the same as that of the word string groups. For example, the entity units PU12 corresponding to String2 are arranged in a first direction (as shown in FIG. 5A) after the entity units PU11 corresponding to the first String 1. In addition, the word line WL2 is arranged after the word line WL1 along the third direction (as shown in fig. 5A).

In addition, the corresponding String groups String1, string2, string3, string4: word line WL1 has physical cells PU11, PU12, PU13, PU14; word line WL2 has physical cells PU21, PU22, PU23, PU24; word line WL3 has physical cells PU31, PU32, PU33, PU34; word line WL4 has physical cells PU41, PU42, PU43, PU44. When the physical unit corresponding to the specified word line and the specified word string group is written with data, the physical unit is written at one time.

Fig. 8B is a flowchart illustrating another data writing method according to an exemplary embodiment of the present invention.

Referring to fig. 8B, fig. 8B shows a data writing method from the perspective of the memory control circuit. In step S850, a first write command sequence is generated and sent via the memory management circuit 61 to instruct to write the first write data to the target physically erased cell of the physically erased cells of the rewritable nonvolatile memory module 43. Each physical erasing unit comprises a plurality of word lines and a plurality of bit lines intersecting the word lines, wherein the intersections of the word lines and the bit lines form a plurality of memory cells for storing data.

Next, in step S860, a second write command sequence is generated and sent via the memory management circuit 61 to instruct to write second write data to the target physical erase unit.

In more detail, referring to fig. 9B, the memory management circuit 61 records an entity address list PATB, wherein the data of the columns of the entity address list PATB includes a plurality of entity address numbers (e.g. numbers "1" to "5" in the entity address list PATB) corresponding to the plurality of entity addresses, a plurality of word line identifiers (e.g. word line identifiers "WL1" and "WL2" in the entity address list PATB) corresponding to the plurality of entity address numbers, and a plurality of String identifiers (e.g. String identifiers "String1" to "String4" in the entity address list PATB) corresponding to the plurality of entity address numbers. The plurality of entity addresses corresponding to the plurality of entity address numbers in the entity address list PATB are grouped into a plurality of groups of entity addresses according to the sequence of the corresponding plurality of word line identification codes, wherein the plurality of entity addresses in each group of entity addresses are arranged according to the sequence of the corresponding plurality of word string groups, and the plurality of entity address numbers are arranged from small to large. By querying the physical address list PATB, word lines and word string groups of the physical units (e.g., the physical units PU 11-PU 21) corresponding to each physical address number can be searched.

In this embodiment, step S850 includes: the first write instruction sequence is generated according to a first physical address number of the plurality of physical address numbers via the memory management circuit 61 to instruct to write the first write data to the first physical address corresponding to the first physical address number, wherein the first physical address is a first physical unit of a first string group within a first word line corresponding to the first physical address number.

Further, step S860 includes: the second write instruction sequence is generated according to a second physical address number of the plurality of physical address numbers via the memory management circuit 61 to instruct to write the second write data to the second physical address corresponding to the second physical address number, wherein the second physical address is a second physical unit of a second string group within a second word line corresponding to the second physical address number. It should be noted that the first physical address number and the second physical address number of the corresponding one and the second write instruction sequence are not two consecutive physical address numbers in the physical address list.

In addition, in an embodiment, the first string group in the first word line corresponding to the first physical address number and the second string group in the second word line corresponding to the second physical address number belong to substantially the same string group. For example, the first write data is written to the entity unit PU11 (which belongs to the String group String 1) shown in fig. 9A, and the second write data is written to the PU21 (which belongs to the String group String 1) shown in fig. 9A.

However, in another embodiment, the first string group in the first word line corresponding to the first physical address number and the second string group in the second word line corresponding to the second physical address number belong to different string groups, respectively. For example, the first write data is written to the entity unit PU21 (which belongs to the String group String 1) shown in fig. 9A, and the second write data is written to the PU12 (which belongs to the String group String 2) shown in fig. 9A.

Next, in step S870, the first write data is written to the first physical address in the target physical erase unit according to the first write command sequence via the memory interface 63.

Next, in step S880, the second write data is written to the second physical address in the target physical erasing unit according to the second write command sequence via the memory interface 63. The first word line to which the first physical address belongs is different from the second word line to which the second physical address belongs, wherein when second write data is written to the second physical address in the target physical erase unit, one or more physical addresses which are arranged behind the first physical address are arranged in the first word line, and no write command sequence for indicating the write data to the target physical erase unit is executed in a time interval between the execution of the first write command sequence and the execution of the second write command sequence.

For example, assume that a first write command sequence is generated according to a first physical address number "1" for indicating to write data to physical cell PU11 of corresponding String set String1 in word line WL 1; the second write command sequence is generated according to the second physical address "5" for indicating the physical unit PU21 for writing data into the corresponding String1 in the word line WL 2. When second write data corresponding to a second write command sequence is written to the second physical address (number "5") in the target physical erase unit, one or more physical addresses (numbers "2" to "4") that are blank after the first physical address (number "1") are arranged in the word line WL 1.

FIG. 10 is a diagram illustrating a conventional write sequence of a physical cell according to the prior art.

Referring to fig. 9A and 10, as shown in the table TB10, the numbers in each square and the arrows in the drawing are used to indicate the writing order of the corresponding physical units (not described below). In general, the specification manual of the rewritable nonvolatile memory module 43 suggests that writing should be performed according to the suggested order of fig. 10 when writing operations are performed on the rewritable nonvolatile memory module 43. That is, conventionally, the memory control circuit unit 42 sequentially performs the operations of writing data according to the arrangement sequence of the corresponding word string group along the first direction, until the written word line has no empty physical cells. And in the subsequent data writing operation, data is then written into the physical unit in the next word line.

For example, assume that writing starts from word line WL1, and that all of the physical cells PU 11-PU 14 of word line WL1 are blank (can be written with data). In this example, the 1 st physical unit PU11 corresponding to the 1 st String group String1 in the word line WL1 is written (e.g., the writing order is 1), then the 2 nd physical unit PU12 corresponding to the 2 nd String group String2 is written (e.g., the writing order is 2), then the 3 rd physical unit PU13 corresponding to the 3 rd String group String3 is written (e.g., the writing order is 3), and then the 4 th physical unit PU14 corresponding to the 4 th String group String4 is written (e.g., the writing order is 4). Next, since the word line WL1 does not have any empty physical cells, the physical cell in the next word line of the word line WL1 is selected for writing, for example, writing is started from the 1 st physical cell PU21 corresponding to the 1 st String group String1 in the word line WL2 (e.g., the writing order is 5), and so on.

Unlike the conventional writing sequence, the data writing method provided in the present exemplary embodiment writes data to the target physical cell in the target word line, even if the target word line has other empty physical cells arranged behind the target physical cell, the memory control circuit unit 42 first selects one or more physical cells (also referred to as another target physical cell) corresponding to the same word string group in one or more word lines (also referred to as another target word line) arranged behind the target word line to perform the subsequent data writing operation. That is, the one or more further target physical units for performing the subsequent data writing operation are one or more physical units arranged behind the target physical unit along the third direction, each of which is located in one or more word lines arranged behind the target word line along the third direction.

FIG. 11 is a diagram illustrating a write sequence of a first aspect of a physical cell according to an example embodiment of the present invention.

For example, referring to fig. 9A and 11, it is assumed that writing is performed from the word line WL1, and the physical cells PU 11-PU 14 of the word line WL1 are all blank (can be written with data). In this example, as shown in table TB11, writing is started from the 1 st physical unit PU11 corresponding to the 1 st String group String1 in the word line WL1 (e.g., the writing order is 1).

At this time, the physical cells PU12 to PU14 arranged in the word line WL1 after the physical cell PU11 are blank, and the physical cells PU21 to PU24 arranged in the word line WL2 after the word line WL1 in the third direction are blank. Then, the memory control circuit unit 42 selects the physical unit PU21 (e.g., the write sequence is 2) corresponding to the same String1 in the word line WL2 to perform the subsequent data writing operation.

At this time, the physical cells PU22 to PU24 arranged after the physical cell PU21 in the word line WL2 are blank, and the physical cells PU31 to PU34 arranged in the word line WL3 after the word line WL2 in the third direction are blank. Next, the memory control circuit unit 42 selects the blank physical unit PU12 (e.g., the writing order is 3) corresponding to the next String2 in the previous word line WL1 to perform the subsequent data writing operation. It should be noted that the memory control circuit unit 42 does not select the physical unit PU31 corresponding to the string group string1 in the word line WL3 to perform the data writing operation with the writing order of 3.

Next, similar to the process from writing order 1 to writing order 2, the memory control circuit unit 42 selects the physical unit PU22 (e.g., writing order 4) of the corresponding String group String2 in the word line WL2 to perform the subsequent data writing operation.

That is, in the writing sequence of the first aspect, the memory control circuit unit 42 selects the written word string group according to the arrangement sequence of the word string group along the first direction to write data into one or more adjacent physical units along the third direction (e.g., the physical unit PU11 and the physical unit PU21 are adjacent physical units), so that the track of the data writing sequence of the plurality of physical units in each group of word lines (e.g., the word lines WL1 and WL2 are adjacent word lines) is similar to a continuous inverted N shape.

It should be noted that in the above example, the number of entity units per group is 2, but the present invention is not limited thereto,

specifically, in another embodiment, after writing the second data, the data writing method further includes: before writing the third data subsequent to the second data in the write data, the memory control circuit unit 42 determines whether there is a jth physical unit located in the (i+2) -th word line corresponding to the blank of the jth word string group. That is, after writing the second data to the jth physical cell in the (i+1) -th word line, the memory control circuit unit 42 determines whether the (i+2) -th word line arranged after the (i+1) -th word line in the third direction has the jth physical cell corresponding to the blank of the jth word string group (the physical cell is arranged after the physical cell storing the second data in the third direction).

Then, in response to determining that there is the jth physical cell in the ith+2 word line corresponding to the blank of the jth word string group, the memory control circuit unit 42 writes the third data to the jth physical cell in the ith+2 word line corresponding to the blank of the jth word string group. That is, if it is determined that there are empty physical units corresponding to the same string group in the next word line, the memory control circuit unit 42 writes the following third data to the empty physical units in the next word line, where the physical units belong to the same string group as the previously written physical units, and are arranged after the previously written physical units along the third direction, and so on. That is, if the subsequent data writing operation is to be performed, the memory control circuit unit 42 writes a plurality of physical units belonging to the same string group in the plurality of word lines along the third direction until the physical units are all fully written.

On the other hand, in response to determining that there is no jth physical cell in the ith+2 word line corresponding to the blank of the jth word string group, the memory control circuit unit 42 writes the third data to the jth+1 physical cell in the ith word line corresponding to the jth+1 word string group. That is, if it is determined that there is no empty physical cell corresponding to the same word line group in the next word line or it is determined that there is no next word line, the memory control circuit unit 42 writes the following third data into the empty physical cell (i.e., j+1th physical cell of the i-th word line) in the first word line of the next word line group (i.e., j+1th word line). That is, if the subsequent data writing operation is to be performed, the memory control circuit unit 42 continues to write the plurality of physical units belonging to the next string group in the plurality of word lines from the next string group in the third direction when the data cannot be written to the next physical unit arranged in the third direction.

Fig. 12 is a schematic diagram showing a writing sequence of a second aspect of a physical unit according to an exemplary embodiment of the present invention.

Unlike the example of fig. 11, the number of physical units per group in the write sequence of the second aspect may be 2 or more.

For example, referring to fig. 9A and 12, assuming that the total number of word lines is 4, the memory control circuit unit 42 starts writing from the word line WL1, and the physical cells PU 11-PU 14 of the word line WL1 are blank (can be written with data). In this example, as shown in table TB12, writing is started from the 1 st physical unit PU11 corresponding to the 1 st String group String1 in the word line WL1 (e.g., the writing order is 1).

At this time, the physical cells PU12 to PU14 arranged in the word line WL1 after the physical cell PU11 are blank, and the physical cells PU21 to PU24 arranged in the word line WL2 after the word line WL1 in the third direction are blank. Then, the memory control circuit unit 42 selects the physical unit PU21 (e.g., the write sequence is 2) corresponding to the same String1 in the word line WL2 to perform the subsequent data writing operation.

At this time, the physical cells PU22 to PU24 arranged after the physical cell PU21 in the word line WL2 are blank, and the physical cells PU31 to PU34 arranged in the word line WL3 after the word line WL2 in the third direction are blank. Next, the memory control circuit unit 42 selects the physical unit PU31 (e.g., the writing order is 3) corresponding to the same String1 in the word line WL3 to perform the subsequent data writing operation. In this way, the memory control circuit unit 42 selects the physical unit PU41 (e.g., the write sequence is 4) corresponding to the same String1 in the next word line WL4 to perform the subsequent data writing operation.

In this embodiment, when the number of written physical units corresponding to the same string set reaches a predetermined value (e.g., 4), the memory control circuit unit 42 selects the physical unit of the next string set to perform the subsequent data writing operation.

That is, as shown in the table TB12, similar to the process from the writing order 1 to the writing order 4, the memory control circuit unit 42 sequentially selects the plurality of entity units PU 12-PU 42 belonging to the next String set String2 (e.g. the writing order is 5-8) to perform the subsequent data writing operation.

That is, in the writing sequence of the second aspect, the memory control circuit unit 42 selects the written string group according to the arrangement sequence of the string group along the first direction, and sequentially writes data to the plurality of entity units of the same string group according to the sequence of the third direction (for example, the entity units PU11 to PU41 are the plurality of entity units corresponding to the same string group string 1) for the plurality of entity units of the same string group, so that the track of the data writing sequence of the second aspect is similar to be continuous inverted N-shapes, and the size of each inverted N-shape is greater than or equal to the size of the N-shape of the first aspect.

In the writing sequence of the second aspect, steps S820 to S840 include writing the first data and the second data to a plurality of first physical units corresponding to the j-th word string group in a plurality of first word lines arranged along the third direction, respectively. When the written plurality of first entity units reach the predetermined value, the memory control circuit unit 42 writes third data, which is subsequent to the second data, in the write data to a plurality of second entity units corresponding to the j+1th word string group, which are respectively located in the plurality of first word lines arranged along the third direction, wherein the third entity units arranged subsequent to the plurality of first entity units along the third direction may be blank.

In one embodiment, the predetermined value of the total number of the plurality of first entity units is determined according to a ratio of data amounts required for generating parity data. In more detail, the memory control circuit unit 42 generates parity data corresponding to the first data and the second data according to the written first data and the second data, wherein a ratio between sizes of the first data and the second data and the generated parity data is the data amount ratio, and the total number of the plurality of first entity units is used for storing the first data and the second data. For example, assume that each entity unit is 16KB and the size of the first data is 16KB, the size of the second data is 12KB, and the size of the parity data generated accordingly is 4KB. In this example, the data amount ratio is (16+12): 4, namely 7:1. the predetermined value of the total number of the plurality of physical units used to store the first data and the second data is set to 2, such that the total size of each group of physical units is sufficient to store the first data, the second data and the parity data (e.g., physical units PU11, PU21 of fig. 15A, which store the write data and parity data PRT1 according to a data volume ratio of 7:1). A detailed example will be described later with reference to fig. 14 to 16.

Referring to fig. 15B, in another embodiment, the parity data corresponding to the data amount ratio of 7:1 is generated, for example, by using 7 physical units of data to generate parity data of one physical unit. For example, as shown in table TB153 in fig. 15B, the memory control circuit unit 42 may generate parity data PRT1 from the data stored in the entity units PU11 to PU71 of the corresponding String group String1, which is stored in the entity unit PU81 of the String group String 1.

It should be noted that an extreme example of the write sequence of the second aspect is that the predetermined value of the total number of the plurality of physical units corresponding to the same string group in one round of data write operation is the total number of all word lines. That is, when all the physical units corresponding to one word string group in all the word lines have been written with data, the memory control circuit unit 42 selects the physical unit corresponding to the next word string group from the first word line to sequentially perform the subsequent data writing operation.

That is, in response to determining that there are one or more third entity units of the space corresponding to the jth word string group arranged after the plurality of first entity units in the third direction, the memory control circuit unit 42 writes the third data to the one or more third entity units of the space, wherein the one or more third entity units of the space are respectively located at one or more second word lines arranged after the plurality of first word lines in the third direction; and in response to determining that there are no one or more third entity units arranged in the third direction that correspond to the blank of the jth word string group after the plurality of first entity units, the memory control circuit unit 42 writes the third data to a plurality of second entity units respectively located in the j+1th word string group within the plurality of first word lines arranged in the third direction.

In one embodiment, after writing the plurality of entity units corresponding to a group of strings (e.g., a j-th string group), the memory control circuit unit 42 backs up the data stored in all entity units corresponding to the j-th string group within the P word lines and the parity data corresponding to the data before writing the subsequent third data to the plurality of entity units corresponding to the next string group (e.g., a j+1th string group). For example, the data and the parity data corresponding to the data may be backed up into other physical erasure cells. After backing up the data corresponding to the jth word string group and/or parity data corresponding to the data, the memory control circuit unit 42 writes the third data to a plurality of entity units corresponding to the jth+1th word string group respectively located in the plurality of word lines arranged along the third direction. Therefore, the problem of data loss caused by the error of the written data due to the writing sequence of the first mode or the second mode different from the traditional writing sequence can be avoided.

Fig. 13 is a schematic diagram showing a third state-like writing sequence of a physical cell according to an exemplary embodiment of the present invention.

Referring to fig. 13, in another embodiment, as shown in the table TB13, according to the third state-like writing sequence, the track of the writing sequence of the continuous data writing operation performed by the memory control circuit unit 42 on the plurality of physical units in each group of word lines can be regarded as a plurality of parallel zigzag tracks (e.g. the writing sequence 1-4 and the writing sequence 5-8 corresponding to the group of word lines WL1 and WL 2). In short, after each writing two physical units corresponding to two word string groups in one word line, the memory control circuit unit 42 selects two physical units corresponding to the same two word string groups in the next word line for writing. It should be noted that, in this embodiment, the width of each zigzag may be preset according to the requirement. It should be noted, however, that the width of each zig-zag will be less than the total number of groups of strings.

Fig. 14 is a schematic diagram illustrating the generation of parity data according to the prior art.

Referring to fig. 14, it is assumed that each entity unit can store data of 4 basic unit sizes, numbers (e.g., numbers 1-5) in the table TB141 are used to represent the writing order, and numbers (e.g., numbers "1" to "4" and each tag corresponds to data of one basic unit size) in the table TB142 are used to represent the numbers of the tags. The tag number may be used to indicate the order in which the physical cells are arranged in the word line to which they belong. Further, it is further assumed that the data amount ratio for generating parity data is 7:1. The dot squares represent one basic unit within a physical unit to which data is written, and the blank squares represent basic units which have not been written. Each basic unit is, for example, one or more memory cells.

In this example, in order to generate the data that can protect the physical unit PU11 stored in the word line WL1, the memory control circuit unit 42 waits for the data to be written into the physical unit PU21 belonging to the same tag number in the next word line WL2, and then generates the parity data PRT1 by using the data written into the physical units PU11 and PU21 (the ratio of the size of the data written into the physical units PU11 and PU21 to the size of the corresponding parity data PRT1 is 7:1).

It should be noted that in generating parity data, the memory control circuit unit 42 may copy the written data into the buffer memory 65 to accelerate the operation of generating parity data. Or the data to be written is temporarily stored in the buffer memory 65, and after parity data is generated, the data to be written is written into the rewritable nonvolatile memory module 43 together with the parity data.

That is, if the conventional write sequence is adopted, the memory control circuit unit 42 consumes additional resources in generating parity data (e.g., generating parity data PRT 1), such as waiting for additional time (e.g., waiting for the data write operation of the physical units PU12, PU13, PU14 to be completed) and consuming additional space of the buffer memory 65 (e.g., space for recording the data stored in the physical units PU12, PU13, PU 14).

Fig. 15A is a schematic diagram illustrating the generation of parity data according to an example embodiment of the present invention.

Referring to fig. 15A, unlike the example of fig. 14, the data writing method of fig. 15A adopts the writing sequence of the first aspect as shown in the table TB151 (see fig. 11).

In this example, to generate the data (whose tag number is "1") that can protect the physical unit PU11 stored in the word line WL1, the memory control circuit unit 42 can generate the parity data PRT1 (the ratio of the size of the data written to the physical unit PU11, PU21 and the size of the corresponding parity data PRT1 is 7:1) directly based on the data in the physical unit PU11 and the data written to the physical unit PU21 in the next word line WL2 (belonging to the same tag number of "1").

That is, if the write sequence of the first aspect of the present invention is adopted, the memory control circuit unit 42 does not consume additional resources in the process of generating parity data (e.g., generating the parity data PRT 1) (see the table TB 152). For example, the memory control circuit unit 42 does not need to wait for additional time (because it does not need to wait for the data writing operation of the entity units PU12, PU13, PU 14) and does not need to consume the space of the additional buffer memory 65 (because it does not need to record the data stored in the entity units PU12, PU13, PU 14), thereby saving the space of the buffer memory 65. In this way, the overall operation efficiency of the memory control circuit unit 42 or the memory storage device 10 is improved. In this example, the space saved is 12/20 (i.e., 3/5) of the space used corresponding to the conventional practice.

It should be noted that the benefits of the data writing method provided by the present invention increase as the number of word string groups per word line increases, and also as the ratio of the data amount used to generate parity data increases.

Fig. 16 is a schematic diagram illustrating the generation of parity data according to another exemplary embodiment of the present invention.

Referring to fig. 16, as shown in a table TB161, the data writing method in fig. 16 adopts a writing sequence of a first aspect (see fig. 11). Unlike the example of fig. 15A, the data amount ratio for generating parity data is 11:1.

In this example, to generate the data (whose tag number is "1") that can protect the physical unit PU11 stored in the word line WL1, the memory control circuit unit 42 can generate the parity data PRT1 (the ratio of the size of the data written to the physical unit PU11, PU21, PU31 to the size of the corresponding parity data PRT1 is 11:1) directly based on the data in the physical unit PU11 and the data written to the physical units PU21, PU31 in the word lines WL2, WL3 (belonging to the same tag number of "1").

However, if the conventional data writing sequence is used in this example, the parity data PRT1 corresponding to the data of the tag label "1" may not be generated until the data is written to the entity unit PU 31. That is, in the conventional method, the memory control circuit unit 42 consumes more additional resources than the example of fig. 16, such as waiting more additional time (e.g., waiting for the data writing operation of the entity units PU12, PU13, PU14, PU22, PU23, PU24 to be completed) and consuming more additional buffer memory (e.g., recording the data stored in the entity units PU12, PU13, PU14, PU22, PU23, PU 24) in generating the parity data (e.g., generating the parity data PRT 1). In the example corresponding to FIG. 16, as shown in Table TB162, the space saved is 24/36 (i.e., 2/3) of the space used corresponding to the conventional practice.

Similarly, in another example, assume that the total number of word string groups per word line is greater, e.g., 8. In the conventional method, the memory control circuit unit 42 consumes more additional resources than the data writing method provided by the present invention, such as waiting more additional time (because of waiting for more physical units to write data to be completed) and consuming more additional buffer memory (because of the additional space required to record the data stored in other physical units with different tag numbers).

In summary, the exemplary embodiments of the present invention can use the provided data writing sequences of different aspects to write the plurality of physical units corresponding to the same word string group in the plurality of word lines along the arrangement direction of the plurality of word lines, so as to save the system resources required in the process of generating the parity data, and further improve the working efficiency of the memory storage device 10 and the memory control circuit 42. Meanwhile, the problem of write interference caused by a write sequence different from the traditional write sequence or the problem of data loss caused by the error of written data can be avoided.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (39)

1. A data writing method for a rewritable nonvolatile memory, wherein the rewritable nonvolatile memory module includes a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines constitute a plurality of memory cells for storing data, wherein the rewritable nonvolatile memory module includes P word lines each including M segments corresponding to M word string groups, wherein each segment of the M segments and the intersecting N bit lines constitute N memory cells corresponding to the same word string group, and the N memory cells constitute one physical cell such that MxN memory cells of each word line constitute M physical cells corresponding to the M word string groups, the method comprising:

Obtaining a write instruction, wherein the write instruction is used for indicating writing of write data to the rewritable nonvolatile memory module;

according to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in the P word lines;

after writing the first data, selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units which are arranged behind the target physical units are arranged in the target word line; and

and writing second data which is subsequent to the first data in the written data into the one or more selected further target entity units.

2. The data writing method of claim 1, wherein the step of writing the first data of the write data to the target physical cell of the target one of the P word lines comprises:

writing the first data into a jth entity unit corresponding to a jth word string group in an ith word line, wherein the ith word line is the target word line, and the jth entity unit is the target entity unit,

Wherein writing the second data to the one or more further target physical units respectively located within the one or more further target word lines comprises:

writing the second data into a j-th entity unit corresponding to the j-th word string group in an i+1th word line, wherein the i+1th word line is the further target word line, and the j-th entity unit in the i+1th word line is the further target entity unit.

3. The data writing method according to claim 2, wherein after writing the second data, the method further comprises:

writing third data which is connected with the second data in the written data into a j+1th entity unit corresponding to a j+1th word string group in the i-th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is not written with data; and

and writing fourth data which is connected with the third data in the written data into a j+1th entity unit corresponding to the j+1th word string group in the i+1th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is blank.

4. The data writing method according to claim 2, wherein after writing the second data, the method further comprises:

before writing third data which is connected after the second data in the written data, judging whether a (j) th entity unit which is positioned in the (i+2) th word line and corresponds to the (j) th word string group is present or not;

writing the third data to a jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group in response to determining that there is the jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group; and

and in response to determining that the j-th entity unit corresponding to the blank of the j-th word string group in the i+2-th word line does not exist, writing the third data into the j+1-th entity unit corresponding to the j+1-th word string group in the i-th word line.

5. The method of claim 1, wherein the plurality of word lines and the plurality of bit lines intersecting the plurality of word lines form a three-dimensional structure, wherein the plurality of bit lines are grouped into the M word line groups that are sequentially arranged along a first direction, the N bit lines of each word line group are sequentially arranged along a second direction and extend along a third direction, wherein the P word lines that are corresponding to the same word line group are sequentially arranged along the third direction and extend along the second direction, wherein the P word lines are sequentially arranged along the third direction, wherein the N bit lines of each word line group together intersect into P sections that are corresponding to the P word lines that are each belonging to the P word line groups to form the MxN memory cells within each word line, and further form the M physical memory cells within each word line that are sequentially arranged along the first direction, wherein the M physical memory cells within each word line group are sequentially arranged along the third direction, and wherein the M physical memory cells within each word line group are perpendicular to each other.

6. The data writing method of claim 5, wherein the step of writing the first data of the write data to the target physical cell of the target word line of the P word lines and the step of writing the second data to the one or more further target physical cells respectively located within the one or more further target word lines comprises:

and writing the first data and the second data into a plurality of first entity units corresponding to the j-th word string group in a plurality of first word lines arranged along the third direction respectively.

7. The data writing method of claim 6, wherein a total number of the plurality of first entity units is determined according to a ratio of data amounts required to generate parity data, the method further comprising:

generating parity data corresponding to the first data and the second data according to the written first data and second data,

wherein a ratio between the sizes of the first data and the second data and the size of the parity data generated is the data amount ratio, and the total number of the plurality of first entity units is used to store the first data and the second data.

8. The data writing method according to claim 6, wherein after writing the second data, the method further comprises:

and writing third data which is connected with the second data in the written data into a plurality of second entity units which are respectively positioned in the first word lines arranged along the third direction and correspond to the j+1th word string group, wherein the third entity units which are arranged behind the first entity units along the third direction are blank.

9. The data writing method according to claim 6, wherein after writing the second data, the method further comprises:

before writing third data which is subsequent to the second data in the written data, judging whether one or more third entity units which are arranged behind the first entity units along the third direction and correspond to the blank of the j-th string group exist or not;

writing the third data to the blank one or more third entity units in response to determining that the blank one or more third entity units corresponding to the jth word string group arranged behind the first entity units in the third direction exist, wherein the blank one or more third entity units are respectively positioned on one or more second word lines arranged behind the first word lines in the third direction; and

And in response to determining that one or more third entity units corresponding to the blank of the jth word string group arranged behind the first entity units along the third direction do not exist, writing the third data into a plurality of second entity units corresponding to the (j+1) th word string group in the first word lines arranged along the third direction.

10. The data writing method according to claim 9, characterized in that the method further comprises:

in response to determining that there are no one or more third entity units in the third direction that are arranged after the plurality of first entity units and that correspond to the j-th string group, backing up data stored in all entity units corresponding to the j-th string group within the P word lines and parity data corresponding to the data before writing the third data to the plurality of second entity units corresponding to the j+1th string group; and

after the data corresponding to the jth word string group and the parity data corresponding to the data are backed up, the third data are written into the plurality of second entity units corresponding to the (j+1) th word string group respectively located in the plurality of first word lines arranged along the third direction.

11. A data writing method for a rewritable non-volatile memory, wherein the rewritable non-volatile memory module comprises a plurality of physical erase units, wherein each physical erase unit comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines with the plurality of bit lines form a plurality of memory cells for storing data, wherein the rewritable non-volatile memory module comprises P word lines, each word line comprises M segments corresponding to M word string groups, wherein each segment of the M segments and the N bit lines intersecting form N memory cells corresponding to the same word string group, and the N memory cells form one physical cell, such that MxN memory cells of each word line form M physical cells corresponding to the M word string groups, the method comprising:

generating and transmitting a first write command sequence via a memory management circuit to instruct writing of first write data to a target physical erase unit of the plurality of physical erase units;

generating and sending, via the memory management circuit, a second write instruction sequence to instruct writing of second write data to the target physical erase unit;

Writing the first writing data to a first entity address in the target entity erasing unit through a memory interface according to the first writing instruction sequence; and

writing the second write data to a second physical address in the target physical erase unit according to the second write command sequence via the memory interface,

wherein the first word line to which the first physical address belongs is different from the second word line to which the second physical address belongs,

wherein when second write data is written to the second physical address in the target physical erase cell, there are blank one or more physical addresses arranged after the first physical address in the first word line,

wherein no write command sequence is executed to indicate writing of data to the target physical erase unit during a time interval between execution of the first write command sequence and execution of the second write command sequence.

12. The method of claim 11, wherein the memory management circuit records a physical address list, wherein the data of the plurality of columns of the physical address list includes a plurality of physical address numbers corresponding to a plurality of physical addresses, a plurality of word line identifiers corresponding to the plurality of physical address numbers, and a plurality of word string group identifiers corresponding to the plurality of physical address numbers, respectively, the method further comprising:

Generating, via the memory management circuit, the first write instruction sequence according to a first physical address number of the plurality of physical address numbers to instruct writing of the first write data to the first physical address corresponding to the first physical address number, wherein the first physical address is a first physical unit of a first string group within a first word line corresponding to the first physical address number; and

generating, via the memory management circuit, the second sequence of write instructions according to a second physical address number of the plurality of physical address numbers to instruct writing of the second write data to the second physical address corresponding to the second physical address number, wherein the second physical address is a second physical unit of a second string group within a second word line corresponding to the second physical address number,

wherein the first physical address number and the second physical address number are not two consecutive physical address numbers in the physical address list.

13. The method of claim 12, wherein the plurality of physical addresses corresponding to the plurality of physical address numbers in the physical address list are grouped into a plurality of groups of physical addresses according to a sequence of the corresponding plurality of word line identifiers, wherein the plurality of physical addresses in each group of physical addresses are arranged according to the sequence of the corresponding plurality of word string groups, and wherein the plurality of physical address numbers are arranged from small to large.

14. A memory storage device, comprising:

the connection interface unit is used for being electrically connected to the host system;

a rewritable nonvolatile memory module comprising a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines with the plurality of bit lines form a plurality of memory cells for storing data, wherein P word lines are included, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersecting N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical cell, such that MxN memory cells of each word line form M physical cells corresponding to the M word string groups; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

obtaining a write instruction, wherein the write instruction is used for indicating writing of write data to the rewritable nonvolatile memory module;

According to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in the P word lines;

after writing the first data, selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units which are arranged behind the target physical units are arranged in the target word line; and

and writing second data which is subsequent to the first data in the written data into the one or more selected further target entity units.

15. The memory storage device of claim 14, wherein the step of writing the first one of the write data to the target physical cell of the target one of the P word lines comprises:

writing the first data into a jth entity unit corresponding to a jth word string group in an ith word line, wherein the ith word line is the target word line, and the jth entity unit is the target entity unit,

wherein writing the second data to the one or more further target physical units respectively located within the one or more further target word lines comprises:

Writing the second data into a j-th entity unit corresponding to the j-th word string group in an i+1th word line, wherein the i+1th word line is the further target word line, and the j-th entity unit in the i+1th word line is the further target entity unit.

16. The memory storage device of claim 15, wherein after writing the second data, the memory control circuit unit is further configured to:

writing third data which is connected with the second data in the written data into a j+1th entity unit corresponding to a j+1th word string group in the i-th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is not written with data; and

and writing fourth data which is connected with the third data in the written data into a j+1th entity unit corresponding to the j+1th word string group in the i+1th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is blank.

17. The memory storage device of claim 15, wherein after writing the second data, the memory control circuit unit is further configured to:

Before writing third data which is connected after the second data in the written data, judging whether a (j) th entity unit which is positioned in the (i+2) th word line and corresponds to the (j) th word string group is present or not;

writing the third data to a jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group in response to determining that there is the jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group; and

and in response to determining that the j-th entity unit corresponding to the blank of the j-th word string group in the i+2-th word line does not exist, writing the third data into the j+1-th entity unit corresponding to the j+1-th word string group in the i-th word line.

18. The memory storage device of claim 14, wherein the plurality of word lines and the plurality of bit lines intersecting the plurality of word lines form a three-dimensional structure, wherein the plurality of bit lines are grouped into the M word line groups that are sequentially arranged along a first direction, the N bit lines of each word line group are sequentially arranged along a second direction and extend along a third direction, wherein the P word lines that are corresponding to the same word line group are sequentially arranged along the third direction and extend along the second direction, wherein the P word lines are sequentially arranged along the third direction, wherein the N bit lines of each word line group together intersect to P sections that are corresponding to the P word lines that are each belonging to the same word line group to form the M physical groups that are sequentially arranged along the third direction within each word line, wherein the M physical groups that are corresponding to the M physical groups that are sequentially arranged along the third direction within each word line, and the third direction are perpendicular to each other.

19. The memory storage device of claim 18, wherein the step of writing the first data of the write data to the target physical cell of the target word line of the P word lines and the step of writing the second data to the one or more further target physical cells respectively located within the one or more further target word lines comprises:

and writing the first data and the second data into a plurality of first entity units corresponding to the j-th word string group in a plurality of first word lines arranged along the third direction respectively.

20. The memory storage device of claim 19, wherein the total number of the plurality of first entity units is determined according to a ratio of data amounts required to generate parity data, the memory control circuit unit further configured to:

generating parity data corresponding to the first data and the second data according to the written first data and second data,

wherein a ratio between the sizes of the first data and the second data and the size of the parity data generated is the data amount ratio, and the total number of the plurality of first entity units is used to store the first data and the second data.

21. The memory storage device of claim 19, wherein after writing the second data, the memory control circuit unit is further configured to:

and writing third data which is connected with the second data in the written data into a plurality of second entity units which are respectively positioned in the first word lines arranged along the third direction and correspond to the j+1th word string group, wherein the third entity units which are arranged behind the first entity units along the third direction are blank.

22. The memory storage device of claim 19, wherein after writing the second data, the memory control circuit unit is further configured to:

before writing third data which is subsequent to the second data in the written data, judging whether one or more third entity units which are arranged behind the first entity units along the third direction and correspond to the blank of the j-th string group exist or not;

writing the third data to the blank one or more third entity units in response to determining that the blank one or more third entity units corresponding to the jth word string group arranged behind the first entity units in the third direction exist, wherein the blank one or more third entity units are respectively positioned on one or more second word lines arranged behind the first word lines in the third direction; and

And in response to determining that one or more third entity units corresponding to the blank of the jth word string group arranged behind the first entity units along the third direction do not exist, writing the third data into a plurality of second entity units corresponding to the (j+1) th word string group in the first word lines arranged along the third direction.

23. The memory storage device of claim 22, wherein the memory control circuit unit is further configured to:

in response to determining that there are no one or more third entity units in the third direction that are arranged after the plurality of first entity units and that correspond to the j-th string group, backing up data stored in all entity units corresponding to the j-th string group within the P word lines and parity data corresponding to the data before writing the third data to the plurality of second entity units corresponding to the j+1th string group; and

after the data corresponding to the jth word string group and the parity data corresponding to the data are backed up, the third data are written into the plurality of second entity units corresponding to the (j+1) th word string group respectively located in the plurality of first word lines arranged along the third direction.

24. A memory storage device, comprising:

the connection interface unit is used for being electrically connected to the host system;

a rewritable nonvolatile memory module comprising a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines with the plurality of bit lines form a plurality of memory cells for storing data, wherein P word lines are included, each word line comprises M sections corresponding to M word string groups, wherein each section of the M sections and the intersecting N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical cell, such that MxN memory cells of each word line form M physical cells corresponding to the M word string groups; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory management circuitry of the memory control circuit unit is configured to generate and send a first sequence of write instructions to instruct writing of first write data to a target physical erase unit of the plurality of physical erase units,

Wherein the memory management circuit is further configured to generate and send a second sequence of write instructions to instruct writing of second write data to the target physical erase unit,

wherein the memory interface of the memory control circuit unit is used for writing the first write data to a first physical address in the target physical erasing unit according to the first write instruction sequence,

wherein the memory interface is further configured to write the second write data to a second physical address in the target physical erase unit according to the second write command sequence,

wherein the first word line to which the first physical address belongs is different from the second word line to which the second physical address belongs,

wherein when second write data is written to the second physical address in the target physical erase cell, there are blank one or more physical addresses arranged after the first physical address in the first word line,

wherein no write command sequence is executed to indicate writing of data to the target physical erase unit during a time interval between execution of the first write command sequence and execution of the second write command sequence.

25. The memory storage device of claim 24, wherein the memory management circuit records a list of physical addresses, wherein the data of the plurality of columns of the list of physical addresses includes a plurality of physical address numbers corresponding to a plurality of physical addresses, a plurality of word line identifiers corresponding to the plurality of physical address numbers, and a plurality of string group identifiers corresponding to the plurality of physical address numbers, respectively, wherein

The memory management circuit generates the first write instruction sequence according to a first physical address number of the plurality of physical address numbers to indicate the first write data to be written to the first physical address corresponding to the first physical address number, wherein the first physical address is a first physical unit of a first string group in a first word line corresponding to the first physical address number,

wherein the memory management circuit generates the second write instruction sequence according to a second physical address number of the plurality of physical address numbers to instruct to write the second write data to the second physical address corresponding to the second physical address number, wherein the second physical address is a second physical unit of a second string group in a second word line corresponding to the second physical address number,

Wherein the first physical address number and the second physical address number are not two consecutive physical address numbers in the physical address list.

26. The memory storage device of claim 25, wherein the plurality of physical addresses corresponding to the plurality of physical address numbers in the physical address list are grouped into a plurality of groups of physical addresses according to a sequence of the corresponding plurality of word line identifiers, wherein the plurality of physical addresses in each group of physical addresses are arranged according to the sequence of the corresponding plurality of word string groups, and wherein the plurality of physical address numbers are arranged from small to large.

27. A memory control circuit unit, comprising:

the host interface is used for being electrically connected to a host system;

the memory interface is used for being electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, each word line comprises M sections corresponding to M word string groups, each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical units corresponding to the M word string groups; and

A memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is to:

obtaining a write instruction, wherein the write instruction is used for indicating writing of write data to the rewritable nonvolatile memory module;

according to the writing instruction, writing first data in the writing data into a target entity unit of a target word line in the P word lines;

after writing the first data, selecting one or more further target physical units respectively located in one or more further target word lines when one or more physical units which are arranged behind the target physical units are arranged in the target word line; and

and writing second data which is subsequent to the first data in the written data into the one or more selected further target entity units.

28. The memory control circuit unit of claim 27, wherein the step of writing the first one of the write data to the target physical cell of the target one of the P word lines comprises:

writing the first data into a jth entity unit corresponding to a jth word string group in an ith word line, wherein the ith word line is the target word line, and the jth entity unit is the target entity unit,

Wherein writing the second data to the one or more further target physical units respectively located within the one or more further target word lines comprises:

writing the second data into a j-th entity unit corresponding to the j-th word string group in an i+1th word line, wherein the i+1th word line is the further target word line, and the j-th entity unit in the i+1th word line is the further target entity unit.

29. The memory control circuit unit of claim 28, wherein after writing the second data, the memory management circuit is further configured to:

writing third data which is connected with the second data in the written data into a j+1th entity unit corresponding to a j+1th word string group in the i-th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is not written with data; and

and writing fourth data which is connected with the third data in the written data into a j+1th entity unit corresponding to the j+1th word string group in the i+1th word line, wherein the j entity unit corresponding to the j-th word string group in the i+2th word line is blank.

30. The memory control circuit unit of claim 28, wherein after writing the second data, the memory management circuit is further configured to:

before writing third data which is connected after the second data in the written data, judging whether a (j) th entity unit which is positioned in the (i+2) th word line and corresponds to the (j) th word string group is present or not;

writing the third data to a jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group in response to determining that there is the jth physical cell in the (i+2) -th word line corresponding to the blank of the jth word string group; and

and in response to determining that the j-th entity unit corresponding to the blank of the j-th word string group in the i+2-th word line does not exist, writing the third data into the j+1-th entity unit corresponding to the j+1-th word string group in the i-th word line.

31. The memory control circuit unit of claim 27, wherein the plurality of word lines and the plurality of bit lines intersecting the plurality of word lines form a three-dimensional structure, wherein the plurality of bit lines are grouped into the M word line groups that are sequentially arranged along a first direction, the N bit lines of each word line group are sequentially arranged along a second direction and extend along a third direction, wherein the P word lines that are corresponding to the same word line group are sequentially arranged along the third direction and extend along the second direction, wherein the P word lines are sequentially arranged along the third direction, wherein the N bit lines of each word line group together intersect into P sections that are corresponding to the P word lines, respectively, to form the MxN memory cells within each word line, to form the M physical memory cells within each word line that are corresponding to the M physical cells within each word line that are sequentially arranged along the first direction, wherein the M physical memory cells within each word line group are sequentially intersected into the M physical cells within each word line group, wherein the N bit lines are associated with each other, and the M physical cells within each word line group are perpendicular to each other.

32. The memory control circuit unit of claim 31, wherein the step of writing the first data of the write data to the target physical cell of the target one of the P word lines and the step of writing the second data to the one or more further target physical cells respectively located within the one or more further target word lines comprises:

and writing the first data and the second data into a plurality of first entity units corresponding to the j-th word string group in a plurality of first word lines arranged along the third direction respectively.

33. The memory control circuit unit of claim 32, wherein the total number of the plurality of first entity units is determined based on a ratio of data amounts required to generate parity data, wherein the memory management circuit is further configured to:

generating parity data corresponding to the first data and the second data according to the written first data and second data,

wherein a ratio between the sizes of the first data and the second data and the size of the parity data generated is the data amount ratio, and the total number of the plurality of first entity units is used to store the first data and the second data.

34. The memory control circuit unit of claim 32, wherein after writing the second data, the memory management circuit is further configured to:

and writing third data which is connected with the second data in the written data into a plurality of second entity units which are respectively positioned in the first word lines arranged along the third direction and correspond to the j+1th word string group, wherein the third entity units which are arranged behind the first entity units along the third direction are blank.

35. The memory control circuit unit of claim 32, wherein after writing the second data, the memory management circuit is further configured to:

before writing third data which is subsequent to the second data in the written data, judging whether one or more third entity units which are arranged behind the first entity units along the third direction and correspond to the blank of the j-th string group exist or not;

writing the third data to the blank one or more third entity units in response to determining that the blank one or more third entity units corresponding to the jth word string group arranged behind the first entity units in the third direction exist, wherein the blank one or more third entity units are respectively positioned on one or more second word lines arranged behind the first word lines in the third direction; and

And in response to determining that one or more third entity units corresponding to the blank of the jth word string group arranged behind the first entity units along the third direction do not exist, writing the third data into a plurality of second entity units corresponding to the (j+1) th word string group in the first word lines arranged along the third direction.

36. The memory control circuit unit of claim 35, wherein the memory management circuit is further configured to:

in response to determining that there are no one or more third entity units in the third direction that are arranged after the plurality of first entity units and that correspond to the j-th string group, backing up data stored in all entity units corresponding to the j-th string group within the P word lines and parity data corresponding to the data before writing the third data to the plurality of second entity units corresponding to the j+1th string group; and

after the data corresponding to the jth word string group and the parity data corresponding to the data are backed up, the third data are written into the plurality of second entity units corresponding to the (j+1) th word string group respectively located in the plurality of first word lines arranged along the third direction.

37. A memory control circuit unit, comprising:

the host interface is used for being electrically connected to a host system;

the memory interface is used for being electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines, wherein intersections of the plurality of word lines and the plurality of bit lines form a plurality of memory cells for storing data, each word line comprises M sections corresponding to M word string groups, each section of the M sections and the intersected N bit lines form N memory cells corresponding to the same word string group, and the N memory cells form one physical unit, so that MxN memory cells of each word line form M physical units corresponding to the M word string groups; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is configured to generate and send a first sequence of write instructions to instruct writing of first write data to a target physical erase unit of the plurality of physical erase units,

Wherein the memory management circuit is further configured to generate and send a second sequence of write instructions to instruct writing of second write data to the target physical erase unit,

wherein the memory interface is used for writing the first writing data to a first entity address in the target entity erasing unit according to the first writing instruction sequence,

wherein the memory interface is further configured to write the second write data to a second physical address in the target physical erase unit according to the second write command sequence,

wherein the first word line to which the first physical address belongs is different from the second word line to which the second physical address belongs,

wherein when second write data is written to the second physical address in the target physical erase cell, there are blank one or more physical addresses arranged after the first physical address in the first word line,

wherein no write command sequence is executed to indicate writing of data to the target physical erase unit during a time interval between execution of the first write command sequence and execution of the second write command sequence.

38. The memory control circuit unit of claim 37, wherein the memory management circuit records a list of physical addresses, wherein the data of the plurality of columns of the list of physical addresses includes a plurality of physical address numbers corresponding to a plurality of physical addresses, a plurality of word line identifiers corresponding to the plurality of physical address numbers, and a plurality of string group identifiers corresponding to the plurality of physical address numbers, respectively, wherein

The memory management circuit generates the first write instruction sequence according to a first physical address number of the plurality of physical address numbers to indicate the first write data to be written to the first physical address corresponding to the first physical address number, wherein the first physical address is a first physical unit of a first string group in a first word line corresponding to the first physical address number,

wherein the memory management circuit generates the second write instruction sequence according to a second physical address number of the plurality of physical address numbers to instruct to write the second write data to the second physical address corresponding to the second physical address number, wherein the second physical address is a second physical unit of a second string group in a second word line corresponding to the second physical address number,

Wherein the first physical address number and the second physical address number are not two consecutive physical address numbers in the physical address list.

39. The memory control circuit unit of claim 38, wherein the plurality of physical addresses corresponding to the plurality of physical address numbers in the physical address list are grouped into a plurality of groups of physical addresses according to a sequence of the corresponding plurality of word line identifiers, wherein the plurality of physical addresses in each group of physical addresses are arranged according to the sequence of the corresponding plurality of word string groups, and wherein the plurality of physical address numbers are arranged from small to large.