CN117762214A - Deformation node based on domestic Feiteng multipath processor - Google Patents

Abstract

The invention belongs to the technical field of processors, and particularly discloses a deformation node based on a domestic Feiteng multipath processor. The invention combines the domestic multi-processor with the whole scorpion cabinet structure, optimizes the whole scorpion cabinet structure, simultaneously applies the domestic multi-processor to the whole scorpion cabinet server, and breaks monopoly of the X86-frame multi-processor in the frame. Through the design of the deformed node, the domestic cloud S2500 multipath processor is not only applied to the high-performance computing node, but also can be matched with the expansion module to realize diversified application nodes such as the high-performance storage node and the like, thereby providing a hardware foundation for the application of the subsequent domestic whole cabinet in various task environments.

Description

Deformation node based on domestic Feiteng multipath processor

Technical Field

The invention relates to the technical field of processors, in particular to a deformed node based on a domestic Feiteng multipath processor.

Background

Along with the acceleration of the domestic new infrastructure, the method provides diversified computing power support for machine learning, video recognition, image recognition, language recognition and other scenes, and can be widely applied to the acceleration of the domestic data centers in the related fields of smart cities, smart traffic, smart energy sources, smart finance and the like.

Under the background, feiteng pushes out a brand new Tengyun S2500 multipath chip, and the domestic high-end multipath chip layout is supplemented. Based on the whole rack server architecture of scorpion, the modified (including calculation, storage and isomerization) node is developed and designed by applying the Tengyun S2500 multichannel chips.

At present, computing nodes, storage nodes and special custom nodes (such as GPU acceleration and the like) in a whole cabinet server based on a whole scorpion cabinet architecture are designed independently, so that the research and development cost is high, and the whole scorpion cabinet server is not reusable, such as: computing nodes typically have two designs, 1U1N and 1U 2N; the storage node is designed for 1U 1N; GPU nodes and the like are specially customized and have no unified specification.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the invention and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to solve the technical problems in the background technology, and provides a deformed node based on a domestic Feiteng multipath processor.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

the deformed node based on the domestic Feiteng multipath processor comprises a core computing module and an expansion module, wherein the computing node, a storage node and a special node are realized through different combination modes of the core computing module and the expansion module;

the core computing module adopts a double-path design and is composed of two cloud S2500 multipath processors, and a single processor integrates 64 ARM v8 instruction set compatible processor cores FTC663, 8 DDR4-3200 memory controllers, a 17-lane PCIE bus, a 16-lane direct communication path and supports 2, 4 and 8-path CPU interconnection;

the expansion module comprises a PCIE x16 SLOT1 expansion unit, a PCIE x16 SLOT2 expansion unit and a PCIE x8SLOT expansion unit.

The technical scheme is further defined in the invention, wherein the memory controller of the core computing module is connected with 16 DDR4 memory strips; the CPU2 of the processor is provided with a primary 1-path PCIE x1 interface, the PCIE x1 interface is connected into the BMC, and the PCIE x1 interface is used for expanding a management network port and a VGA interface of the BMC to realize the resource management and control functions of the nodes; the processor CPU1 is connected to the PCIE x16 SLOT1 SLOT at the board end by a primary 16Lane PCIE Gen3 bus, and is used for connecting with an expansion module; the CPU2 native 16Lane PCIE Gen3 bus is accessed to a PCIE Bridge chip, and a 3-path PCIE x8 interface, a 1-path PCIE x2 interface and a 1-path PCIE x1 interface are expanded.

The following is a further defined technical solution of the present invention, where the PCIE x16 SLOT1 expansion unit uses PCIE x16 signals native to the processor CPU1 to directly connect, and the PCIE signals are directly connected to the processor, so that the PCIE x16 expansion unit is used for operating expansion devices with high transmission rate.

The following is a further defined technical solution of the present invention, where the PCIE x16 SLOT2 expansion unit uses PCIE x8 signals generated by PCIE Bridge, and is used for working and using expansion devices based on PCIE x8 bandwidth due to limitation of uplink PCIE bus bandwidth.

The following is a further defined technical solution of the present invention, where the PCIE x8SLOT expansion unit uses PCIE x8 signals generated by PCIE Bridge, and is used for working and using expansion devices based on PCIE x8 bandwidth due to limitation of uplink PCIE bus bandwidth.

Compared with the prior art, the invention has the following technical effects:

the invention combines the domestic multi-processor with the whole scorpion cabinet structure, optimizes the whole scorpion cabinet structure, simultaneously applies the domestic multi-processor to the whole scorpion cabinet server, and breaks monopoly of the X86-frame multi-processor in the frame. Through the design of the deformed node, the domestic cloud S2500 multipath processor is not only applied to the high-performance computing node, but also can be matched with the expansion module to realize diversified application nodes such as the high-performance storage node and the like, thereby providing a hardware foundation for the application of the subsequent domestic whole cabinet in various task environments.

The invention will be further described with reference to the drawings and examples.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will briefly explain the embodiments or the drawings needed in the prior art, and it is obvious that the drawings in the following description are only some embodiments of the present invention and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a core computing block in accordance with the present invention;

FIG. 2 is a block diagram of a memory expansion module according to the present invention;

FIG. 3 is a block diagram of a heterogeneous expansion module according to the present invention;

FIG. 4 is a hardware framework diagram of the present invention;

FIG. 5 is a schematic diagram of a node combining a core computing module and a heterogeneous expansion module in accordance with the present invention.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.

As shown in fig. 1-5, a deformation node based on a domestic Feiteng multipath processor is provided, which comprises a core calculation module and an expansion module, wherein the expansion module comprises a storage expansion module and a heterogeneous expansion module, as shown in fig. 1-3; the computing nodes, the storage nodes and the special nodes are realized through different combination modes of the core computing module and the expansion module.

The deformation node based on the domestic cloud s2500 multipath processor consists of a core calculation module and an expansion module, and a single module is designed according to 1U 2N.

1. Core computing module design

The core computing module adopts a double-way design and consists of two cloud S2500 multipath processors, a single processor integrates 64 ARM v8 instruction set compatible processor cores FTC663, 8 DDR4-3200 storage controllers, a 17lane PCIE bus, a 16lane direct communication path and supports 2, 4 and 8 paths of CPU interconnection, and detailed performance indexes are shown in the following table:

TABLE 1 Performance index form

A hardware framework based on this processor design is shown in fig. 4.

The memory controller of the core computing module is connected with 16 DDR4 memory strips (standard single 32GB with ECC verification function and total capacity of 512 GB); the CPU2 of the processor is provided with a primary 1-path PCIE x1 interface, PCIE x1 is connected into the BMC, and the PCIE x1 interface is used for expanding interfaces such as management interfaces of the BMC, VGA and the like, so that the resource management and control functions of the nodes are realized; the processor CPU1 native 16Lane PCIE Gen3 bus is connected to a PCIE x16 SLOT1 SLOT at a board end and is used for connecting an expansion module (GPU/FPGA board card), the processor CPU2 native 16Lane PCIE Gen3 bus is connected to a PCIE Bridge chip (PEX 8748), a 3-path PCIE x8 interface, a 1-path PCIE x2 interface and a 1-path PCIE x1 interface are expanded, and the specific allocation is as follows:

the 1-path PCIE x1 interface is connected with the USB Bridge chip to generate 2 USB3.0 interfaces for connecting with USB external equipment;

the 1-path PCIE x2 interface is accessed to a SATA Bridge chip (with a hard RAID function) to generate 2 M.2SATA interfaces which are used for connecting 2 M.2SSD hard disks, can be used as a system disk and supports RAID 0/1;

the 1-path PCIE x8 interface is connected to a PCIE x8SLOT at the board end and is used for connecting an expansion module (tera-megacard/Raid card);

the 1-path PCIE x8 interface is connected with an Intel 82599 tera chip to generate 2 tera interfaces for connecting a tera switch, so that high-speed communication among nodes is realized;

the 1-path PCIE x8 interface is connected to a PCIE x16 SLOT2 SLOT and is used for connecting an expansion module (Raid/GPU/FPGA board card);

because the PCIE Bridge chip is limited by the uplink PCIE x16 bandwidth, the downlink expansion PCIE interface needs to consider the speed of the uplink total bandwidth when the equipment is connected in parallel when the peripheral equipment is connected.

2. Expansion module design

The expansion module is based on three external SLOT expansion designs of PCIE x16 SLOT1, PCIE x16 SLOT2 and PCIE x8SLOT of the core module, and comprises a PCIE x16 SLOT1 expansion unit, a PCIE x16 SLOT2 expansion unit and a PCIE x8SLOT expansion unit.

PCIE x16 SLOT1 expansion unit:

the expansion unit uses a PCIE x16 signal direct connection design of a processor CPU1, and expansion equipment is directly connected with the processor through PCIE signals, so that the expansion unit is suitable for expansion equipment with higher transmission rate requirements, such as: and the GPU (x 16) card and the FPGA (x 16) card are used for selecting a full-length card dimension design structural member of a PCIE standard, are compatible with expansion equipment of different specifications, and are connected into a PCIE x16 SLOT1 SLOT of a core computing module through a PCIEX16 extension line.

PCIE x16 SLOT2 expansion unit:

the expansion unit uses PCIE x8 signals generated by PCIE Bridge, and because the expansion unit is limited by the uplink PCIE bus bandwidth, the expansion unit is suitable for expansion devices based on PCIE x8 bandwidth, for example: and the RAID (x 8) card, the FPGA (x 8) card and the GPU (x 8) card are used for selecting a full-length card size design structural member of a PCIE standard, and are compatible with expansion equipment of different specifications, and the expansion equipment is connected into a PCIE x16 SLOT2 SLOT of a core computing module through a PCIEx16 extension line.

PCIE x8SLOT expansion unit:

the expansion unit uses PCIE x8 signals generated by PCIE Bridge, and because the expansion unit is limited by the uplink PCIE bus bandwidth, the expansion unit is suitable for expansion devices based on PCIE x8 bandwidth, for example: the universal network card and the RAID (x 8) card are limited by the size, a half-card size design structural member of PCIE standard is selected, and the universal network card and the RAID are compatible with expansion equipment with different specifications and are connected through an on-board PCIE x6 SLOT2 SLOT.

The matched equipment of the RAID (x 8) card is connected with the RAID card through an SAS cable by a hard disk connection card, and the disk position of the hard disk supports 3.5 inches and 2.5 inches.

The LSIMegaRAID SAS 9361-8i is selected in matching with the standard of the heterogeneous expansion module, 8-disk bits are supported, the single-disk capacity is 10TB, the total capacity is 80TB, and RAID0, 1, 5, 6, 10, 50 and 60 are supported;

the LSIMegaRAID SAS 9361-16i is selected in combination with the standard of the storage expansion module, which supports 16 disk bits, 10TB of single disk capacity, 160TB of total capacity, and RAID0, 1, 5, 6, 10, 50, 60.

3. Deformed node combination

Based on different configurations and combination modes of the core module and the expansion module, the node can be deformed, and the suggested configuration is shown in the following table 2;

TABLE 2 configuration forms

The list only lists the suggested combination collocation of the common expansion cards, so that different expansion cards can be replaced according to the actual demands of the users, and the reusability and the deployment flexibility of the nodes are improved.

It should be noted that, the related english terms of this embodiment are further described:

GPU: graphics Processing Unit, a graphics processor;

and (3) FPGA: field Programmable Gate Array, field programmable gate array;

1U1N: u=1200 mm x600mm x46.5mm, n=node means core module/extension module, 1 core/extension module is contained in 1U space;

SATA: serial Advanced Technology Attachment, serial advanced technology attachment;

SAS: serial Attached SCSI, serial attached SCSI;

RAID: redundant Arrays of Independent Disks, disk arrays;

PCIE: peripheral Component Interconnect express, high speed serial computer expansion bus standard;

BMC: baseboard Management Controller, a baseboard management controller.

The above description is only of the preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, all equivalent changes according to the shape, structure and principle of the present invention are covered in the protection scope of the present invention.

Claims (5)

1. The deformation node based on the domestic Feiteng multipath processor is characterized by comprising a core calculation module and an expansion module, wherein the calculation node, a storage node and a special node are realized through different combination modes of the core calculation module and the expansion module;

the core computing module adopts a double-path design and is composed of two cloud S2500 multipath processors, and a single processor integrates 64 ARM v8 instruction set compatible processor cores FTC663, 8 DDR4-3200 memory controllers, a 17-lane PCIE bus, a 16-lane direct communication path and supports 2, 4 and 8-path CPU interconnection;

the expansion module comprises a PCIE x16 SLOT1 expansion unit, a PCIE x16 SLOT2 expansion unit and a PCIE x8SLOT expansion unit.

2. The modified node based on a domestic Feiteng multipath processor according to claim 1, wherein the memory controller of the core computing module is connected with 16 DDR4 memory banks; the CPU2 of the processor is provided with a primary 1-path PCIE x1 interface, the PCIE x1 interface is connected into the BMC, and the PCIE x1 interface is used for expanding a management network port and a VGA interface of the BMC to realize the resource management and control functions of the nodes; the processor CPU1 is connected to the PCIE x16 SLOT1 SLOT at the board end by a primary 16Lane PCIE Gen3 bus, and is used for connecting with an expansion module; the CPU2 native 16Lane PCIE Gen3 bus is accessed to a PCIE Bridge chip, and a 3-path PCIE x8 interface, a 1-path PCIE x2 interface and a 1-path PCIE x1 interface are expanded.

3. The deformation node based on the domestic Feiteng multipath processor of claim 1, wherein the PCIE x16 SLOT1 expansion unit uses PCIE x16 signals native to the processor CPU1 directly connected with the processor through PCIE signals, and is used for operating expansion equipment with high transmission rate.

4. The deformation node based on the domestic Feiteng multipath processor of claim 1, wherein the PCIE x16 SLOT2 expansion unit uses PCIE x8 signals generated by PCIE Bridge, and is used for the operation of expansion equipment based on PCIE x8 bandwidth due to the limitation of uplink PCIE bus bandwidth.

5. The deformation node based on the domestic Feiteng multipath processor of claim 1, wherein the PCIE x8SLOT expansion unit uses PCIE x8 signals generated by PCIE Bridge, and is used for operating expansion equipment based on PCIE x8 bandwidth due to the limitation of uplink PCIE bus bandwidth.