CN117762189A - Distributed full-coherent synchronous intermediate frequency generation system based on independent DDS - Google Patents

Abstract

The invention relates to a distributed full-phase coherent synchronous intermediate frequency generation system based on independent DDS, which comprises N DDS synchronous circuit boards, a clock phase distributor, a frequency multiplication phase distributor, a frequency division phase divider and an optical fiber triggering phase distributor, wherein the DDS synchronous circuit boards comprise FPGA modules, DDS modules and optical modules, a reference clock CLK0 of an external clock source is used as a coherent reference, the reference clock CLK is distributed to each FPGA module through the clock phase distributor, the reference clock REFCLK is distributed to each DDS module through the frequency multiplication phase distributor and the like, a synchronous clock SYNC_IN is distributed to each DDS module through the frequency division phase divider, a frequency control code and a synchronous triggering signal are distributed to each optical module through the optical fiber triggering phase distributor, and the optical modules send received signals to the corresponding FPGA modules. The invention makes the operation parameter control of DDS more flexible.

Description

Distributed full-coherent synchronous intermediate frequency generation system based on independent DDS

Technical Field

The invention belongs to the technical field of active phased array radar frequency sources, and particularly relates to a distributed full-phase coherent synchronous intermediate frequency generation system based on an independent DDS.

Background

In the technical research and equipment development of active phased array radar frequency sources at present, clocks and local oscillation signals of TR components are usually provided by a frequency source module after power division of a constant-amplitude and constant-phase distribution network, the frequencies of the local oscillation signals of all subarray TR components of an area array are the same, and the requirement of flexible scheduling of the area array subarray cannot be met. If each subarray has an independently working frequency source, and local oscillation signals output by the frequency sources are synchronous, the conditions that different subarrays independently work in time and space and the two-to-two half arrays independently work can be met, and conditions are provided for the radar to flexibly realize the calling of independent distributed subarrays.

The DDS synchronization technology is also a center, and the traditional synchronization signal generation adopts an analog mode and a digital mode to realize phase control. The analog mode realizes the phase control by dividing the single signal power into multiple paths of signals and performing time delay and other methods on each path of signal to adjust the phase of each path of signal. The digital method performs phase control, and has simple circuit, but can accurately represent the analog signal because of infinite quantization bit number. In practical applications, the quantization bit number is limited by many factors, and cannot reach the upper limit, which leads to quantization error.

Along with the development of modern electronic technology and microelectronic technology, direct Digital Synthesis (DDS) has been developed rapidly, and has the advantages of short frequency conversion time, high frequency resolution, continuous phase output, programmable control, full-digital structure, convenient integration and the like, so that the DDS is widely applied in the fields of communication, radar, test system, electronic countermeasure and the like, and becomes a new main mode of frequency synthesis. Along with the development of DDS technology, the DDS chip integrates the function of synchronous signal calibration, so that how to synchronize output signals among a plurality of DDS chips is studied, and the method has important use value.

Disclosure of Invention

The invention aims to provide a distributed full-coherent synchronous intermediate frequency generation system based on independent DDSs, which can control each DDS to generate synchronous single-frequency signals with set phases, so that the control of the operation parameters of the DDS is more flexible, and the system has the functions of independent programming control, frequency agility and external synchronous triggering.

The aim of the invention is achieved by the following technical scheme:

the distributed full-coherent synchronous intermediate frequency generation system based on the independent DDS is characterized by comprising N DDS synchronous circuit boards, a clock phase distributor, a frequency multiplication phase distributor, a frequency division phase divider and an optical fiber triggering phase distributor, wherein the DDS synchronous circuit boards comprise FPGA modules, DDS modules and optical modules, a reference clock CLK0 of an external clock source is used as a coherent reference, the reference clock CLK0 is distributed to working clocks CLK of all the FPGA modules through the clock phase distributor, then is distributed to reference clocks REFCLK of all the DDS modules through the frequency multiplication phase distributor and the like, is distributed to all the optical modules through the frequency division phase divider and the synchronous clock SYNC_IN of all the DDS modules through the optical fiber triggering phase distributor, the optical modules transmit received signals to the corresponding FPGA modules, and all the FPGA modules control signal generator data streams of all the DDS modules according to received signal parameter control commands, and control all the DDS modules to generate intermediate frequency signals for setting phases and frequencies when receiving synchronous triggering signals.

Furthermore, each working clock source in the system adopts the same reference clock source; the clock phase distributor, the frequency multiplication phase distributor, the distribution phase distributor and the clock source are all coherent signals, and the phase difference of the same kind of signals is consistent at the same moment;

further, the FPGA controls the signal casting time required by the DDS to generate the intermediate frequency signals to be consistent, and paths of the synchronous trigger signals of the fiber and other distributor stations reaching all the FPGA are arranged in equal length;

further, each DDS is provided with a synchronous control function pin, and the intermediate frequency signal flow completes reset under the signal;

further, the path delay of the external reference clock source input to each clock interface pin in the system is the same;

further, paths of the optical modules of the wiring channels of the external source synchronous trigger signal unit transmission synchronous trigger signal unit are arranged in equal length;

further, the parameter characteristics of the sinusoidal signal generated by the DDS signal generator are determined by the initial phase, the phase accumulated value and the phase accumulated stepping parameter;

further, the input reference source clock CLK0 of the distributed full-coherent synchronous intermediate frequency generation system is unique, the reference clock CLK0 is distributed to the clock CLK of the FPGA through a clock distributor and the like, is distributed to the DDS reference clock REFCLK through a frequency multiplication distributor and the like, and is distributed to the DDS synchronous clock sync_in through a frequency division and the like, wherein CLK0, CLK, REFCLK and sync_in are coherent signals.

Further, DDS internal registers in each DDS synchronous circuit board are configured asynchronously through the FPGA, and the DDS internal registers comprise a general register, a frequency register, an initial phase register, an amplitude register and a synchronous register. After the system is powered on, the data flow of each DDS signal generator is instructed to use a synchronous clock SYNC_IN calibration logic, each DDS chip generates an equal-phase synchronous clock SYNC_CLK, after each FPGA on the DDS synchronous circuit board detects the rising edge of the synchronous trigger signal pulse, a synchronous IO_UPDATE signal is sent to each DDS, and the values IN the DDS buffer area are instructed to be written into N DDS registers at the same time. The N DDSs are ensured to use the same frequency update pulse synchronized by the synchronous clock, the frequency control word and the amplitude control word of each DDS are ensured to be synchronously updated in the same system clock counting period, and a plurality of DDSs are controlled to generate synchronous single-frequency signals with set phases.

Further, the FPGA module receives the frequency control code and writes the frequency control code into a frequency register of the DDS module in advance through an SPI communication protocol.

Further, the block number of the DDS synchronous circuit board is set according to the array division of the phased array active area array.

Compared with the prior art, the invention has the beneficial effects that:

(1) According to the invention, the quantity of the FPGA is consistent with that of the DDS, one FPGA chip controls one DDS, independent expansion distribution can be realized according to the actual application system requirement, a DDS synchronous circuit board does not have main and auxiliary components, the output of each DDS is independent and independent of each other, the FPGA control program is unified, each DDS is ensured to use the same frequency update pulse synchronized by the synchronous clock, the frequency control word and the amplitude control word of each DDS are ensured to be synchronously updated in the same system clock counting period, and a plurality of DDSs are controlled to generate synchronous single-frequency signals with set phases;

(2) The DDS signal generating circuit board performs data interaction with the trigger distribution plate through the optical fiber, the FPGA realizes a signal flow interface with the optical module, the stability of data transmission is ensured, the frequency control code and the synchronous trigger signal of the trigger distribution plate of the optical fiber are received, the hardware circuit is consistent, the channels can be mutually exchanged, the flexibility of interchange is improved, the circuit is simple, and the precision is high.

Drawings

Fig. 1 is a schematic diagram of the working principle of the DDS synchronous circuit board.

Fig. 2 is a schematic diagram of a distributed full-coherent synchronous intermediate frequency generation system based on an independent DDS.

Fig. 3 is a schematic diagram of an internal program flow of the independent DDS synchronization circuit board FPGA.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The embodiment provides a distributed full-phase coherent synchronous intermediate frequency generation system based on an independent DDS, which is characterized in that the full-phase coherent DDS synchronous system is provided with N DDS synchronous circuit boards, a clock phase distributor, a frequency multiplication phase distributor, a frequency division phase frequency divider and an optical fiber triggering phase distributor according to the requirements of an application system (such as a phased array active area array); the synchronous system takes an input reference source clock CLK0 as a coherent reference, wherein the reference clock CLK0 is distributed to an FPGA working clock CLK through a clock distributor and the like, distributed to a DDS reference clock REFCLK through a frequency multiplication distributor and the like, and distributed to a DDS synchronous clock SYNC_IN through a frequency division divider and the like, wherein CLK0, CLK, REFCLK and SYNC_IN are coherent signals. Each FPGA controls each DDS signal generator data stream to use a synchronous clock SYNC_IN calibration logic according to the received signal parameter control command, and controls each DDS to generate an intermediate frequency signal with set phase and frequency when receiving a synchronous trigger signal; specifically, the following aspects are devised.

DDS synchronization circuit board hardware configuration

The DDS chip is a core for realizing the synchronization function of the whole system, the DDS synchronization circuit board is a single-channel DDS chip with the synchronization function, a synchronization mechanism is supported on hardware, and a SYCN_IN receiver is integrated inside. The SYCN_IN signal is mainly used for synchronous reassignment, so that the clock state of the clock generator inside the DDS chip can be kept consistent with that of other DDS chips. Assuming that all devices have the same REFCLK edge (using the clock distribution and delay equalization module) and all devices have the same syncin edge (using the SYNC distribution and delay equalization module), then all DDS chips will generate one consistent internal SYNC pulse that causes all devices to become the same predefined clock state at the same time, that is, all devices' internal clocks are fully synchronized. The working principle schematic diagram of the DDS synchronous circuit board is shown in fig. 1, an optical module receives an external frequency code and a trigger signal and sends the external frequency code and the trigger signal to an internal FPGA, and the FPGA writes the external frequency code and the trigger signal into a DDS internal register buffer area through an SPI;

the synchronization mechanism depends on whether the edge detection module in the synchronous receiver can stably generate the synchronization pulse. To generate a valid synchronization pulse, the sync_in signal rising edge needs to be correctly sampled by the local SYSCLK rising edge.

The FPGA selects a high-performance field programmable gate array, integrates powerful programmable resources which can be flexibly configured and combined, and is used for realizing various functions such as an input/output interface, general digital logic, a memory, digital signal processing, clock management and the like. Not only CLB modules are included that can be used to implement conventional digital logic and distributed RAM. In addition, the optical module also comprises programmable modules such as I/O, block RAM, DSP, MMCM, GTX and the like, and can realize communication with the optical module. The optical module has four-receiving and four-transmitting functions, is a four-path parallel optical receiving and transmitting integrated module, has a single-path speed of 10.3125Gbps and is mainly applied to very short-distance parallel multichannel optical interconnection data communication. Has the characteristics of small electromagnetic radiation, strong anti-interference capability and the like. The LVDS driving chip converts an externally input SYNC_IN single-ended chip into an LVDS differential signal.

The number of the FPGA is consistent with that of the DDS, one FPGA chip controls one DDS, and independent expansion distribution can be realized according to the requirements of an actual application system.

When the number of the all-phase reference DDS channels is larger than 1, the working clock CLK of each FPGA, the reference clock REFCLK of the DDS and the synchronous clock SYNC_IN are derived from the same external reference clock source CLK0, and the same kind of clock delay reaching each device after frequency multiplication or frequency division of the external reference clock source is consistent.

The FPGA controls the signal casting time delay required by the DDS to generate the intermediate frequency signal to be consistent, and the processing precision of the printed board is ensured; and paths of wires of the optical fiber and other distributor output synchronous trigger signals reaching each FPGA are subjected to equal length control.

The DDS signal generating circuit board performs data interaction with the trigger distribution plate through an optical fiber, a signal flow interface with the optical module is realized by the FPGA, and a frequency control code and a synchronous trigger signal of the optical fiber trigger distribution plate are received.

The DDS synchronous circuit board has identical hardware circuits, channels can be mutually exchanged, the debugging complexity is reduced, and the flexibility of the exchange is improved.

System hardware configuration

The distributed full-coherent synchronous intermediate frequency generation system comprises a plurality of DDS synchronous circuit boards, a clock phase distributor, a frequency multiplication phase distributor, a frequency division phase frequency divider and an optical fiber triggering phase distributor; the reference clock is distributed to a clock CLK of the FPGA through an isophase distributor, distributed to a DDS reference clock REFCLK through frequency multiplication, and distributed to a DDS synchronous clock SYNC_IN through frequency division of REFCLK; the FPGA commands the data streams of the DDS signal generators to use synchronous clock SYNC_IN calibration logic according to the received signal parameter control command, and when receiving the synchronous trigger signal, the FPGA simultaneously controls a plurality of DDSs to generate digital signals with set phases;

the method comprises the steps of connecting a computer with an optical fiber trigger plate through a network, controlling ARM in the optical fiber trigger plate through the network, controlling an FPGA to command an optical module to respectively send single-pulse triggers, distributing the single-pulse triggers through equal phases, enabling the single-pulse triggers to a DDS synchronous circuit board through equal-length optical fibers, and simultaneously sending IO_UPDATE trigger signals to the DDS after each FPGA detects a pulse rising edge to command values in a DDS buffer area to be written into a register. And the frequency update pulse synchronized by the same synchronized clock is used for all the DDSs, and the frequency control words and the amplitude control words of all the DDSs are synchronously updated in the same system clock counting period.

FPGA asynchronous programming and synchronous trigger signal

After the FPGA asynchronously programs and writes the frequency and phase control words into the DDS through the SPI communication protocol, the DDS does not UPDATE the data to the DDS register, but temporarily registers the data in the buffer area, and all DDS kernels cannot respond to the changes until the register UPDATE signal I/O_UPDATE arrives, and the registers corresponding to the frequency and phase control words are updated. The distributed DDS output signal can therefore only be synchronized after the SYNC_CLK is aligned and the I/O_UPDATE signals are synchronized.

After alignment of the sync_clk inside the DDS, the synchronous io_update signal needs to be simultaneously provided to the DDS. First, the frequency tuning word register and the phase register of the device are programmed in the DDS buffer one by one in an asynchronous manner. The DDS core on the synchronization circuit board will not respond to these changes for a while until the IO UPDATE signal is received.

Because the data updating signal is a sudden and discontinuous digital signal, in the actual use process, the distance between the trigger plate and the main/auxiliary channel DDS is longer, if a differential signal is used for long-distance transmission, rising edge slowing or ringing phenomenon can occur, error rate is introduced, the reliability of the trigger signal is reduced, and therefore the DDS cannot complete frequency hopping at the required moment and cannot realize synchronization.

In order to enhance the reliability of the data updating signal, the transmission of the triggering signal is completed through the optical fiber, and the optical fiber has the advantages of small volume, light weight, small loss, high transmission rate and the like. In addition, the optical power distribution network is flexible and various, electromagnetic interference and crosstalk among various paths of signals can be well avoided, and alternating modulation interference does not exist. The high frequency of the light wave makes the signal bandwidth very small compared with the signal bandwidth, so that the optical fiber has excellent constant transmission performance in the required microwave frequency band, and the sensitivity to temperature variation is an order of magnitude lower than that of the coaxial cable and the microstrip line. Each fiber branch joint is sent to each channel, and has high inserting phase stability.

Programming control design

Under the conditions of clock state matching and state transition synchronization, multi-device synchronization can be realized. Clock synchronization may allow a user to program multiple devices asynchronously while programming content is activated synchronously by I/O updates to all devices simultaneously. The FPGA is a main control chip of a signal source, and has higher operability and feasibility by adopting VHDL language. And testing the phase index of the output signal, analyzing the result, storing amplitude and phase error compensation data by using a FLASH memory, and controlling the DDS by using an FPGA during whole machine debugging to finish amplitude and phase error compensation.

The distributed DDS synchronization is realized, except that all the synchronization conditions are met on hardware, and the synchronization step is realized by virtue of the configuration of the FPGA asynchronous programming DDS register. After power-on, in order to avoid the excessively fast loading time of the FLASH program and the starting time of the DDS, the time delay of 5 seconds is needed to be manually carried out after the power-on, so that the normal operation of the time sequence is ensured. And then resetting the DDS registers, and commanding all registers to restore default settings. Configuring a DDS register, firstly commanding SYNC_CLK not to be enabled, and performing DAC calibration to firstly set '1' and then set '0'; the synchronous calibration enable of the synchronous register USR0 is then turned on. Then turn on SYNCLK enable output, DAC calibration is first '1' then '0'; configuring PROFILE enabling of the DDS register, and configuring a DDS frequency register and an amplitude register; after the preparation work is finished, waiting to judge whether the local control command and the external trigger command are received or not, thereby completing frequency hopping. After the frequency hopping is completed, the synchronizing function of the synchronizing register is closed.

The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (10)

1. The distributed full-coherent synchronous intermediate frequency generation system based on the independent DDS is characterized by comprising N DDS synchronous circuit boards, a clock phase distributor, a frequency multiplication phase distributor, a frequency division phase divider and an optical fiber triggering phase distributor, wherein the DDS synchronous circuit boards comprise FPGA modules, DDS modules and optical modules, a reference clock CLK0 of an external clock source is used as a coherent reference, the reference clock CLK0 is distributed to working clocks CLK of all the FPGA modules through the clock phase distributor, then is distributed to reference clocks REFCLK of all the DDS modules through the frequency multiplication phase distributor and the like, is distributed to all the optical modules through the frequency division phase divider and the synchronous clock SYNC_IN of all the DDS modules through the optical fiber triggering phase distributor, the optical modules transmit received signals to the corresponding FPGA modules, and all the FPGA modules control signal generator data streams of all the DDS modules according to received signal parameter control commands, and control all the DDS modules to generate intermediate frequency signals for setting phases and frequencies when receiving synchronous triggering signals.

2. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the paths of the wires of the optical fiber equal-phase distributor output synchronous trigger signals reaching all FPGA modules are equal in length.

3. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the clock phase distributor, the frequency multiplication phase distributor and the external clock source have the same instantaneous phase difference at the same time.

4. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the FPGA module asynchronously configures registers inside the DDS module to realize distributed DDS synchronization.

5. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 4, wherein said registers include DDS registers, frequency registers, initial phase registers, amplitude registers, and synchronization registers.

6. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 5, wherein the method for realizing the synchronization of the distributed DDS is as follows: after the system is powered on, manually delaying for 5 seconds, resetting the DDS registers, and commanding all registers to restore default settings; configuring a DDS register, firstly commanding SYNC_CLK of the DDS register not to be enabled, and firstly setting 1 and then setting 0 by DAC calibration; then starting synchronous calibration enabling of a synchronous register USR0, starting SYNCLK enabling output of a DDS register, and setting 1 and 0 in DAC calibration; configuring PROFILE enabling of the DDS register, and configuring a DDS frequency register and an amplitude register; after the preparation work is finished, waiting to judge whether the local control command and the external trigger command are received or not, and finishing frequency hopping.

7. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the FPGA module receives the frequency control code and writes it into the frequency register of the DDS module in advance through the SPI communication protocol.

8. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the number of blocks of the DDS synchronous circuit board is set according to the array division of the phased array active area array.

9. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the optical module adopts four-receiving four-emitting modules, and the single-path rate reaches 10.3125Gbps.

10. The distributed full-coherent synchronous intermediate frequency generation system based on independent DDS according to claim 1, wherein the FPGA module adopts VHDL language.