CN113451776A - High-integration-level digital phased array system - Google Patents
High-integration-level digital phased array system Download PDFInfo
- Publication number
- CN113451776A CN113451776A CN202110694715.1A CN202110694715A CN113451776A CN 113451776 A CN113451776 A CN 113451776A CN 202110694715 A CN202110694715 A CN 202110694715A CN 113451776 A CN113451776 A CN 113451776A
- Authority
- CN
- China
- Prior art keywords
- radio frequency
- layer
- digital
- phased array
- matrix switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 claims abstract description 43
- 238000006243 chemical reaction Methods 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 6
- 230000010354 integration Effects 0.000 abstract description 10
- 239000011449 brick Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000006872 improvement Effects 0.000 description 7
- 238000003491 array Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
- H01Q3/36—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means with variable phase-shifters
- H01Q3/38—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means with variable phase-shifters the phase-shifters being digital
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0006—Particular feeding systems
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a high-integration-level digital phased array system which comprises a panel antenna array layer, a matrix switch calibration network layer, a radio frequency transceiving channel layer based on radio frequency SOC (system on chip) and a digital beam forming layer, wherein the panel antenna array layer is connected with the matrix switch calibration network layer through a radio frequency signal, and the matrix switch calibration network layer is connected with the radio frequency transceiving channel layer based on the radio frequency SOC through a radio frequency signal and a high-speed digital signal. According to the invention, the panel antenna array layer, the matrix switch calibration network layer, the radio frequency transceiving channel layer based on the radio frequency SOC and the digital beam forming layer are packaged in a vertical three-dimensional framework in a tile integration mode, so that a digital phased array system with complete functions is formed, the problems of high cost, multiple components, difficulty in synchronization and high integration difficulty of the traditional digital phased array brick integration mode are solved, the digital phased array brick integration method is suitable for scenes requiring light weight and portability of equipment, and the use range of the digital phased array is greatly expanded.
Description
Technical Field
The invention relates to the technical field of phased array systems, in particular to a high-integration-level digital phased array system.
Background
With the increasing application of phased array systems in military and civil electronic systems, the phased array technology itself is also continuously developing forward. The digital phased array system adopts a digital mode to form wave beams, and compared with an analog phased array, the digital phased array system has the advantages of large dynamic range, high wave beam precision, easy formation of simultaneous multi-wave beams and the like, but simultaneously, because the wave beams are formed in a digital domain, a receiving and transmitting channel behind each antenna comprises a receiving and transmitting component part in the analog phased array, a frequency conversion channel and analog/digital mixing devices such as AD, DA and the like, the complexity of the receiving and transmitting channel is high, and the number of components is greatly increased.
The phased array is mainly integrated in a brick type and a tile type. The phased array formed by adopting the tile type integration mode is a mainstream integration mode of an analog phased array system due to light weight and low section, and the distance between the antenna units of the phased array is usually smaller than half wavelength, so that the interval between the receiving and transmitting channels is limited within half wavelength. Different from an analog phased array, because each receiving and transmitting channel of the digital phased array contains a plurality of devices and is difficult to arrange in a half-wavelength distance, the integration mode of the general digital phased array usually adopts backward brick type integration, so that the system cost is high, the size is large, and the digital phased array is not beneficial to being used in a scene needing light weight and portability of equipment.
Disclosure of Invention
The invention provides a high-integration digital phased array system to solve the problems in the background technology.
In order to achieve the purpose, the invention adopts the following technical scheme:
a high-integration-level digital phased array system comprises a panel antenna array layer, a matrix switch calibration network layer, a radio frequency transceiving channel layer based on radio frequency SOC and a digital beam forming layer, wherein the panel antenna array layer is connected with the matrix switch calibration network layer through radio frequency signals, the matrix switch calibration network layer is connected with the radio frequency transceiving channel layer based on the radio frequency SOC through radio frequency signals and high-speed digital signals, and the radio frequency transceiving channel layer based on the radio frequency SOC is connected with the digital beam forming layer through the high-speed digital signals.
As a further improvement scheme of the technical scheme: the planar antenna array layer comprises N unit antenna arrays, microstrip units and a metal back plate, a feed port of each unit antenna in the N unit antenna arrays is fixedly connected to the microstrip units, the feed mode of each unit antenna is a feedback mode, and the microstrip units are arranged on the surface of the metal back plate.
As a further improvement scheme of the technical scheme: the matrix switch calibration network layer comprises a calibration transmitting channel, a calibration receiving channel and a matrix switch network, the matrix switch calibration network layer is of a planar PCB structure, the matrix switch network comprises a high-speed bus connector, a plurality of SMA connectors and a plurality of SMP connectors, and the high-speed bus connector is used for transmitting a control signal from the FPGA and controlling the calibration transmitting and receiving channels to work in a time-sharing mode; the first SMA connectors are distributed at the left end and the right end of the PCB and used for connecting a radio frequency receiving and transmitting channel layer based on a radio frequency SOC; a plurality of SMP connectors are distributed at the middle position of the PCB, and the plurality of SMP connectors are used for connecting signals to the N-unit antenna array.
As a further improvement scheme of the technical scheme: the matrix switch calibration network layer further includes a SP8T and a plurality of SPDT switches, the SP8T and the plurality of SPDT switches for controlling routing of signals in the matrix switch calibration network layer.
As a further improvement scheme of the technical scheme: the radio frequency receiving and transmitting channel layer based on the radio frequency SOC is of a planar PCB structure and comprises a control signal connector, a plurality of second SMA connectors, two high-speed signal connectors and a plurality of radio frequency SOC chips, wherein the control signal connector is connected with the matrix switch calibration network layer and is used for transmitting control signals from the FPGA and controlling the matrix switch calibration network layer to work in a time-sharing mode; the plurality of second SMA connectors are distributed at the left end and the right end of the PCB and are used for connecting the matrix switch calibration network layer; two high-speed signal connectors are distributed in the middle of the PCB, are connected with the digital beam forming layer and are used for transmitting baseband data from the ADC and the DAC to the beam forming layer and bridging control signals of the FPGA.
As a further improvement scheme of the technical scheme: each radio frequency SOC chip comprises a receiving front end, a transmitting front end, a receiving frequency conversion channel, a transmitting frequency conversion channel, a BB phase-locked loop, an RX phase-locked loop, a TX phase-locked loop, an ADC data converter and a DAC data converter, wherein a signal output end of the receiving front end is in electrical signal connection with a signal input end of the receiving frequency conversion channel, a signal output end of the receiving frequency conversion channel is in electrical signal connection with a signal input end of the ADC data converter, a signal output end of the RX phase-locked loop is in electrical signal connection with a signal input end of the receiving frequency conversion channel, a signal output end of the DAC data converter is in electrical signal connection with a signal input end of the transmitting frequency conversion channel, a signal output end of the transmitting frequency conversion channel is in electrical signal connection with a signal input end of the transmitting front end, and a signal output end of the TX phase-locked loop is in electrical signal connection with a signal input end of the transmitting frequency conversion channel, and the signal output end of the BB phase-locked loop is respectively in electric signal connection with the signal input ends of the ADC data converter and the DAC data converter.
As a further improvement scheme of the technical scheme: the digital beam forming layer comprises a plurality of FIR filters and a plurality of multipliers, and each FIR filter is electrically connected with each corresponding multiplier.
As a further improvement scheme of the technical scheme: the digital wave beam shaping layer also comprises a secondary power supply, a data receiving interface and a data sending interface, wherein the secondary power supply is used for converting a 28V power supply input from the outside into a power supply with a specification of +5V, +3.3V or +1.8V required by the work of the digital phased array system, the data receiving interface and the data sending interface are both network ports, the data receiving interface is used for receiving wave beam pointing information and dwell time information sent by the outside, and the data sending interface is used for sending the current state information of the digital phased array system to the outside.
Compared with the prior art, the invention has the beneficial effects that:
the invention adopts radio frequency SOC to simplify radio frequency transceiving channel, and on the basis, adopts a plane layered structure comprising a flat antenna array layer, a matrix switch calibration network layer, a radio frequency transceiving channel layer based on the radio frequency SOC, a digital beam forming layer and other multilayer plane circuit structures, and an antenna backboard and other plane mounting structures, and forms a tile type integrated digital phased array system by the multilayer structure in a vertical radio frequency connection and vertical digital high-speed connection mode, integrates the traditional complicated radio frequency transceiving channel in a single chip by adopting a high-integration radio frequency SOC chip mode, greatly reduces the system volume, avoids the layout constraint of the antenna spacing on small phased array tile type integrated devices, further forms the digital phased array system with complete functions, solves the problems that the traditional digital phased array type integration mode has high cost and more devices, the digital phased array is difficult to synchronize and high in integration difficulty, is suitable for scenes needing light weight and portability of equipment, and greatly expands the application range of the digital phased array.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings. The detailed description of the present invention is given in detail by the following examples and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic structural diagram of a high-integration digital phased array system according to the present invention;
FIG. 2 is a schematic block diagram of a calibration network layer of a matrix switch of a highly integrated digital phased array system according to the present invention;
FIG. 3 is a diagram showing an internal structure of a radio frequency SOC of a highly integrated digital phased array system according to the present invention;
FIG. 4 is a diagram of a clock tree of a highly integrated digital phased array system according to the present invention;
fig. 5 is a schematic block diagram of receive digital beamforming of a highly integrated digital phased array system according to the present invention;
fig. 6 is a schematic block diagram of transmit digital beamforming of a highly integrated digital phased array system according to the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
the antenna comprises a panel antenna array layer 1, a matrix switch calibration network layer 2, a radio frequency SOC-based radio frequency transceiving channel layer 3 and a digital beam forming layer 4.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention. The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 to 6, in an embodiment of the present invention, a high-integration digital phased array system includes a flat antenna array layer 1, a matrix switch calibration network layer 2, a radio frequency transceiving channel layer 3 based on a radio frequency SOC, and a digital beam forming layer 4, where the flat antenna array layer 1 is connected to the matrix switch calibration network layer 2 through a radio frequency signal, the matrix switch calibration network layer 2 is connected to the radio frequency transceiving channel layer 3 based on the radio frequency SOC through a radio frequency signal and a high-speed digital signal, and the radio frequency transceiving channel layer 3 based on the radio frequency SOC is connected to the digital beam forming layer 4 through a high-speed digital signal.
Preferably, the panel antenna array layer 1 includes N element antenna arrays, microstrip elements and a metal back plate, the N element antenna arrays adopt a √ N planar arrangement manner, each element antenna is in the form of a microstrip antenna, a feed port of each element antenna in the N element antenna arrays is fixedly connected to a microstrip element, a feed manner of each element antenna is a feedback, and the microstrip elements are mounted on the surface of the metal back plate.
Preferably, the matrix switch calibration network layer 2 comprises a calibration transmitting channel, a calibration receiving channel and a matrix switch network, the matrix switch calibration network layer 2 is of a planar PCB structure, the matrix switch network comprises a high-speed bus connector, a plurality of SMA connectors and a plurality of SMP connectors, the high-speed bus connector is a 60-core high-speed connector, and the high-speed bus connector is used for transmitting a control signal from the FPGA and controlling the calibration transmitting and receiving channel to work in a time-sharing manner; the first SMA connectors are distributed at the left end and the right end of the PCB and used for connecting a radio frequency receiving and transmitting channel layer 3 based on a radio frequency SOC; a plurality of SMP connectors are distributed at the middle position of the PCB, and the plurality of SMP connectors are used for connecting signals to the N-unit antenna array.
Preferably, the matrix switch calibration network layer 2 further comprises a SP8T and a plurality of SPDT switches, the SP8T and the plurality of SPDT switches being used to control the routing of signals in the matrix switch calibration network layer 2.
Preferably, the radio frequency receiving and transmitting channel layer 3 based on the radio frequency SOC is a planar PCB structure, the radio frequency receiving and transmitting channel layer 3 based on the radio frequency SOC includes a control signal connector, a plurality of second SMA connectors, two high-speed signal connectors and a plurality of radio frequency SOC chips, the control signal connector is a 60-core connector, the control signal connector is connected with the matrix switch calibration network layer 2, and is used for transmitting a control signal from the FPGA and controlling the matrix switch calibration network layer 2 to work in a time-sharing manner; the plurality of second SMA connectors are distributed at the left end and the right end of the PCB and are used for connecting the matrix switch calibration network layer 2; the two high-speed signal connectors are 240-core connectors, are distributed in the middle of the PCB and are connected with the digital beam forming layer 4, and are used for transmitting baseband data from the ADC and the DAC to the beam forming layer and bridging control signals of the FPGA.
Preferably, each radio frequency SOC chip includes a receiving front end, a transmitting front end, a receiving frequency conversion channel, a transmitting frequency conversion channel, a BB phase-locked loop, an RX phase-locked loop, a TX phase-locked loop, an ADC data converter, a DAC data converter, an electrical signal connection between a signal output end of the receiving front end and a signal input end of the receiving frequency conversion channel, an electrical signal connection between a signal output end of the receiving frequency conversion channel and a signal input end of the ADC data converter, an electrical signal connection between a signal output end of the RX phase-locked loop and a signal input end of the receiving frequency conversion channel, an electrical signal connection between a signal output end of the DAC data converter and a signal input end of the transmitting frequency conversion channel, an electrical signal connection between a signal output end of the transmitting frequency conversion channel and a signal input end of the transmitting front end, an electrical signal output end of the TX phase-locked loop and a signal input end of the transmitting frequency conversion channel, a signal output end of the BB phase-locked loop and a signal input ends of the ADC data converter and the DAC data converter, respectively The inter-signal connection is adopted, when the invention adopts 16 radio frequency SOCs, 16 paths of simultaneous radio frequency receiving and transmitting systems can be constructed, each radio frequency receiving and transmitting channel is in a full-coherent mode, the synchronization performance of the channel is ensured, specifically, the same 50M reference clock source is divided into 17 paths, wherein 16 paths provide an external clock for a baseband phase-locked loop of the 16 radio frequency SOCs, 1 path provides a reference clock for an ADF5355 of a phase-locked chip, the ADF5355 is locked to generate a local oscillation signal, and the local oscillation signal is divided into 16 paths to provide local oscillations for the 16 radio frequency SOCs respectively. The radio frequency SOC adopted by the invention has a synchronization function, specifically, the radio frequency SOC externally comprises a synchronization signal SYNC pin, and when the pin receives an external synchronization trigger pulse, a frequency divider of a baseband phase-locked loop in a chip is reset, so that the output of the baseband phase-locked loop is locked to a fixed phase. When the external trigger pulse keeps synchronous, the synchronous sampling clocks in the SOC can be ensured, and amplitude and phase errors caused by local oscillator wiring errors and the inconsistency of radio frequency receiving and transmitting channels can be eliminated through multi-channel calibration of the whole machine.
Preferably, the digital beam forming layer 4 includes a plurality of FIR filters and a plurality of multipliers, each FIR filter is connected to each corresponding multiplier through an electrical signal, the digital beam forming layer 4 is responsible for transceiving digital beam forming, the main function of the digital beam forming layer 4 is implemented inside the FPGA, at a receiving end, the digital beam forming device receives AD data of each radio frequency channel, amplitude weighting is performed on each channel by using the multipliers, each phase is adjusted by using the FIR filters, and the channel data are summed to obtain a digital synthesis receiving beam. At the transmitting end, the digital beam former generates amplitude and phase data of each channel according to the transmitting beam direction and side lobe requirements, and sends the amplitude and phase data to a DAC of the radio frequency SOC for digital/analog conversion, so as to generate a required radio frequency signal, as shown in fig. 5 and 6.
Preferably, the digital beamforming layer further includes a secondary power supply, a data receiving interface, and a data transmitting interface, where the secondary power supply is configured to convert an externally input 28V power supply into a +5V, +3.3V, or +1.8V power supply required by the digital phased array system, the data receiving interface and the data transmitting interface are both network ports, the data receiving interface is configured to receive beam pointing information and dwell time information sent from the outside, and the data transmitting interface is configured to transmit current state information of the digital phased array system to the outside.
The 16-channel digital phased array system is taken as the following working process:
firstly, executing a calibration flow after power-on, wherein calibration is carried out in a mode of calibrating transmission first and then calibrating reception, specifically, an FPGA in a digital beam forming layer controls a calibration network to be in a receiving state, 16 radio frequency channels enter a transmitting state, namely, calibration receiving channels are opened, and the calibration receiving channels are controlled to be sequentially connected with the 16 radio frequency transmitting channels according to a certain time interval, each radio frequency transmitting channel transmits signals with the same amplitude, the same initial phase and the same frequency, the calibration receiving channels sequentially receive radio frequency signals transmitted by the radio frequency transmitting channels, convert the radio frequency signals into digital signals, analyze the amplitude phase difference of each signal through FFT (fast Fourier transform algorithm), count in a transmission calibration table, and at this moment, finish transmission calibration;
secondly, the FPGA in the digital beam forming layer controls the calibration network to be in a transmitting state, the 16 radio frequency channels enter a receiving state, namely the calibration transmitting channel is opened, and the calibration transmitting channel is controlled to be sequentially connected with the 16 radio frequency receiving channels according to a certain time interval, the calibration transmitting channel transmits signals with the same amplitude, the same initial phase and the same frequency each time, the radio frequency receiving channels sequentially receive the radio frequency signals transmitted by the calibration transmitting channel and convert the radio frequency signals into digital signals, the amplitude phase difference of each signal is analyzed through FFT (fast Fourier transform), a receiving calibration table is counted, and at this moment, the receiving calibration is finished;
thirdly, the digital beam forming layer receives control information of the master control, wherein the control information comprises a transmitting beam pointing direction, a transmitting beam residing time length, a receiving beam pointing direction and a receiving beam residing time length;
fourthly, the digital beam former calculates a gain phase configuration table of each transmitting channel according to the received transmitting beam direction, adds the gain phase configuration table and the transmitting calibration table to obtain a corrected gain phase configuration table, configures multiplier multiplication factors of each transmitting channel according to the gain of the table, and configures FIR filter coefficients of each transmitting channel according to the phase of the table; after the configuration is finished, the digital beam former records that the time is T0, and times according to the received transmit beam dwell duration TI, when the time is T0+ T1, the transmit beam forming is finished, and each transmit channel is closed;
fifthly, the digital beam former calculates a gain phase configuration table of each receiving channel according to the received receiving beam direction, adds the gain phase configuration table and the receiving calibration table to obtain a corrected gain phase configuration table, configures multiplier multiplication factors of each receiving channel according to the gain of the table, and configures FIR filter coefficients of each receiving channel according to the phase of the table; after the configuration is finished, the digital beam former records that the time is T0, and times according to the received transmit beam dwell time T2, when the time reaches T0+ T2, the receive beam forming is finished, and all receive channels are closed;
and sixthly, repeating the second step to the fifth step to obtain any angle scanning and any weighting side lobe directional diagram of the antenna.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can readily practice the invention as shown and described in the drawings and detailed description herein; however, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims; meanwhile, any changes, modifications, and evolutions of the equivalent changes of the above embodiments according to the actual techniques of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (8)
1. The high-integration-level digital phased array system is characterized by comprising a flat antenna array layer (1), a matrix switch calibration network layer (2), a radio frequency transceiving channel layer (3) based on radio frequency SOC and a digital beam forming layer (4), wherein the flat antenna array layer (1) is connected with the matrix switch calibration network layer (2) through radio frequency signals, the matrix switch calibration network layer (2) is connected with the radio frequency transceiving channel layer (3) based on the radio frequency SOC through radio frequency signals and high-speed digital signals, and the radio frequency transceiving channel layer (3) based on the radio frequency SOC is connected with the digital beam forming layer (4) through the high-speed digital signals.
2. The highly integrated digital phased array system according to claim 1, wherein the planar antenna array layer (1) comprises an N-element antenna array, a microstrip element and a metal back plate, wherein the feed port of each element antenna in the N-element antenna array is fixedly connected to the microstrip element, the feed mode of each element antenna is a feedback, and the microstrip element is mounted on the surface of the metal back plate.
3. The high-integration digital phased array system according to claim 1, wherein the matrix switch calibration network layer (2) comprises a calibration transmitting channel, a calibration receiving channel and a matrix switch network, the matrix switch calibration network layer (2) is of a planar PCB structure, the matrix switch network comprises a high-speed bus connector, a plurality of SMA connectors and a plurality of SMP connectors, and the high-speed bus connector is used for transmitting control signals from the FPGA and controlling the calibration transmitting and receiving channels to work in a time-sharing manner; the first SMA connectors are distributed at the left end and the right end of the PCB and used for connecting a radio frequency receiving and transmitting channel layer (3) based on a radio frequency SOC; a plurality of SMP connectors are distributed at the middle position of the PCB, and the plurality of SMP connectors are used for connecting signals to the N-unit antenna array.
4. A highly integrated digital phased array system as claimed in claim 3, characterised in that the matrix switch calibration network layer (2) further comprises SP8T and a plurality of SPDT switches, the SP8T and the plurality of SPDT switches being arranged to control the routing of signals in the matrix switch calibration network layer (2).
5. The high-integration digital phased array system according to claim 1, wherein the radio frequency SOC-based radio frequency transceiving channel layer (3) is a planar PCB structure, the radio frequency SOC-based radio frequency transceiving channel layer (3) comprises a control signal connector, a plurality of second SMA connectors, two high-speed signal connectors and a plurality of radio frequency SOC chips, the control signal connector is connected with the matrix switch calibration network layer (2) and is used for transmitting a control signal from the FPGA to control the matrix switch calibration network layer (2) to operate in a time-sharing manner; the second SMA connectors are distributed at the left end and the right end of the PCB and are used for connecting the matrix switch calibration network layer (2); two high-speed signal connectors are distributed in the middle of the PCB, are connected with the digital beam forming layer (4), and are used for transmitting baseband data from the ADC and the DAC to the beam forming layer and bridging control signals of the FPGA.
6. The highly integrated digital phased array system according to claim 5, wherein each RF SOC chip comprises a receive front-end, a transmit front-end, a receive conversion channel, a transmit conversion channel, a BB PLL, an RX PLL, a TX PLL, an ADC data converter, a DAC data converter, a signal output of said receive front-end is electrically connected to a signal input of said receive conversion channel, a signal output of said receive conversion channel is electrically connected to a signal input of said ADC data converter, a signal output of said RX PLL is electrically connected to a signal input of said receive conversion channel, a signal output of said DAC data converter is electrically connected to a signal input of said transmit conversion channel, a signal output of said transmit conversion channel is electrically connected to a signal input of said transmit front-end, the signal output end of the TX phase-locked loop is in electric signal connection with the signal input end of the transmitting frequency conversion channel, and the signal output end of the BB phase-locked loop is in electric signal connection with the signal input ends of the ADC data converter and the DAC data converter respectively.
7. A highly integrated digital phased array system as claimed in claim 1, characterized in that the digital beam forming layer (4) comprises a plurality of FIR filters and a plurality of multipliers, each FIR filter being electrically connected to each corresponding multiplier.
8. The highly integrated digital phased array system according to claim 1, wherein the digital beam forming layer further comprises a secondary power supply, a receiving data interface and a transmitting data interface, the secondary power supply is used for converting an externally input 28V power supply into a +5V, +3.3V or +1.8V power supply required by the digital phased array system, the receiving data interface and the transmitting data interface are both network ports, the receiving data interface is used for receiving beam pointing information and dwell time information transmitted from the outside, and the transmitting data interface is used for transmitting current state information of the digital phased array system to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110694715.1A CN113451776B (en) | 2021-06-22 | 2021-06-22 | High-integration digital phased array system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110694715.1A CN113451776B (en) | 2021-06-22 | 2021-06-22 | High-integration digital phased array system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113451776A true CN113451776A (en) | 2021-09-28 |
| CN113451776B CN113451776B (en) | 2024-03-26 |
Family
ID=77812296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110694715.1A Active CN113451776B (en) | 2021-06-22 | 2021-06-22 | High-integration digital phased array system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113451776B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114614275A (en) * | 2022-05-11 | 2022-06-10 | 成都锐芯盛通电子科技有限公司 | HTCC dual-beam tile-type airtight SIP module |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024143A (en) * | 2015-08-06 | 2015-11-04 | 中国电子科技集团公司第三十八研究所 | Chip-type Ka-frequency band wide-angle scanning satellite communication antenna |
| WO2015172730A1 (en) * | 2014-05-14 | 2015-11-19 | 电信科学技术研究院 | Active antenna associated device and system, and transmitting and receiving calibration method |
| CN105390814A (en) * | 2015-10-18 | 2016-03-09 | 中国电子科技集团公司第十研究所 | Active phased array antenna with internal calibration network |
| CN105655725A (en) * | 2016-03-14 | 2016-06-08 | 中国电子科技集团公司第三十八研究所 | Two-dimensional expandable chip type active array antenna |
| CN106654541A (en) * | 2017-02-20 | 2017-05-10 | 成都瑞迪威科技有限公司 | Millimeter-wave 64 array element tile type phased array antenna |
| US20180115087A1 (en) * | 2016-10-26 | 2018-04-26 | Movandi Corporation | Phased Array Antenna Panel with Configurable Slanted Antenna Rows |
| US20180175916A1 (en) * | 2016-03-14 | 2018-06-21 | Ross Sciences Limited | Hybrid Beam-Forming Antenna Array using Selection Matrix for Antenna Phase Calibration |
| CN208384112U (en) * | 2018-07-26 | 2019-01-15 | 北京冠群桦成信息技术有限公司 | A kind of on-chip antenna millimeter audiolocator |
| EP3460908A1 (en) * | 2017-09-25 | 2019-03-27 | Gapwaves AB | Phased array antenna |
| CN110739537A (en) * | 2019-09-28 | 2020-01-31 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | High-density high-integration millimeter wave tile-type phase-controlled antenna T component |
| CN111541471A (en) * | 2020-04-21 | 2020-08-14 | 中国电子科技集团公司第五十四研究所 | Digital multi-beam phased-array antenna device for ad hoc network communication |
| CN112382862A (en) * | 2021-01-15 | 2021-02-19 | 四川斯艾普电子科技有限公司 | Tile type multi-beam phased array antenna |
-
2021
- 2021-06-22 CN CN202110694715.1A patent/CN113451776B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015172730A1 (en) * | 2014-05-14 | 2015-11-19 | 电信科学技术研究院 | Active antenna associated device and system, and transmitting and receiving calibration method |
| CN105024143A (en) * | 2015-08-06 | 2015-11-04 | 中国电子科技集团公司第三十八研究所 | Chip-type Ka-frequency band wide-angle scanning satellite communication antenna |
| CN105390814A (en) * | 2015-10-18 | 2016-03-09 | 中国电子科技集团公司第十研究所 | Active phased array antenna with internal calibration network |
| CN105655725A (en) * | 2016-03-14 | 2016-06-08 | 中国电子科技集团公司第三十八研究所 | Two-dimensional expandable chip type active array antenna |
| US20180175916A1 (en) * | 2016-03-14 | 2018-06-21 | Ross Sciences Limited | Hybrid Beam-Forming Antenna Array using Selection Matrix for Antenna Phase Calibration |
| US20180115087A1 (en) * | 2016-10-26 | 2018-04-26 | Movandi Corporation | Phased Array Antenna Panel with Configurable Slanted Antenna Rows |
| CN106654541A (en) * | 2017-02-20 | 2017-05-10 | 成都瑞迪威科技有限公司 | Millimeter-wave 64 array element tile type phased array antenna |
| EP3460908A1 (en) * | 2017-09-25 | 2019-03-27 | Gapwaves AB | Phased array antenna |
| CN208384112U (en) * | 2018-07-26 | 2019-01-15 | 北京冠群桦成信息技术有限公司 | A kind of on-chip antenna millimeter audiolocator |
| CN110739537A (en) * | 2019-09-28 | 2020-01-31 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | High-density high-integration millimeter wave tile-type phase-controlled antenna T component |
| CN111541471A (en) * | 2020-04-21 | 2020-08-14 | 中国电子科技集团公司第五十四研究所 | Digital multi-beam phased-array antenna device for ad hoc network communication |
| CN112382862A (en) * | 2021-01-15 | 2021-02-19 | 四川斯艾普电子科技有限公司 | Tile type multi-beam phased array antenna |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114614275A (en) * | 2022-05-11 | 2022-06-10 | 成都锐芯盛通电子科技有限公司 | HTCC dual-beam tile-type airtight SIP module |
| CN114614275B (en) * | 2022-05-11 | 2022-09-20 | 成都锐芯盛通电子科技有限公司 | HTCC dual-beam tile-type airtight SIP module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113451776B (en) | 2024-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111030748B (en) | Digital beam forming terminal device for satellite communication | |
| EP1891700B1 (en) | True time delay phase array radar using rotary clocks and electronic delay lines | |
| KR101829974B1 (en) | System and method for high-speed analog beamforming | |
| EP2589108B1 (en) | Low cost, active antenna arrays | |
| EP3889636A1 (en) | Radar system and control method therefor | |
| EP3502733B1 (en) | Radar system comprising coupling device | |
| WO2008000318A1 (en) | Antenna array calibration | |
| EP4082079B1 (en) | Phased array module | |
| WO2021018057A1 (en) | Multi-channel phase synchronization device for base station, method, and base station | |
| CN105510888A (en) | Radar signal simulation method based on digital synthesis, and simulator | |
| CN111245472B (en) | Radio frequency transceiver chip, and synchronization system and method for radio frequency transceiver chip | |
| D'Amato et al. | Toward a novel architecture for beam steering of active phased-array antennas | |
| CN113451776A (en) | High-integration-level digital phased array system | |
| CN113484828A (en) | Cascade extended millimeter wave sensor chip | |
| US11212016B1 (en) | Distribution of inter/intra calibration signals for antenna beamforming signals | |
| Wu et al. | An X-band Scalable 4× 4 Digital Phased Array Module using RF SoC and Antenna-in-Package | |
| CN209690498U (en) | A kind of signal source of S-band wave observation radar | |
| CN113328265A (en) | Extensible E-band digital active array | |
| Ji et al. | The synchronization design of multi-channel digital TR module for phased array radar | |
| CN115799843A (en) | W-band digital active antenna array | |
| KR101997988B1 (en) | Hybrid Type Transceiver for Broadband Large Area Beamforming | |
| Marinho et al. | Application of digital beamforming to software defined radio 5G/radar systems | |
| Leibetseder et al. | A 79GHz 4RX-2TX SiGe-Integrated Sequential Sampling Pulse Radar | |
| CN113036462B (en) | C-band broadband digital multi-beam array antenna system | |
| Krishna et al. | Bi-Directional True Time Delay Core Chip for Phased Array Radars |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |