CN117747565A - Structure for conducting and radiating in stacked chip units and manufacturing method thereof - Google Patents
Structure for conducting and radiating in stacked chip units and manufacturing method thereof Download PDFInfo
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- CN117747565A CN117747565A CN202311835320.4A CN202311835320A CN117747565A CN 117747565 A CN117747565 A CN 117747565A CN 202311835320 A CN202311835320 A CN 202311835320A CN 117747565 A CN117747565 A CN 117747565A
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- heat
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- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004020 conductor Substances 0.000 claims abstract description 117
- 239000002184 metal Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 238000005520 cutting process Methods 0.000 claims abstract description 41
- 230000017525 heat dissipation Effects 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005452 bending Methods 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010931 gold Substances 0.000 claims abstract description 13
- 229910052737 gold Inorganic materials 0.000 claims abstract description 13
- 230000001070 adhesive effect Effects 0.000 claims abstract description 10
- 239000000853 adhesive Substances 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 claims abstract description 7
- 238000004806 packaging method and process Methods 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 239000003292 glue Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000004513 sizing Methods 0.000 claims description 2
- 238000000605 extraction Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 229920000297 Rayon Polymers 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a structure for conducting and radiating heat in a stacked chip unit.A metal plate is arranged between a WB chip and an FC chip which are stacked up and down in the chip unit, the metal plate is communicated with a back gold surface of the lower surface of the WB chip, the outer end of the metal plate extends downwards to be bent and connected with a metal conductor with conducting and radiating functions in a substrate, and the current of the back gold surface of the WB chip and the heat generated by the WB chip and the FC chip are guided to the metal conductor in the substrate through the metal plate. The metal plate is adhered and communicated with the gold-back surface of the lower surface of the WB chip through conductive adhesive. An inner heat conductor is arranged in an inner space formed between the L-shaped downward bending of the metal plate and the end part of the FC chip, and the inner heat conductor is provided with a first exposed heat dissipation cutting surface on two sides of the metal plate after the sealing and cutting are completed. The advantages are that: the problem of current extraction in a WB chip and FC chip stacked chip unit is well solved; the problem of heat dissipation after the WB chip and the FC chip are stacked and packaged is well solved.
Description
Technical Field
The invention relates to a structure for conducting and radiating in stacked chip units and a manufacturing method thereof, and belongs to the technical field of chip stacking.
Background
When WB and FC chips are packaged in a multi-chip manner, the two chips can be packaged in a side-by-side or stacked manner. The parallel packaging is that a WB chip is connected with a substrate through silver paste or Bonding glue, and an FC chip is connected with the substrate through a flip-chip mode; the stack package is usually formed by flip-chip connection of the FC chip to the substrate, and the WB chip is stacked over the FC chip and connected by Bonding glue. However, when the package size is limited and signals need to be led out from both sides of the WB chip, the two conventional package methods are not applicable, where the package size required by the parallel package method is too large to meet the limited package size requirement, and the stacked package method has the problem that the signals on the back (non-active side) of the WB chip cannot be led out.
In addition, the parallel packaging is that the WB chip is connected with the substrate through silver paste or Bonding glue, heat generated by the WB chip can be conducted and emitted to a metal conductor in the substrate nearby, the WB chip is far away from the substrate after the stacked packaging is implemented and limited by the packaging glue layer, the heat emission generated by the WB chip is difficult to solve, and after the WB chip is stacked with the FC chip, part of heat generated by the FC chip is overlapped with heat generated by the FC chip, so that the difficulty of solving the problem is further increased.
The prior art published application number 202210825966.3 discloses a method for manufacturing a package structure, comprising the steps of: bonding wires are led in the PAD position of the bare chip, and after bonding and ball implantation are carried out, solder balls are formed; carrying out plastic package on the whole bare chip subjected to the ball bonding and ball planting to form a plastic package body; grinding the plastic package body to the position of the solder ball; carrying out fanout wiring on the bare chip; and stacking bare chips layer by layer, wherein each layer of bare chips are subjected to plastic package or film pressing in the stacking process, and wiring is carried out on each layer of bare chips in the stacking process, so that a finished product is obtained. Through the multiple buried chips and the multiple wiring technology, the packaging integration level is increased, meanwhile, the signal transmission path is shortened, the electrical property of the product is improved, meanwhile, the product has high heat dissipation property, the electrical and thermal performance of the product is improved, and the product integration level is increased; and bonding wires are introduced to carry out pressure welding and ball planting, grinding is carried out after plastic packaging, the flow is simpler, the cost and development period are saved, and the service life is longer. The specific technical scheme of the document also discloses a heat dissipation mode of a heat dissipation carrier, but the problem of low heat dissipation efficiency still exists, and the heat dissipation carrier has obvious differences from the application in terms of technical effect, structural mode and manufacturing process.
Disclosure of Invention
The invention aims to solve the technical problems that: how to solve the problems of current extraction and heat dissipation of the WB chip and the FC chip stacked package.
Aiming at the problems, the technical scheme provided by the invention is as follows:
a metal plate is arranged between a WB chip and an FC chip which are stacked up and down in the chip unit, the metal plate is communicated with a back gold surface of the lower surface of the WB chip, the outer end of the metal plate extends downwards to be bent and connected with a metal conductor with a conductive heat dissipation function in a substrate, and current of the back gold surface of the WB chip and heat generated by the WB chip and the FC chip are guided to the metal conductor in the substrate through the metal plate.
Further, the outer end of the metal plate is bent downwards in an L shape.
Further, the metal plate is adhered and communicated with the back gold surface of the lower surface of the WB chip through conductive adhesive.
The metal plate is connected with the upper surface of the FC chip through adhesive.
Further, an inner space formed between the L-shaped downward bending of the metal plate and the end part of the FC chip is provided with an inner heat conductor, and after the sealing and cutting are completed, the inner heat conductor is positioned at two sides of the metal plate and provided with a first exposed heat dissipation cutting surface.
Further, two outer side surfaces which are formed by bending the metal plate downwards in an L shape and are intersected in a right angle are provided with L-shaped outer heat conductors, and after the sealing and cutting are completed, the outer heat conductors are positioned on two sides of the metal plate and are provided with exposed radiating cutting surfaces II.
Further, the inner heat conductor and the outer heat conductor are made of semiconductor silicon, and an insulating interval capable of being filled with sizing materials during packaging is arranged between each inner heat conductor and the metal plate.
Further, the inner sides of the two ends of the outer heat conductor are respectively provided with a spacer which extends inwards and is used for keeping the interval between the outer heat conductor and the inner heat conductor, when the heat exchanger is applied, the spacers at the two ends of the outer heat conductor are attached to the inner heat conductor, and an L-shaped cavity which can accommodate the L-shaped bending part of the outer end of the metal plate is formed between the outer heat conductor and the inner heat conductor between the two spacers.
The manufacturing method of the structure for conducting electricity and radiating heat in the stacked chip units comprises the steps of manufacturing an inner heat conductor and an outer heat conductor of each chip unit according to the total length of a row of a plurality of chip units arranged on a substrate to be cut before packaging and cutting, manufacturing an inner heat conductor whole section which can be divided into inner heat conductors belonging to each chip unit and an outer heat conductor whole section which can be divided into outer heat conductors belonging to each chip unit, and cutting the inner heat conductor whole section and the outer heat conductor whole section together when the chip units are divided after packaging is completed.
Further, the method comprises the following steps:
the method comprises the steps of firstly, fixing FC chips of all chip units on a substrate to be cut according to a set matrix;
secondly, placing the whole section of the inner heat conductor at one end of each row of FC chips, and bonding the whole section of the inner heat conductor with the FC chips by using viscose;
thirdly, placing and fixing L-shaped metal plates on each FC chip, and enabling the whole section of the inner heat conductor to be positioned in an inner space formed by bending the metal plates in an L shape;
fourthly, placing and fixing WB chips on the metal plates;
fifthly, placing the whole section of the outer heat conductor on the outer side of the L-shaped bending of the outer end of each metal plate, and bonding the whole section of the outer heat conductor with the WB chip by using viscose;
sixthly, injecting glue and packaging all devices on the substrate according to requirements;
and seventh, cutting to obtain single chip units, wherein the conductive and heat-dissipating structure of each chip unit is provided with a first exposed heat-dissipating cutting surface and a second exposed heat-dissipating cutting surface which are positioned on two sides of the metal plate.
Further: the cutting lines are arranged on the whole section of the outer heat conductor and are arranged at the position of each spacer, so that the cut-out heat dissipation cutting surface II is arranged on the section of the spacer, and the splicing gap between the heat dissipation cutting surface I and the heat dissipation cutting surface II is further reduced.
Advantageous effects
1. The problem of current extraction in a WB chip and FC chip stacked chip unit is well solved;
2. the problem of heat dissipation after the WB chip and the FC chip are stacked and packaged is well solved.
Drawings
Fig. 1 is a schematic plan view of a structural blank of a chip unit in which WB chips and FC chips are stacked in the first embodiment;
fig. 2 is a schematic perspective view of a structure blank array of a plurality of chip units stacked by WB chips and FC chips on a substrate, wherein the structure blank of the plurality of chip units of the array is packaged and cut to form a single chip unit;
fig. 3 is a partially cross-sectional schematic view of a structural blank of a chip unit in which WB chips and FC chips are stacked in the second embodiment;
fig. 4 is a schematic view showing the whole section of the inner heat conductor, the whole section of the outer heat conductor and the metal plate in the second embodiment;
FIG. 5 is a schematic diagram showing the combination of the whole inner conductor and the whole outer conductor in the second embodiment;
FIG. 6 is a schematic view taken along line A-A of FIG. 5;
fig. 7 is a schematic perspective view of a structure blank array of a plurality of chip units stacked by WB chips and FC chips on a substrate in the second embodiment, wherein the structure blank of the plurality of chip units in the array is packaged and cut to form a single chip unit;
fig. 8 is a schematic perspective view of a packaged and diced chip unit in accordance with the second embodiment.
In the figure: 1. a substrate; 101. a metal conductor; 2. WB chip; 201. a back gold surface; 202. WB wire; 3. an FC chip; 4. a metal plate; 5. conducting resin; 6. the whole section of the inner heat conductor; 601. an inner heat conductor; 6011. a first radiating cutting surface; 7. the whole section of the outer heat conductor; 701. an outer heat conductor; 7011. a second radiating cutting surface; 7012. a spacer; 7013. cutting lines; 8. an insulation interval; 9. an L-shaped cavity; 100. and a chip unit.
Detailed Description
The chip unit 100 is formed by stacking WB chips 2 and FC chips 3 on a substrate 1 and encapsulating them with glue.
The invention is further described below with reference to examples and figures:
example 1
As shown in fig. 1 and 2, in a structure for conducting heat dissipation in a stacked chip unit, a metal plate 4 is provided between WB chips 2 and FC chips 3 stacked one above the other in the chip unit 100, the metal plate 4 communicates with a back gold surface 201 on the lower surface of the WB chips 2, the outer end thereof extends downward and bends to connect with a metal conductor 101 having a conducting heat dissipation function in a substrate 1, and the current on the back gold surface of the WB chips 2 and the heat generated by the WB chips 2 and the FC chips 3 are conducted to the metal conductor 101 in the substrate 1 via the metal plate 4. Thus, the current guiding problem of the back gold surface of the WB chip 2 is solved, and meanwhile, the heat guiding problem of the heat generated between the WB chip 2 and the FC chip 3 is solved by utilizing the heat conductivity of the metal plate 4.
Furthermore, the outer end of the metal plate 4 is bent downwards in an L shape, so that the metal plate is convenient to bend uniformly by 90 degrees during processing, and the end part which is vertically downwards after bending is also convenient to connect with a metal conductor in the substrate 1.
The metal plate 4 is bonded and connected with the back gold surface 201 of the lower surface of the WB chip 2 by the conductive adhesive 5. Thus, the adhesive effect and the conductive effect are achieved. The metal plate 4 and the upper surface of the FC chip 3 may be connected by other adhesives, or may be connected by conductive adhesives.
The WB chip 2 has WB lines 202 on its upper surface connected to corresponding circuits in the substrate 1, and in the chip units stacked in this embodiment, the WB lines are still connected to corresponding circuits in the substrate 1 in a conventional manner.
Example two
As shown in fig. 3-8, the difference from the first embodiment is that an inner space formed between the L-shaped bent metal plate 4 and the end of the FC chip 3 is provided with an inner heat conductor 601, and after the sealing and cutting are completed, the inner heat conductor 601 is located at two sides of the metal plate 4 and has a exposed heat dissipation cutting surface 6011. An L-shaped outer heat conductor 701 is arranged on the outer side surfaces of the two right-angle intersecting sides formed by bending the metal plate 4 downwards in an L shape, and the outer heat conductor 701 is provided with a second exposed heat dissipation cutting surface 7011 on two sides of the metal plate 4 after the sealing and cutting are completed. Thus, after the chip unit 100 is encapsulated by the resin, the exposed first heat dissipation cut surface 6011 and the second heat dissipation cut surface 7011 have better heat dissipation properties.
The material of the inner conductor 601 and the outer conductor 701 is semiconductor silicon, and an insulating space 8 capable of filling glue material when being packaged is arranged between the inner conductor 601 and the metal plate 4. Since the semiconductor silicon still has a certain conductivity, it is necessary to reserve an insulation space 8 between the inner conductor 601 and the outer conductor 701 and the metal plate 4, and fill resin glue in the reserved space during packaging.
The inner sides of the two ends of the outer heat conductor 701 are respectively provided with a spacer 7012 which extends inwards and is used for keeping the distance between the outer heat conductor 701 and the inner heat conductor 601, when the heat conductor is applied, the spacers 7012 at the two ends of the outer heat conductor 701 are attached to the inner heat conductor 601, and an L-shaped cavity 9 which can accommodate the L-shaped bending part of the outer end of the metal plate 4 is formed between the outer heat conductor 701 and the inner heat conductor 601 between the two spacers 7012. This facilitates the securing of the width of the L-shaped cavity 9 during manufacture, and further ensures that a standard insulation space 8 is reserved between the inner 601 and outer 701 conductors and the metal plate 4.
Here, the width of the insulating space 8 is only sufficient for insulation, and too wide a space affects the heat conduction effect of the metal plate 4 to the inner heat conductor 601 and the outer heat conductor 701.
The above method for manufacturing the structure for conducting and dissipating heat in the stacked chip units, wherein the manufacturing of the inner heat conductor 601 and the outer heat conductor 701 of the chip units 100 is to manufacture the inner heat conductor whole section 6 which can be divided into the inner heat conductor 601 belonging to each chip unit 100 and the outer heat conductor whole section 7 which can be divided into the outer heat conductor 701 belonging to each chip unit 100 according to the total length of the array of the plurality of chip units 100 on the substrate 1 to be cut before packaging and cutting, and cut the inner heat conductor whole section 6 and the outer heat conductor whole section 7 together when the chip units 100 are divided after packaging. In this way, firstly, the chip unit 100 is easy to manufacture quickly, and the chip unit 100 is prevented from being assembled with a single inner heat conductor 601 and a single outer heat conductor 701, and secondly, the chip unit 100 is prevented from being assembled with a single inner heat conductor 601 and a single outer heat conductor 701, and then the end faces of the inner heat conductor 601 and the outer heat conductor 701 are sealed by glue and cannot be exposed to influence the heat dissipation effect during packaging.
The manufacturing method of the structure for conducting and radiating in the stacked chip units of the embodiment comprises the following steps:
first, fixing FC chips 3 of each chip unit 100 on a substrate 1 to be cut according to a set matrix;
secondly, placing an integral section 6 of the inner heat conductor at one end of each row of FC chips 3, and bonding the integral section 6 of the inner heat conductor with the FC chips 3 by using viscose;
thirdly, placing and fixing an L-shaped metal plate 4 on each FC chip 3, and enabling the whole section 6 of the inner heat conductor to be positioned in an inner space formed by bending the metal plate 4 in an L shape;
a fourth step of placing and fixing WB chips 2 on the respective metal plates 4;
fifthly, placing the whole section 7 of the outer heat conductor on the outer side of the L-shaped bending of the outer end of each metal plate 4, and bonding the whole section 7 of the outer heat conductor with the WB chip 2 by using viscose;
sixthly, injecting glue and packaging all devices on the substrate 1 according to requirements;
seventh, the individual chip units 100 are obtained by dicing, so that the conductive and heat-dissipating structure of each chip unit 100 has a first heat-dissipating dicing surface 6011 and a second heat-dissipating dicing surface 7011 exposed at both sides of the metal plate 4.
Further, a cutting line 7013 is arranged on the whole section 7 of the outer heat conductor, the cutting line 7013 is arranged at each spacer 7012, so that the cut radiating cutting surface II 7011 is positioned on the section of the spacer 7012, and the splicing gap between the radiating cutting surface I6011 and the radiating cutting surface II 7011 is further reduced, the exposed radiating surface can be further enlarged, and the radiating effect can be obtained to the greatest extent.
The above embodiments are only for the purpose of more clearly describing the present invention and should not be construed as limiting the scope of the present invention, and any equivalent modifications should be construed as falling within the scope of the present invention.
Claims (10)
1. A structure for conducting heat dissipation in a stacked chip unit, characterized by: a metal plate (4) is arranged between a WB chip (2) and an FC chip (3) which are stacked up and down in a chip unit (100), the metal plate (4) is communicated with a back gold surface (201) of the lower surface of the WB chip (2), the outer end of the metal plate is downwards extended and bent to be connected with a metal conductor (101) with a conductive heat dissipation function in a substrate (1), and the current of the back gold surface of the WB chip (2) and the heat generated by the WB chip (2) and the FC chip (3) are guided to the metal conductor (101) in the substrate (1) through the metal plate (4).
2. The structure for conductive heat dissipation in a stacked chip unit of claim 1, wherein: the outer end of the metal plate (4) is bent downwards in an L shape.
3. The structure for conductive heat dissipation in a stacked chip unit of claim 1, wherein: the metal plate (4) is adhered and communicated with the back gold surface (201) of the lower surface of the WB chip (2) through the conductive adhesive (5).
4. The structure for conductive heat dissipation in a stacked chip unit of claim 2, wherein: an inner space formed between the L-shaped downward bending of the metal plate (4) and the end part of the FC chip (3) is provided with an inner heat conductor (601), and after the sealing and cutting are completed, the inner heat conductor (601) is positioned at two sides of the metal plate (4) and is provided with a first exposed heat dissipation cutting surface (6011).
5. The structure for conductive heat dissipation in a stacked chip unit of claim 4, wherein: the outer side surfaces of the metal plate (4) which are formed by bending downwards in an L shape and are intersected in a right angle are provided with L-shaped outer heat conductors (701), and after the sealing and cutting are completed, the outer heat conductors (701) are positioned on two sides of the metal plate (4) and are provided with exposed heat dissipation cutting surfaces II (7011).
6. The structure for conductive heat dissipation in a stacked chip unit of claim 5, wherein: the inner heat conductor (601) and the outer heat conductor (701) are made of semiconductor silicon, and an insulating interval (8) capable of being filled with sizing materials during packaging is arranged between each inner heat conductor and the metal plate (4).
7. The structure for conductive heat dissipation in a stacked chip unit of claim 6, wherein: the inner sides of the two ends of the outer heat conductor (701) are respectively provided with a spacer (7012) which extends inwards and is used for keeping the interval between the outer heat conductor (701) and the inner heat conductor (601), when the heat radiator is applied, the spacers (7012) at the two ends of the outer heat conductor (701) are attached to the inner heat conductor (601), and an L-shaped cavity (9) which can accommodate the L-shaped bending part at the outer end of the metal plate (4) is formed between the outer heat conductor (701) and the inner heat conductor (601) between the two spacers (7012).
8. The method of fabricating a structure for conducting heat dissipation in a stacked chip unit of claim 7, wherein: the manufacturing of the inner heat conductor (601) and the outer heat conductor (701) of the chip units (100) is to manufacture an inner heat conductor whole section (6) which can be divided into the inner heat conductors (601) belonging to the chip units (100) and an outer heat conductor whole section (7) which can be divided into the outer heat conductors (701) belonging to the chip units (100) according to the total length of a row of a plurality of chip units (100) arranged on a substrate (1) to be cut before packaging and cutting in advance, and cut the inner heat conductor whole section (6) and the outer heat conductor whole section (7) together when the packaging is completed and the chip units (100) are divided.
9. The method of fabricating a structure for conductive heat dissipation in a stacked chip unit of claim 8, comprising the steps of:
firstly, fixing FC chips (3) of each chip unit (100) on a substrate (1) to be cut according to a set matrix;
secondly, placing the whole section (6) of the inner heat conductor at one end of each row of FC chips (3), and bonding the whole section (6) of the inner heat conductor with the FC chips (3) by using adhesive;
thirdly, placing and fixing an L-shaped metal plate (4) on each FC chip (3), and enabling the whole section (6) of the inner heat conductor to be positioned in an inner space formed by bending the metal plate (4) in an L shape;
fourthly, placing and fixing WB chips (2) on the metal plates (4);
fifthly, placing an outer heat conductor whole section (7) on the outer side of the L-shaped bending of the outer end of each metal plate (4), and bonding the outer heat conductor whole section (7) with the WB chip (2) by using adhesive;
sixthly, injecting glue and packaging all devices on the substrate (1) according to requirements;
seventh, cutting to obtain single chip units (100), wherein the conductive and heat-dissipating structure of each chip unit (100) is provided with a first heat-dissipating cutting surface (6011) and a second heat-dissipating cutting surface (7011) which are exposed on two sides of the metal plate (4).
10. The method of fabricating a structure for conducting heat dissipation in a stacked chip unit of claim 9, wherein: cutting lines (7013) are arranged on the whole section (7) of the outer heat conductor, the cutting lines (7013) are arranged at each spacer (7012), and the cut radiating cutting surface II (7011) is located on the section of the spacer (7012), so that the splicing gap between the radiating cutting surface I (6011) and the radiating cutting surface II (7011) is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311835320.4A CN117747565A (en) | 2023-12-28 | 2023-12-28 | Structure for conducting and radiating in stacked chip units and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311835320.4A CN117747565A (en) | 2023-12-28 | 2023-12-28 | Structure for conducting and radiating in stacked chip units and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117747565A true CN117747565A (en) | 2024-03-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311835320.4A Pending CN117747565A (en) | 2023-12-28 | 2023-12-28 | Structure for conducting and radiating in stacked chip units and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117747565A (en) |
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2023
- 2023-12-28 CN CN202311835320.4A patent/CN117747565A/en active Pending
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