CN117747450A - Semiconductor device, preparation method thereof and electronic device - Google Patents
Semiconductor device, preparation method thereof and electronic device Download PDFInfo
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- CN117747450A CN117747450A CN202311777245.0A CN202311777245A CN117747450A CN 117747450 A CN117747450 A CN 117747450A CN 202311777245 A CN202311777245 A CN 202311777245A CN 117747450 A CN117747450 A CN 117747450A
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Abstract
A semiconductor device, a method for manufacturing the same, and an electronic device, wherein the method comprises the following steps: providing a substrate, forming a device structure layer in the substrate, forming an interlayer dielectric layer on the device structure layer, and forming a top metal layer on the interlayer dielectric layer; etching the top metal layer to form a first metal pad and a second metal pad, the first metal pad and the second metal pad having sloped sidewall topography; forming a first passivation layer; patterning the first passivation layer to form a first opening in the first passivation layer; a second passivation layer is formed to cover the first passivation layer and has a second opening. According to the scheme, the first metal bonding pad and the second metal bonding pad with the inclined side wall morphology are formed, so that the stress of the side walls and the corners of the first metal bonding pad and the second metal bonding pad can be effectively relieved, the problems that the side walls and the corners of the first metal bonding pad and the second metal bonding pad are cracked and the like are avoided, and the reliability and the product yield of the device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.
Background
The main devices in Integrated Circuits (ICs), especially very large scale integrated circuits, are metal oxide field effect transistors (MOS), wherein silicon carbide crystals, such as 4H-SiC, are ideal materials for manufacturing high-voltage MOS due to the characteristics of large forbidden bandwidth, high critical breakdown electric field, high saturated electron drift speed and the like, so that the silicon carbide materials become research hotspots of international power semiconductor devices, and in the fields of high-power application occasions, such as high-speed railways, hybrid electric vehicles, intelligent high-voltage direct current transmission and the like, the silicon carbide devices are endowed with very high expectations.
In the related art, a passivation layer is often formed to protect the device, however, the passivation layer in the related art is easy to crack or even fall off, so that water vapor and impurity ions invade to cause the failure of the device, and further the yield of the product is reduced.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the problems existing at present, an aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a substrate, forming a device structure layer extending from a first surface of the substrate into the substrate in the substrate, forming an interlayer dielectric layer on the device structure layer, and forming a top metal layer on the interlayer dielectric layer;
etching the top metal layer to form a first metal pad and a second metal pad isolated from each other, wherein the first metal pad and the second metal pad have sloped sidewall topography;
forming a first passivation layer on the substrate, wherein the first passivation layer covers the first metal pad and the second metal pad;
patterning the first passivation layer to form a first opening in the first passivation layer exposing top surfaces of the first metal pad and the second metal pad portion;
a second passivation layer is formed on the substrate, the second passivation layer covering the first passivation layer and having a second opening exposing top surfaces of the first metal pad and the second metal pad portion.
Illustratively, the first passivation layer is formed using an atomic layer deposition method.
Illustratively, the material of the first passivation layer includes aluminum oxide.
Illustratively, the material of the second passivation layer comprises polyimide.
Illustratively, the semiconductor device comprises a silicon carbide MOS device.
Illustratively, the first metal pad comprises a source pad and the second metal pad comprises a gate pad.
Illustratively, a drain region is also formed in the substrate extending from the second surface of the substrate into the substrate, and a third metal pad is also formed on the drain region.
Another aspect of the present invention provides a semiconductor device comprising:
a substrate in which a device structure layer is formed extending from a first surface of the substrate into the substrate;
an interlayer dielectric layer on the device structure layer;
a first metal pad and a second metal pad isolated from each other on the interlayer dielectric layer, wherein the first metal pad and the second metal pad have sloped sidewall topography;
a first passivation layer covering sidewalls and a portion of top surfaces of the first and second metal pads;
and a second passivation layer covering the first passivation layer and having a second opening exposing top surfaces of the first and second metal pad portions.
Illustratively, the material of the first passivation layer comprises aluminum oxide and/or the material of the second passivation layer comprises polyimide.
In yet another aspect, the present invention provides an electronic apparatus including the semiconductor device described above.
According to the semiconductor device, the preparation method thereof and the electronic device, the first passivation layer and the second passivation layer are adopted to form double-layer protection on the device, and the stress of the side walls and the corners of the first metal bonding pad and the second metal bonding pad can be effectively relieved by forming the first metal bonding pad and the second metal bonding pad with inclined side wall morphology, so that the adhesion capability of the first passivation layer and the second passivation layer is improved, the problems that the side walls of the first metal bonding pad and the second metal bonding pad and the first passivation layer and the second passivation layer at the corners are cracked and the like are avoided, and the reliability and the product yield of the device are improved.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.
In the accompanying drawings:
fig. 1 shows a schematic cross-sectional view of a related art semiconductor device;
fig. 2 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3A to 3G are schematic cross-sectional views showing a semiconductor device obtained by sequentially carrying out a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In order to provide a thorough understanding of the present invention, detailed steps and structures will be presented in the following description in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
In the related art, as shown in fig. 1, a first metal pad 101 and a second metal pad 102 are formed on a substrate 100, and the first metal pad 101 and the second metal pad 102 are used for extracting a gate and a source respectively in a subsequent process; and a first passivation layer 103 covering sidewalls and a portion of the top surfaces of the first and second metal pads 101 and 102 and a second passivation layer 104 covering the first passivation layer 103 are formed, the first and second passivation layers 103 and 104 serving to protect the device from intrusion of moisture and impurity ions.
However, the inventors of the present application found that: the stress at the corners and the side walls of the first metal pad 101 and the second metal pad 102 is too large, so that the first passivation layer 103 and the second passivation layer 104 at the corners and the side walls of the first metal pad 101 and the second metal pad 102 are easy to crack or even fall off, and the like, thereby causing device failure and product yield reduction.
Accordingly, in view of the foregoing technical problems, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, which mainly includes the following steps:
step S1, providing a substrate, wherein a device structure layer extending from a first surface of the substrate to the substrate is formed in the substrate, an interlayer dielectric layer is formed on the device structure layer, and a top metal layer is formed on the interlayer dielectric layer;
step S2, etching the top metal layer to form a first metal pad and a second metal pad which are isolated from each other, wherein the first metal pad and the second metal pad have inclined side wall morphology;
step S3, forming a first passivation layer covering the first metal pad and the second metal pad on the substrate;
step S4, patterning the first passivation layer to form a first opening exposing the top surfaces of the first metal pad and the second metal pad part in the first passivation layer;
and S5, forming a second passivation layer on the substrate, wherein the second passivation layer covers the first passivation layer and is provided with a second opening exposing the top surfaces of the first metal pad and the second metal pad.
According to the preparation method of the semiconductor device, the first passivation layer and the second passivation layer are adopted to form double-layer protection on the device, and the first metal bonding pad and the second metal bonding pad with inclined side wall morphology are formed, so that the stress of the side walls and the corners of the first metal bonding pad and the second metal bonding pad can be effectively relieved, the adhesive capacity of the first passivation layer and the second passivation layer is improved, the problems that the side walls and the corners of the first metal bonding pad and the second metal bonding pad are cracked and the like are avoided, and the reliability and the product yield of the device are improved.
Example 1
Next, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to fig. 2 to 3G, wherein fig. 2 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 3A to 3G are schematic cross-sectional views of semiconductor devices obtained by sequentially performing the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Illustratively, the method of fabricating a semiconductor device of the present invention includes the steps of:
first, step S1 is performed to provide a substrate in which a device structure layer extending from a first surface of the substrate into the substrate is formed, an interlayer dielectric layer is formed on the device structure layer, and a top metal layer is formed on the interlayer dielectric layer. Specifically, as shown in fig. 3A, a device structure layer 301 extending from the surface of the substrate 300 into the substrate 300 is formed in the substrate 300, an interlayer dielectric layer 302 is formed on the device structure layer 301, and a top metal layer 303 is formed on the interlayer dielectric layer 302.
In one example, substrate 300 is a bulk silicon substrate, which may include at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductor, or substrate 300 may also comprise silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which substrate 300 may be formed are described herein, any material that may serve as substrate 300 falls within the spirit and scope of the present invention. In one embodiment, the substrate 300 may be of an N-type conductivity type, and in other embodiments, the substrate 300 may also be of a P-type conductivity type, and in particular, a suitable substrate may be selected according to the type of device. In one embodiment, the material of the substrate 300 is silicon carbide.
In one example, the semiconductor device of the present application includes a silicon carbide MOS device. Illustratively, taking the semiconductor device of the present application as a Vertical Diffusion Metal Oxide Semiconductor (VDMOS) as an example, the device structure layer 301 may include a gate structure, a body region, and a source region, wherein the source region is located within the body region. Illustratively, the body region is formed using a standard ion implantation process, which may be combined with a high energy ion implantation and a high temperature thermal annealing process. Illustratively, the source region may be formed by photolithography and by an ion implantation process, followed by a rapid thermal annealing process, with a high temperature of 900 to 1050 degrees celsius being used to activate the dopants within the source region and simultaneously repair the lattice structure of the surface of the semiconductor substrate damaged during each ion implantation process. Illustratively, the body region has a conductivity type different from the substrate, the source region has the same conductivity type as the substrate, e.g., the substrate is of an N-type conductivity type, the body region is of a P-type conductivity type, and the source region is of an N-type conductivity type, an N-channel may be formed in the body region.
Illustratively, the gate structure includes a gate layer and a gate dielectric layer. Alternatively, the gate dielectric layer may comprise conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment, the gate layer is composed of a polysilicon material, and a metal, metal nitride, metal silicide, or the like may be generally used as the material of the gate layer. In other embodiments, device structure layer 301 may also include other components, such as drain regions, and the like.
Illustratively, the substrate 300 includes a semiconductor base and an epitaxial layer formed on the semiconductor base. Alternatively, the semiconductor substrate and the epitaxial layer may have the same conductivity type. Illustratively, the semiconductor substrate and the epitaxial layer may have different doping concentrations, e.g., the doping concentration of the epitaxial layer may be lower than the doping concentration of the semiconductor substrate, alternatively, the epitaxial layer may serve as a drift region of the semiconductor device of the present invention, the drift region being present to provide a breakdown voltage of the device and to act as a buffer, while parasitic capacitance between the source and drain electrodes may be reduced.
In one example, the interlayer dielectric layer 302 may be formed using various deposition methods commonly used in the art, and may be formed by, for example, a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. Illustratively, the interlayer dielectric layer 302 may be made of silicon dioxide, fluorocarbon, carbon doped silicon oxide, or silicon carbonitride, which is not limited in this application. In one example, the material of the top metal layer 303 is not particularly limited, and one or more materials from Ag, au, cu, pd, cr, mo, ti, ta, W and Al may be used.
Next, step S2 is performed to etch the top metal layer to form a first metal pad and a second metal pad isolated from each other, wherein the first metal pad and the second metal pad have sloped sidewall topography. Specifically, as shown in fig. 3C, the top metal layer 303 is etched to form a first metal pad 305 and a second metal pad 306 isolated from each other, wherein the first metal pad 305 and the second metal pad 306 have sloped sidewall topography. Illustratively, the first metal pad 305 and the second metal pad 306 are isolated from each other such that a portion of the surface of the interlayer dielectric layer 302 is exposed. By way of example, by making the first metal pad 305 and the second metal pad 306 have inclined sidewall morphology, compared with vertical sidewall morphology, stress at corners and sidewalls of the first metal pad 305 and the second metal pad 306 can be greatly relieved, so that adhesion capability of a film layer formed at the corners and sidewalls of the first metal pad 305 and the second metal pad 306 can be increased, and further problems of cracking or even falling of the film layer formed at the corners and sidewalls of the first metal pad 305 and the second metal pad 306 can be effectively avoided. Illustratively, an anisotropic dry etching process may be used to etch the top metal layer 303 so that the first metal pad 305 and the second metal pad 306 are formed to have sloped sidewall features, or a combined wet etching and dry etching process may be used to etch the top metal layer 303 so that the first metal pad 305 and the second metal pad 306 are formed to have sloped sidewall features.
In one example, the first metal pad 305 includes a source pad and the second metal pad 306 includes a gate pad. Illustratively, the source and gate pads are used in subsequent processes to electrically connect the gate structure and source region, respectively, in the device structure layer 301 to extract the gate structure and source region in the device structure layer 301, e.g., the source and gate pads are electrically connected to the gate structure and source region, respectively, in the device structure layer 301 through contact holes (not shown) formed in the interlayer dielectric layer 302.
In one example, a drain region is further formed on the second surface of the substrate 300, and a third metal pad (not shown) is further formed on the drain region. The third metal pad is illustratively a drain pad for electrically connecting the drain region in a subsequent process to achieve the function of extracting the drain region.
In one example, as shown in fig. 3B and 3C, etching the top metal layer 303 to form a first metal pad 305 and a second metal pad 306 isolated from each other, comprising: forming a patterned mask layer 304 over the top metal layer 303; etching the top metal layer 303 with the mask layer 304 as a mask to form a first metal pad 305 and a second metal pad 306 isolated from each other; finally, the mask layer 304 is removed. Illustratively, the mask layer 304 may be photoresist or other suitable material capable of being used as a mask.
Next, step S3 is performed to form a first passivation layer covering the first metal pad and the second metal pad on the substrate. Specifically, as shown in fig. 3D, a first passivation layer 307 is formed to cover the first metal pad 305 and the second metal pad 306.
In one example, the first passivation layer 307 is formed using an atomic layer deposition method. Illustratively, the first passivation layer 307 formed by using the atomic layer deposition method has the advantages of good step coverage, high compactness, uniform thickness, no void defect, moisture resistance and the like, and can better protect the device from the invasion of water vapor and impurity ions, thereby effectively improving the reliability of the device.
In one example, the material of the first passivation layer 307 includes aluminum oxide. Illustratively, the first passivation layer 307 of aluminum oxide has excellent field effect passivation characteristics and good chemical passivation characteristics, and in addition, the first passivation layer 307 of aluminum oxide has the advantages of good thermal stability, strong radiation damage resistance, strong ion permeation resistance, and the like. In other embodiments, the material of the first passivation layer 307 may be other suitable materials.
Next, step S4 is performed to pattern the first passivation layer to form a first opening exposing top surfaces of the first metal pad and the second metal pad portion in the first passivation layer. Specifically, as shown in fig. 3E, the first passivation layer 307 is patterned to form a first opening 308 exposing a portion of the top surfaces of the first metal pad 305 and the second metal pad 306 in the first passivation layer 307. Illustratively, the patterned first passivation layer 307 covers the exposed interlayer dielectric layer 302 and extends partially onto the top surfaces of the first metal pad 305 and the second metal pad 306. Optionally, patterning the first passivation layer 307 includes the steps of: forming a mask layer on the first passivation layer 307; etching the first passivation layer 307 with the mask layer as a mask to form a first opening 308 exposing a portion of the top surfaces of the first metal pad 305 and the second metal pad 306 in the first passivation layer 307; and finally removing the mask layer. Dry etching may be selected for this step, including but not limited to Reactive Ion Etching (RIE), ion beam etching, plasma etching, and the like. The mask layer may be, for example, photoresist or other suitable material capable of being used as a mask.
Finally, a step S5 is performed of forming a second passivation layer on the substrate, the second passivation layer covering the first passivation layer and having a second opening exposing the top surfaces of the first metal pad and the second metal pad portion. Specifically, as shown in fig. 3G, a second passivation layer 309 is formed, the second passivation layer 309 covering the first passivation layer 307 and having a second opening 310 exposing a portion of the top surfaces of the first metal pad 305 and the second metal pad 306. Illustratively, the second opening 310 is used in a subsequent process to connect the first metal pad 305 and the second metal pad 306 to external circuitry. Illustratively, the second passivation layer 309 covers and encapsulates the first passivation layer 307, which can further enhance the protection capability of the device.
In one example, as shown in fig. 3F and 3G, the second passivation layer 309 covering the first passivation layer 307 and the entire top surfaces of the first and second metal pads 305 and 306 may be formed by blanket deposition, and then the second passivation layer 309 may be patterned to form the second opening 310 exposing portions of the top surfaces of the first and second metal pads 305 and 306. Optionally, patterning the second passivation layer 309 includes the steps of: forming a mask layer on the second passivation layer 309; etching the second passivation layer 309 with the mask layer as a mask to form a second opening 310 exposing a portion of the top surfaces of the first metal pad 305 and the second metal pad 306 in the second passivation layer 309; and finally removing the mask layer. Dry etching may be selected for this step, including but not limited to Reactive Ion Etching (RIE), ion beam etching, plasma etching, and the like. The mask layer may be, for example, photoresist or other suitable material capable of being used as a mask. The second passivation layer 309 may be formed using various deposition methods commonly used in the art, for example, may be formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, or the like, for example.
In one example, the material of the second passivation layer 309 includes polyimide. Illustratively, the second passivation layer 309 of polyimide material has excellent high temperature resistance, good physical and chemical stability, and excellent electrical insulation, and furthermore, the second passivation layer 309 of polyimide material has good toughness and strength. In other embodiments, the material of the second passivation layer 309 may be other suitable materials.
The method for manufacturing the semiconductor device of the present invention has the advantages that the key steps of the method for manufacturing the semiconductor device of the present invention are described, and other steps can be included in the manufacture of the complete semiconductor device, which is not described in detail herein, and it is worth mentioning that the sequence of the steps can be adjusted on the premise of no conflict.
In summary, the preparation method of the semiconductor device of the embodiment of the invention adopts the first passivation layer and the second passivation layer to form double-layer protection for the device, and by forming the first metal pad and the second metal pad with inclined side wall morphology, the stress of the side wall and the corner of the first metal pad and the second metal pad can be effectively relieved, thereby improving the adhesion capability of the first passivation layer and the second passivation layer, avoiding the cracking and other problems of the side wall and the corner of the first metal pad and the second metal pad, and improving the reliability and the product yield of the device. Illustratively, the first passivation layer is formed by an atomic deposition method, so that the step coverage and compactness of the first passivation layer can be further improved, and the reliability of the device can be further improved.
Example two
The present invention also provides a semiconductor device obtained by the method of the first embodiment. Since the device of the present application is prepared by the method described above, the same advantages as the method described above are obtained. Specifically, as shown in fig. 3G, the semiconductor device includes:
a substrate 300, in which a device structure layer 301 is formed in the substrate 300 extending from a first surface of the substrate 300 into the substrate 300;
an interlayer dielectric layer 302 on the device structure layer 301;
a first metal pad 305 and a second metal pad 306 isolated from each other on the interlayer dielectric layer 302, wherein the first metal pad 305 and the second metal pad 306 have an inclined sidewall morphology;
a first passivation layer 307, the first passivation layer 307 covering sidewalls and a portion of top surfaces of the first metal pad 305 and the second metal pad 306;
and a second passivation layer 309, the second passivation layer 309 covering the first passivation layer 307 and having a second opening 310 exposing a portion of the top surfaces of the first metal pad 305 and the second metal pad 306.
In one example, substrate 300 is a bulk silicon substrate, which may include at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductor, or substrate 300 may also comprise silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which substrate 300 may be formed are described herein, any material that may serve as substrate 300 falls within the spirit and scope of the present invention. In one embodiment, the substrate 300 may be of an N-type conductivity type, and in other embodiments, the substrate 300 may also be of a P-type conductivity type, and in particular, a suitable substrate may be selected according to the type of device. In one embodiment, the material of the substrate 300 is silicon carbide.
In one example, the semiconductor device of the present application includes a silicon carbide MOS device. Illustratively, taking the semiconductor device of the present application as a Vertical Diffusion Metal Oxide Semiconductor (VDMOS) as an example, the device structure layer 301 may include a gate structure, a body region, and a source region, wherein the source region is located within the body region. Illustratively, the body region is formed using a standard ion implantation process, which may be combined with a high energy ion implantation and a high temperature thermal annealing process. Illustratively, the source region may be formed by photolithography and by an ion implantation process, followed by a rapid thermal annealing process, with a high temperature of 900 to 1050 degrees celsius being used to activate the dopants within the source region and simultaneously repair the lattice structure of the surface of the semiconductor substrate damaged during each ion implantation process. Illustratively, the body region has a conductivity type different from the substrate, the source region has the same conductivity type as the substrate, e.g., the substrate is of an N-type conductivity type, the body region is of a P-type conductivity type, and the source region is of an N-type conductivity type, an N-channel may be formed in the body region.
Illustratively, the gate structure includes a gate layer and a gate dielectric layer. Alternatively, the gate dielectric layer may comprise conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment, the gate layer is composed of a polysilicon material, and a metal, metal nitride, metal silicide, or the like may be generally used as the material of the gate layer. In other embodiments, device structure layer 301 may also include other components, such as drain regions, and the like.
Illustratively, the substrate 300 includes a semiconductor base and an epitaxial layer formed on the semiconductor base. Alternatively, the semiconductor substrate and the epitaxial layer may have the same conductivity type. Illustratively, the semiconductor substrate and the epitaxial layer may have different doping concentrations, e.g., the doping concentration of the epitaxial layer may be lower than the doping concentration of the semiconductor substrate, alternatively, the epitaxial layer may serve as a drift region of the semiconductor device of the present invention, the drift region being present to provide a breakdown voltage of the device and to act as a buffer, while parasitic capacitance between the source and drain electrodes may be reduced.
In one example, the interlayer dielectric layer 302 may be formed using various deposition methods commonly used in the art, and may be formed by, for example, a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. Illustratively, the interlayer dielectric layer 302 may be made of silicon dioxide, fluorocarbon, carbon doped silicon oxide, or silicon carbonitride, which is not limited in this application. In one example, the material of the top metal layer 303 is not particularly limited, and one or more materials from Ag, au, cu, pd, cr, mo, ti, ta, W and Al may be used.
In one example, the first metal pad 305 includes a source pad and the second metal pad 306 includes a gate pad. Illustratively, the source and gate pads are used in subsequent processes to electrically connect the gate structure and source region, respectively, in the device structure layer 301 to extract the gate structure and source region in the device structure layer 301, e.g., the source and gate pads are electrically connected to the gate structure and source region, respectively, in the device structure layer 301 through contact holes (not shown) formed in the interlayer dielectric layer 302.
In one example, a drain region is further formed on the second surface of the substrate 300, and a third metal pad (not shown) is further formed on the drain region. The third metal pad is illustratively a drain pad for electrically connecting the drain region in a subsequent process to achieve the function of extracting the drain region.
In one example, the first passivation layer 307 is formed using an atomic layer deposition method. Illustratively, the first passivation layer 307 formed by using the atomic layer deposition method has the advantages of good step coverage, high compactness, uniform thickness, no void defect, moisture resistance and the like, and can better protect the device from the invasion of water vapor and impurity ions, thereby effectively improving the reliability of the device.
In one example, the material of the first passivation layer 307 includes aluminum oxide. Illustratively, the first passivation layer 307 of aluminum oxide has excellent field effect passivation characteristics and good chemical passivation characteristics, and in addition, the first passivation layer 307 of aluminum oxide has the advantages of good thermal stability, strong radiation damage resistance, strong ion permeation resistance, and the like. In other embodiments, the material of the first passivation layer 307 may be other suitable materials.
In one example, the material of the second passivation layer 309 includes polyimide. Illustratively, the second passivation layer 309 of polyimide material has excellent high temperature resistance, good physical and chemical stability, and excellent electrical insulation, and furthermore, the second passivation layer 309 of polyimide material has good toughness and strength. In other embodiments, the material of the second passivation layer 309 may be other suitable materials.
Thus, the description of the structure of the semiconductor device of the present invention is completed, and other constituent structures may be included in the complete device, which will not be described in detail herein.
In summary, the semiconductor device of the embodiment of the invention adopts the first passivation layer and the second passivation layer to form double-layer protection for the device, and forms the first metal pad and the second metal pad with inclined side wall morphology, so that the stress of the side walls and the corners of the first metal pad and the second metal pad can be effectively relieved, the adhesion capability of the first passivation layer and the second passivation layer is improved, the problems that the side walls of the first metal pad and the second metal pad and the first passivation layer and the second passivation layer at the corners crack and the like are avoided, and the reliability and the product yield of the device are improved. Illustratively, the first passivation layer formed by the atomic deposition method can further improve the step coverage and compactness thereof, thereby further improving the reliability of the device.
Example III
In another embodiment of the present invention, an electronic apparatus is provided, including the semiconductor device described above.
The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.
Although a number of embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and alterations may be made in the arrangement and/or component parts of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and variations in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate, forming a device structure layer extending from a first surface of the substrate into the substrate in the substrate, forming an interlayer dielectric layer on the device structure layer, and forming a top metal layer on the interlayer dielectric layer;
etching the top metal layer to form a first metal pad and a second metal pad isolated from each other, wherein the first metal pad and the second metal pad have sloped sidewall topography;
forming a first passivation layer on the substrate, wherein the first passivation layer covers the first metal pad and the second metal pad;
patterning the first passivation layer to form a first opening in the first passivation layer exposing top surfaces of the first metal pad and the second metal pad portion;
a second passivation layer is formed on the substrate, the second passivation layer covering the first passivation layer and having a second opening exposing top surfaces of the first metal pad and the second metal pad portion.
2. The method of claim 1, wherein the first passivation layer is formed using an atomic layer deposition process.
3. The method of claim 1, wherein the material of the first passivation layer comprises aluminum oxide.
4. The method of claim 1, wherein the material of the second passivation layer comprises polyimide.
5. The method of manufacturing according to claim 1, wherein the semiconductor device comprises a silicon carbide MOS device.
6. The method of manufacturing of claim 1, wherein the first metal pad comprises a source pad and the second metal pad comprises a gate pad.
7. The method of manufacturing according to claim 1, wherein a drain region extending from the second surface of the substrate into the substrate is further formed in the substrate, and a third metal pad is further formed on the drain region.
8. A semiconductor device, comprising:
a substrate in which a device structure layer is formed extending from a first surface of the substrate into the substrate;
an interlayer dielectric layer on the device structure layer;
a first metal pad and a second metal pad isolated from each other on the interlayer dielectric layer, wherein the first metal pad and the second metal pad have sloped sidewall topography;
a first passivation layer covering sidewalls and a portion of top surfaces of the first and second metal pads;
and a second passivation layer covering the first passivation layer and having a second opening exposing top surfaces of the first and second metal pad portions.
9. The semiconductor device according to claim 8, wherein a material of the first passivation layer comprises aluminum oxide and/or a material of the second passivation layer comprises polyimide.
10. An electronic device, characterized in that it comprises the semiconductor device according to any one of claims 8-9.
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