CN117711948A - Multilayer epitaxial super-junction field effect transistor and preparation method thereof - Google Patents

Multilayer epitaxial super-junction field effect transistor and preparation method thereof Download PDF

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CN117711948A
CN117711948A CN202311789978.6A CN202311789978A CN117711948A CN 117711948 A CN117711948 A CN 117711948A CN 202311789978 A CN202311789978 A CN 202311789978A CN 117711948 A CN117711948 A CN 117711948A
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superjunction
region
cell region
layer
unit
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尹小宝
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a multilayer epitaxial superjunction field effect transistor and a preparation method thereof, wherein a cell region superjunction column is formed by diffusion connection of a first cell region superjunction doping unit, a second cell region superjunction doping unit, a third cell region superjunction doping unit, a fourth cell region superjunction doping unit and a fifth cell region superjunction doping unit, the third cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction, and the fourth cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction to a second side opposite to the first side. The adoption of the superjunction column in the cellular region can improve the short-circuit tolerance capability of the multilayer epitaxial superjunction field effect transistor device, and is particularly characterized in that the short-circuit tolerance time is increased and the heating during the short-circuit period is reduced, for example, when the superjunction device works under a short-circuit working condition, the short-circuit tolerance time can be increased by 25%, and the device temperature before the short-circuit protection is started is reduced by 30-50 ℃.

Description

Multilayer epitaxial super-junction field effect transistor and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a multilayer epitaxial super-junction field effect transistor and a preparation method thereof.
Background
Multilayer epitaxial superjunction field effect transistors (Super Junction MOSFET) are widely used in electronic power systems as an advanced power MOSFET device technology. When the superjunction device is used as a switching device in a circuit, the superjunction device inevitably works under some undesirable working conditions, such as a short-circuit working condition, and the device is simultaneously subjected to high current and high voltage, so that the device can quickly generate heat, and if a short-circuit protection mechanism is not started in time, the device can be damaged.
Therefore, how to improve the short-circuit tolerance of the superjunction device is an important technical problem to be solved by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a multi-layer epitaxial superjunction field effect transistor and a method for manufacturing the same, which are used for solving the problem that the short-circuit tolerance of the existing superjunction device needs to be improved.
To achieve the above and other related objects, the present invention provides a multilayer epitaxial superjunction field effect transistor and a method for manufacturing the same, comprising the steps of:
providing a substrate, forming a first semiconductor layer on the substrate, wherein the first semiconductor layer comprises a first epitaxial layer, a first unitary cell area super junction doping unit and a first terminal area super junction doping unit, wherein the first unitary cell area super junction doping unit and the first terminal area super junction doping unit are positioned on the upper surface layer of the first epitaxial layer;
forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises at least one second epitaxial layer, a second cell region super-junction doping unit and a second terminal region super-junction doping unit are formed on the upper surface layer of each second epitaxial layer, and the second cell region super-junction doping unit is positioned right above the first cell region super-junction doping unit;
forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer comprises at least one double-layer structure, each double-layer structure comprises a third epitaxial layer and a fourth epitaxial layer positioned on the third epitaxial layer, a third cell region superjunction doping unit and a third terminal region superjunction doping unit are formed on the upper surface layer of each third epitaxial layer, a fourth cell region superjunction doping unit and a fourth terminal region superjunction doping unit are formed on the upper surface layer of each fourth epitaxial layer, the third cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction, and the fourth cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction on a second side opposite to the first side;
Forming a fourth semiconductor layer on the third semiconductor layer, wherein the fourth semiconductor layer comprises at least one fifth epitaxial layer, a fifth cell region super-junction doping unit and a fifth terminal region super-junction doping unit are formed on the upper surface layer of each fifth epitaxial layer, and the fifth cell region super-junction doping unit is positioned right above the first cell region super-junction doping unit;
and annealing treatment is carried out so that the first cell region superjunction doping unit, the second cell region superjunction doping unit, the third cell region superjunction doping unit, the fourth cell region superjunction doping unit and the fifth cell region superjunction doping unit are in diffusion connection to form a cell region superjunction column, and the first terminal region superjunction doping unit, the second terminal region superjunction doping unit, the third terminal region superjunction doping unit, the fourth terminal region superjunction doping unit and the fifth terminal region superjunction doping unit are in diffusion connection to form a terminal region superjunction column.
Optionally, the first terminal region superjunction doping unit, the second terminal region superjunction doping unit, the third terminal region superjunction doping unit, the fourth terminal region superjunction doping unit and the fifth terminal region superjunction doping unit are located on a same straight line in a thickness direction.
Optionally, the widths of the first cell region superjunction doping unit, the second cell region superjunction doping unit, the third cell region superjunction doping unit, the fourth cell region superjunction doping unit and the fifth cell region superjunction doping unit are the same, and the widths of the first terminal region superjunction doping unit, the second terminal region superjunction doping unit, the third terminal region superjunction doping unit, the fourth terminal region superjunction doping unit and the fifth terminal region superjunction doping unit are the same.
Optionally, the distance of the third superjunction doping unit of the subcell region to the first side in the width direction is 10% -40% of the width of the superjunction doping unit of the first subcell region, and the distance of the second side opposite to the first side of the superjunction doping unit of the subcell region to the first side in the width direction is 10% -40% of the width of the superjunction doping unit of the first subcell region.
Optionally, the number of the cell area superjunction columns is multiple, and the cell area superjunction columns are sequentially and alternately arranged in the width direction; the number of the terminal area super-junction columns is multiple, and the terminal area super-junction columns are sequentially and alternately arranged in the width direction; the width of the terminal area super junction column is larger than that of the cell area super junction column, and the distance between two adjacent terminal area super junction columns is larger than that between two adjacent cell area super junction columns.
Optionally, the method further comprises the following steps:
forming a field oxide layer on the fourth semiconductor layer, wherein the field oxide layer covers the terminal area super junction column;
forming a gate structure on the fourth semiconductor layer, wherein the gate structure is positioned at one side of the superjunction column of the cellular region and comprises a gate dielectric layer and a gate conducting layer positioned on the gate dielectric layer;
forming a body region on the upper surface layer of the fourth semiconductor layer, wherein the body region is opposite to the fifth cell region super-junction doping unit, and the bottom surface of the body region is higher than the bottom surface of the fifth cell region super-junction doping unit which is positioned at the topmost layer and after diffusion;
forming a source region on the upper surface layer of the body region;
forming an interlayer dielectric layer covering the gate structure on the fourth semiconductor layer;
forming a contact hole in the interlayer dielectric layer;
forming a front metal interconnection layer on the interlayer dielectric layer and in the contact hole;
thinning the substrate from the back side;
and forming a back metal layer on the back of the substrate.
Optionally, the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the fifth epitaxial layer are all of a first conductivity type, the cell region superjunction pillar and the terminal region superjunction pillar are both of a second conductivity type opposite to the first conductivity type, and the first conductivity type is N-type or P-type.
The invention also provides a multilayer epitaxial superjunction field effect transistor comprising:
a substrate;
an epitaxial layer on the substrate;
the cell region superjunction column is positioned in the epitaxial layer, the bottom surface of the cell region superjunction column is higher than the bottom surface of the epitaxial layer, the cell region superjunction column comprises a first cell region superjunction diffusion region, a second cell region superjunction diffusion region, a third cell region superjunction diffusion region and a fourth cell region superjunction diffusion region which are sequentially connected from bottom to top, the first cell region superjunction diffusion region comprises a first cell region superjunction diffusion unit, the second cell region superjunction diffusion region comprises one or a plurality of second cell region superjunction diffusion units stacked in the thickness direction, the second cell region superjunction diffusion unit is positioned right above the first cell region superjunction diffusion unit, the first cell region superjunction diffusion region comprises one or a plurality of first cell region superjunction diffusion regions stacked in the thickness direction, the first cell region superjunction diffusion region comprises a third cell region superjunction diffusion unit and a fourth cell region superjunction diffusion unit stacked in the thickness direction, the second cell region superjunction diffusion unit is positioned on one side of the first cell region and the side of the first cell diffusion unit, the first cell region is positioned on the side of the first cell diffusion unit in the thickness direction, and the first cell region is positioned on the side of the first cell diffusion unit in the first cell region;
And the terminal area super junction column is positioned in the epitaxial layer, and the bottom surface of the terminal area super junction column is higher than the bottom surface of the epitaxial layer.
Optionally, the third superjunction diffusion unit is offset from the first superjunction diffusion unit toward a first side in the width direction by a distance of 10% -40% of the width of the first superjunction diffusion unit, and the fourth superjunction diffusion unit is offset from the first superjunction diffusion unit toward a second side opposite to the first side in the width direction by a distance of 10% -40% of the width of the first superjunction diffusion unit.
Optionally, the method further comprises:
the field oxide layer is positioned on the epitaxial layer and covers the terminal area super junction column;
the grid structure is positioned on the epitaxial layer and arranged on one side of the superjunction column of the cellular region, and comprises a grid dielectric layer and a grid conducting layer positioned on the grid dielectric layer;
the body region is positioned on the upper surface layer of the epitaxial layer and is opposite to the fifth cell region superjunction diffusion unit, and the bottom surface of the body region is higher than the bottom surface of the fifth cell region superjunction diffusion unit positioned on the topmost layer;
the source region is positioned on the upper surface layer of the body region;
The interlayer dielectric layer is positioned on the epitaxial layer and covers the grid structure;
the contact hole is positioned in the interlayer dielectric layer;
the front metal interconnection layer is positioned on the interlayer dielectric layer and in the contact hole;
and the back metal layer is positioned on the back of the substrate.
As described above, in the multilayer epitaxial superjunction field effect transistor and the manufacturing method thereof, the superjunction column of the cellular region is formed by diffusion connection of the superjunction doping unit of the first cellular region, the superjunction doping unit of the second cellular region, the superjunction doping unit of the third cellular region, the superjunction doping unit of the fourth cellular region and the superjunction doping unit of the fifth cellular region, wherein the superjunction doping unit of the third cellular region deviates from the superjunction doping unit of the first cellular region by a preset distance in the width direction, the superjunction doping unit of the fourth cellular region deviates from the superjunction doping unit of the first cellular region by a preset distance in the width direction in the second side opposite to the first side, and the superjunction column of the cellular region can improve the short-circuit tolerance capability of the multilayer epitaxial superjunction field effect transistor.
Drawings
Fig. 1 shows a device cross-sectional structure diagram of a cell region and a termination region of a multi-layer epitaxial superjunction field effect transistor device.
Fig. 2 is a process flow diagram of a method of fabricating a multi-layer epitaxial superjunction field effect transistor of the present invention.
Fig. 3 is a schematic diagram showing a structure obtained after forming a first semiconductor layer on a substrate by the method for manufacturing a multi-layer epitaxial superjunction field effect transistor according to the present invention.
Fig. 4 is a schematic diagram showing the structure obtained after forming the first layer of the second semiconductor layer by the method for manufacturing a multi-layered epitaxial superjunction field effect transistor according to the present invention.
Fig. 5 is a schematic diagram showing the structure obtained after forming the second layer of the second semiconductor layer by the method for manufacturing a multi-layered epitaxial superjunction field effect transistor according to the present invention.
Fig. 6 is a schematic diagram showing the structure obtained after forming the first layer of the third semiconductor layer by the method for manufacturing a multi-layered epitaxial superjunction field effect transistor according to the present invention.
Fig. 7 is a schematic diagram showing a structure obtained after forming a second layer of a third semiconductor layer according to the method for manufacturing a multi-layered epitaxial superjunction field effect transistor of the present invention.
Fig. 8 is a schematic diagram showing a structure obtained after forming a third layer of a third semiconductor layer according to the method for manufacturing a multi-layered epitaxial superjunction field effect transistor of the present invention.
Fig. 9 is a schematic diagram showing a structure obtained after forming a fourth layer of a third semiconductor layer according to the method for manufacturing a multi-layered epitaxial superjunction field effect transistor of the present invention.
Fig. 10 is a schematic diagram showing a structure obtained after forming a fourth semiconductor layer on a third semiconductor layer according to the method for manufacturing a multi-layer epitaxial super junction field effect transistor of the present invention.
Fig. 11 is a schematic diagram showing the structure obtained after annealing treatment to obtain a cell region superjunction pillar and a terminal region superjunction pillar according to the preparation method of the multilayer epitaxial superjunction field effect transistor of the present invention.
Fig. 12 is a schematic diagram showing a structure obtained after forming a field oxide layer on a fourth semiconductor layer according to the method for manufacturing a multi-layer epitaxial superjunction field effect transistor of the present invention.
Fig. 13 is a schematic diagram showing a structure obtained after forming a gate structure on a fourth semiconductor layer according to the method for manufacturing a multi-layer epitaxial superjunction field effect transistor of the present invention.
Fig. 14 is a schematic diagram showing a structure obtained after a body region is formed on an upper surface layer of a fourth semiconductor layer by the method for manufacturing a multi-layer epitaxial superjunction field effect transistor according to the present invention.
Fig. 15 is a schematic diagram showing the structure obtained after forming an interlayer dielectric layer and a contact hole by the method for manufacturing a multi-layer epitaxial superjunction field effect transistor according to the present invention.
Fig. 16 is a schematic diagram showing the structure obtained after the front-side metal interconnection layer is formed by the method for manufacturing the multi-layer epitaxial superjunction field effect transistor according to the present invention.
Fig. 17 is a schematic diagram showing the structure obtained after the back metal layer is formed by the method for manufacturing the multi-layer epitaxial superjunction field effect transistor according to the present invention.
Description of the reference numerals
S1 to S5 steps
101. Substrate and method for manufacturing the same
102 N-type epitaxial layer
103. P column of cellular region
104. Terminal region P column
105 P-well
106 N-type heavily doped source region
107. Gate oxide
108. Field oxygen
109. Polycrystalline silicon
110. Interlayer dielectric layer
111. Front side metal layer
112. Backside metal layer
201. Substrate and method for manufacturing the same
202. First semiconductor layer
2021. First epitaxial layer
2022. Super junction doping unit of first unitary cell region
2023. Super junction doping unit of first terminal region
203. Photoresist layer
204. Second semiconductor layer
2041. Second epitaxial layer
2042. Super junction doping unit of second binary cell region
2043. Second terminal region super junction doping unit
205. Photoresist layer
206. Third semiconductor layer
2061. Third epitaxial layer
2062. Fourth epitaxial layer
2063. Super junction doping unit of third cell region
2064. Third terminal region super junction doping unit
2065. Fourth cell region superjunction doping unit
2066. Fourth terminal region super junction doping unit
207. Photoresist layer
208. Fourth semiconductor layer
2081. Fifth epitaxial layer
2082. Super junction doping unit of fifth cell region
2083. Fifth terminal region super junction doping unit
209. Photoresist layer
210. Super junction column of cellular region
2101. Super junction diffusion unit of first unitary cell region
2102. Second binary cell region superjunction diffusion unit
2103. Third cell region superjunction diffusion unit
2104. Fourth cell area superjunction diffusion unit
2105. Super junction diffusion unit of fifth cell region
211. Super junction column of terminal area
2111. Super junction diffusion unit of first terminal region
2112. Second termination region superjunction diffusion unit
2113. Third termination region superjunction diffusion cell
2114. Fourth termination region superjunction diffusion cell
2115. Fifth termination region superjunction diffusion cell
212. Field oxide layer
213. Photoresist layer
214. Gate structure
2141. Gate dielectric layer
2142. Gate conductive layer
215. Body region
216. Source region
217. Interlayer dielectric layer
218. Contact hole
219. Front side metal interconnect layer
220. Backside metal layer
A first unitary cell region superjunction diffusion region
B second binary cell region superjunction diffusion region
C third cell region superjunction diffusion region
D fourth cell region superjunction diffusion region
E third cell region superjunction diffusion region
Detailed Description
Referring to fig. 1, a device cross-sectional structure diagram of a Cell (Cell) region and a terminal region of a multi-layer epitaxial superjunction field effect transistor device is shown, which includes a substrate 101, an N-type epitaxial layer 102, a Cell region P pillar 103, a terminal region P pillar 104, a P well 105, an N-type heavily doped source region 106, a gate oxide 107, a field oxide 108, polysilicon 109, an interlayer dielectric layer 110, a front metal layer 111 and a back metal layer 112, wherein the P pillar is repeatedly formed by a combination process of epitaxial growth, photolithography, and boron implantation. Because the super junction field effect transistor needs the charge balance of the P column and the N type epitaxial layer to fully exhaust the P column and the N type epitaxial layer after the space charge region is unfolded, the product of the doping concentration and the volume of the P column is required to be equivalent to the product of the doping concentration and the volume of the N type epitaxial layer. When the P column and the N type epitaxial layer are perfectly balanced, the breakdown voltage reaches a peak value, the on resistance is also the lowest, but the short circuit tolerance capability is poor at the moment, and the device is easy to damage in a short circuit working condition. Through a great amount of analysis and research, the inventor of the application improves the forming method and structure of the P column, and can improve the short-circuit tolerance capability of the multilayer epitaxial super junction field effect transistor device, and the short-circuit tolerance capability is embodied by increasing the short-circuit tolerance time and reducing the heating during the short-circuit.
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to 17. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The invention provides a preparation method of a multilayer epitaxial super junction field effect transistor, referring to fig. 2, a process flow chart of the method is shown, comprising the following steps:
s1: providing a substrate, forming a first semiconductor layer on the substrate, wherein the first semiconductor layer comprises a first epitaxial layer, a first unitary cell area super junction doping unit and a first terminal area super junction doping unit, wherein the first unitary cell area super junction doping unit and the first terminal area super junction doping unit are positioned on the upper surface layer of the first epitaxial layer;
S2: forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises at least one second epitaxial layer, a second cell region super-junction doping unit and a second terminal region super-junction doping unit are formed on the upper surface layer of each second epitaxial layer, and the second cell region super-junction doping unit is positioned right above the first cell region super-junction doping unit;
s3: forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer comprises at least one double-layer structure, each double-layer structure comprises a third epitaxial layer and a fourth epitaxial layer positioned on the third epitaxial layer, a third cell region superjunction doping unit and a third terminal region superjunction doping unit are formed on the upper surface layer of each third epitaxial layer, a fourth cell region superjunction doping unit and a fourth terminal region superjunction doping unit are formed on the upper surface layer of each fourth epitaxial layer, the third cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction, and the fourth cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction on a second side opposite to the first side;
S4: forming a fourth semiconductor layer on the third semiconductor layer, wherein the fourth semiconductor layer comprises at least one fifth epitaxial layer, a fifth cell region super-junction doping unit and a fifth terminal region super-junction doping unit are formed on the upper surface layer of each fifth epitaxial layer, and the fifth cell region super-junction doping unit is positioned right above the first cell region super-junction doping unit;
s5: and annealing treatment is carried out so that the first cell region superjunction doping unit, the second cell region superjunction doping unit, the third cell region superjunction doping unit, the fourth cell region superjunction doping unit and the fifth cell region superjunction doping unit are in diffusion connection to form a cell region superjunction column, and the first terminal region superjunction doping unit, the second terminal region superjunction doping unit, the third terminal region superjunction doping unit, the fourth terminal region superjunction doping unit and the fifth terminal region superjunction doping unit are in diffusion connection to form a terminal region superjunction column.
The above steps are described in detail below in conjunction with the block diagrams.
Referring first to fig. 3, the step S1 is performed: a substrate 201 is provided, and a first semiconductor layer 202 is formed on the substrate 201, wherein the first semiconductor layer 202 includes a first epitaxial layer 2021, and a first cell region super junction doping unit 2022 and a first terminal region super junction doping unit 2023 located on an upper surface layer of the first epitaxial layer 2021.
Specifically, the first meta-region super-junction doping unit 2022 is configured to form a part of a meta-region super-junction pillar, which is the same as a conductivity type of the meta-region super-junction pillar, and the first terminal-region super-junction doping unit 2023 is configured to form a part of a terminal-region super-junction pillar, which is the same as a conductivity type of the terminal-region super-junction pillar. When the first epitaxial layer 2021 is of a first conductivity type, the cell region superjunction pillar and the terminal region superjunction pillar are both of a second conductivity type opposite to the first conductivity type, the first conductivity type being either N-type or P-type. In a preferred embodiment, the first epitaxial layer 2021 is N-type, and the cell region superjunction pillar and the terminal region superjunction pillar are P-type.
As an example, the substrate 201 may be a silicon substrate or other suitable semiconductor substrate.
As an example, forming the first semiconductor layer 202 includes the steps of:
(1) The first epitaxial layer 2021 is grown on the substrate 201, and the thickness of the first epitaxial layer 2021 may be set according to the device performance requirement, and the present invention is not particularly limited.
(2) A photoresist layer 203 is formed on the first epitaxial layer 2021, and the photoresist layer 203 is patterned by a photolithography process such as exposure, development, etc., so as to define a cell region superjunction pillar region and a terminal region superjunction pillar region.
(3) The first meta-region superjunction doped unit 2022 and the first terminal-region superjunction doped unit 2023 are formed by ion implantation, for example, when the meta-region superjunction pillar and the terminal-region superjunction pillar are P-type, boron ion implantation may be used.
As an example, the number of the superjunction columns in the cell region is plural, and the superjunction columns in the cell region are sequentially and alternately arranged in the width direction; the number of the terminal area super-junction columns is multiple, and the terminal area super-junction columns are sequentially and alternately arranged in the width direction; the width of the terminal area super junction column is larger than that of the cell area super junction column, and the distance between two adjacent terminal area super junction columns is larger than that between two adjacent cell area super junction columns. In some embodiments, the spacing between adjacent two of the terminal region superjunction posts is increased by 10% -20% compared to the spacing between adjacent two of the cell region superjunction posts.
Referring to fig. 4 to 5, the step S2 is performed: a second semiconductor layer 204 is formed on the first semiconductor layer 201, the second semiconductor layer 204 includes at least one second epitaxial layer 2041, a second cell region super junction doping unit 2042 and a second terminal region super junction doping unit 2043 are formed on an upper surface layer of each second epitaxial layer 2041, and the second cell region super junction doping unit 2042 is located right above the first cell region super junction doping unit 2022.
Specifically, the second cell region superjunction doping unit 2042 is used for forming a part of a cell region superjunction pillar, and has the same conductivity type as the cell region superjunction pillar, and the second terminal region superjunction doping unit 2043 is used for forming a part of a terminal region superjunction pillar, and has the same conductivity type as the terminal region superjunction pillar.
As an example, the second cell region superjunction doping unit 2042 has the same width as the first cell region superjunction doping unit 2022, and the second terminal region superjunction doping unit 2043 has the same width as the first terminal region superjunction doping unit 2023.
As an example, the second terminal region superjunction doped unit 2043 is also located directly above the first terminal region superjunction doped unit 2023.
It should be noted that the second semiconductor layer 204 includes at least one second epitaxial layer 2041, and a second cell region super junction doping unit 2042 and a second terminal region super junction doping unit 2043 are formed on an upper surface layer of each second epitaxial layer 2041. In this embodiment, the forming process of the second semiconductor layer 204 is described by taking the example that the second semiconductor layer 204 includes two layers of the second epitaxial layer 2041, and the forming process includes the following steps:
(1) As shown in fig. 4, a second epitaxial layer 2041 is grown on the first epitaxial layer 2021, and the thickness of the second epitaxial layer 2041 may be set according to the device performance requirement, and the present invention is not particularly limited.
(2) Continuing with fig. 4, a photoresist layer 205 is formed on the second epitaxial layer 2041, and the photoresist layer 205 is patterned by a photolithography process such as exposure, development, etc., exposing a cell region superjunction pillar region and a terminal region superjunction pillar region.
(3) As further shown in fig. 4, the second cell region superjunction doped unit 2042 and the second terminal region superjunction doped unit 2043 are formed by ion implantation.
(4) As shown in fig. 5, another second epitaxial layer 2041 is grown on the previously grown second epitaxial layer 2041.
(5) Continuing with fig. 5, another photoresist layer 205 is formed on the post-grown second epitaxial layer 2041, and the other photoresist layer 205 is patterned by a photolithographic process such as exposure, development, etc., revealing the cell region superjunction pillar region and the termination region superjunction pillar region.
(6) As further shown in fig. 5, the second cell region superjunction doped unit 2042 and the second terminal region superjunction doped unit 2043 are formed again by ion implantation.
Referring to fig. 6 to 9, the step S3 is performed: a third semiconductor layer 206 is formed on the second semiconductor layer 204, the third semiconductor layer 206 includes at least one bilayer structure, each bilayer structure includes a third epitaxial layer 2061 and a fourth epitaxial layer 2062 on the third epitaxial layer 2061, a third cell region super junction doping unit 2063 and a third terminal region super junction doping unit 2064 are formed on an upper surface layer of each third epitaxial layer 2061, a fourth cell region super junction doping unit 2065 and a fourth terminal region super junction doping unit 2066 are formed on an upper surface layer of each fourth epitaxial layer 2062, the third cell region super junction doping unit 2063 is deviated from the first cell region super junction doping unit 2022 by a preset distance in a width direction, and the fourth cell region super junction doping unit 2065 is deviated from the first cell region super junction doping unit 2022 by a preset distance in a width direction to a second side opposite to the first side.
Specifically, the third superjunction doping unit 2063 and the fourth superjunction doping unit 2065 are both used for forming a part of a superjunction column of a cell region and have the same conductivity type as the superjunction column of the cell region, and the third superjunction doping unit 2064 and the fourth superjunction doping unit 2066 are both used for forming a part of a superjunction column of a terminal region and have the same conductivity type as the superjunction column of the terminal region.
As an example, the third and fourth super-junction doping units 2063 and 2065 have the same width as the first and fourth super-junction doping units 2022 and 2064 and 2066 have the same width as the first and fourth super-junction doping units 2023.
As an example, the third cell region superjunction doping unit 2063 is offset from the first cell region superjunction doping unit 2022 by a distance of 10% -40% (e.g., 30%) of the width of the first cell region superjunction doping unit 2022 in the width direction (e.g., left side), and the fourth cell region superjunction doping unit 2065 is offset from the first cell region superjunction doping unit 2022 by a distance of 10% -40% (e.g., 30%) of the width of the first cell region superjunction doping unit 2022 in the width direction (e.g., right side) opposite to the first side.
As an example, the third termination region superjunction doping unit 2064 and the fourth termination region superjunction doping unit 2066 are both located directly above the first termination region superjunction doping unit 2023.
It should be noted that, the third semiconductor layer 206 includes at least one bilayer structure, and the forming process of the third semiconductor layer 206 is described by taking the example that the third semiconductor layer 206 includes two bilayer structures, which includes the following steps:
(1) As shown in fig. 6, the third epitaxial layer 2061 is grown on the second epitaxial layer 2041.
(2) Continuing with fig. 6, a photoresist layer 207 is formed on the third epitaxial layer 2061, and the photoresist layer 207 is patterned by a photolithography process such as exposure, development, etc., exposing a cell region superjunction pillar region and a terminal region superjunction pillar region.
(3) As further shown in fig. 6, the third cell region super-junction doped unit 2063 and the third terminal region super-junction doped unit 2064 are formed on the upper surface layer of the third epitaxial layer 2061 by ion implantation.
(4) As shown in fig. 7, the fourth epitaxial layer 2062 is grown on the third epitaxial layer 2061.
(5) Continuing with fig. 7, another photoresist layer 207 is formed on the fourth epitaxial layer 2062, and the photoresist layer 207 is patterned by a photolithography process such as exposure, development, etc., exposing the cell region superjunction pillar region and the terminal region superjunction pillar region.
(6) As further shown in fig. 7, the fourth cell region super-junction doped unit 2065 and the fourth terminal region super-junction doped unit 2066 are formed on the upper surface layer of the fourth epitaxial layer 2062 by ion implantation.
(7) As shown in fig. 8, another third epitaxial layer 2061 is grown on the fourth epitaxial layer 2062.
(8) Continuing with fig. 8, another photoresist layer 207 is formed on the other third epitaxial layer 2061, and the other photoresist layer 207 is patterned by a photolithography process such as exposure, development, etc., exposing the cell region superjunction pillar region and the terminal region superjunction pillar region.
(9) As further shown in fig. 8, another third cell region super-junction doping unit 2063 and another third terminal region super-junction doping unit 2064 are formed on the upper surface layer of the another third epitaxial layer 2061 by ion implantation.
(10) As shown in fig. 9, another fourth epitaxial layer 2062 is grown on the another third epitaxial layer 2061.
(11) Continuing with fig. 9, another photoresist layer 207 is formed on the other fourth epitaxial layer 2062, and the other photoresist layer 207 is patterned by a photolithography process such as exposure, development, etc., exposing the cell region superjunction pillar region and the terminal region superjunction pillar region.
(12) As further shown in fig. 9, another fourth cell region super-junction doped unit 2065 and another fourth terminal region super-junction doped unit 2066 are formed on the upper surface layer of the another fourth epitaxial layer 2062 by ion implantation.
Referring to fig. 10 again, the step S4 is performed: a fourth semiconductor layer 208 is formed on the third semiconductor layer 206, where the fourth semiconductor layer 208 includes at least a fifth epitaxial layer 2081, and a fifth cell region super junction doping unit 2082 and a fifth terminal region super junction doping unit 2083 are formed on an upper surface layer of each fifth epitaxial layer 2081, and the fifth cell region super junction doping unit 2082 is located right above the first cell region super junction doping unit 2022.
Specifically, the fifth cell region superjunction doping unit 2082 is configured to form a part of a cell region superjunction pillar, and is the same as the conductivity type of the cell region superjunction pillar, and the fifth terminal region superjunction doping unit 2083 is configured to form a part of a terminal region superjunction pillar, and is the same as the conductivity type of the terminal region superjunction pillar.
As an example, the width of the fifth cell region superjunction doping unit 2082 is the same as the width of the first cell region superjunction doping unit 2022, the width of the fifth terminal region superjunction doping unit 2083 is the same as the width of the first terminal region superjunction doping unit 2023, that is, to this step, in an embodiment, the widths of the first cell region superjunction doping unit 2022, the second cell region superjunction doping unit 2042, the third cell region superjunction doping unit 2063, the fourth cell region superjunction doping unit 2065 and the fifth cell region superjunction doping unit 2802 are the same, and the widths of the first terminal region superjunction doping unit 2023, the second terminal region superjunction doping unit 2043, the third terminal region superjunction doping unit 2064, and the fourth terminal region superjunction doping unit 2066 are the same as the width of the fifth terminal region superjunction doping unit 2083.
As an example, the fifth terminal region superjunction doping unit 2083 is also located directly above the first terminal region superjunction doping unit 2023, that is, to this step, in an embodiment, the first terminal region superjunction doping unit 2023, the second terminal region superjunction doping unit 2043, the third terminal region superjunction doping unit 2064, the fourth terminal region superjunction doping unit 2066 and the fifth terminal region superjunction doping unit 2083 are located on a straight line in the thickness direction.
It should be noted that the fourth semiconductor layer 208 includes at least one fifth epitaxial layer 2081, and a fifth cell region super-junction doping unit 2082 and a fifth terminal region super-junction doping unit 2083 are formed on an upper surface layer of each fifth epitaxial layer 2081. In this embodiment, the forming process of the fourth semiconductor layer 208 is described by taking the example that the second semiconductor layer 204 includes one layer of the second epitaxial layer 2041, and the method includes the following steps:
(1) As shown in fig. 10, the fifth epitaxial layer 2081 is grown on the third semiconductor layer 206, and the thickness of the fifth epitaxial layer 2081 may be set according to the device performance requirement, which is not particularly limited in the present invention.
(2) Continuing with fig. 10, a photoresist layer 209 is formed on the fifth epitaxial layer 2081, and the photoresist layer 209 is patterned by a photolithography process such as exposure, development, etc., to expose the cell region superjunction pillar region and the termination region superjunction pillar region.
(3) As further shown in fig. 10, the fifth cell region super-junction doping unit 2082 and the fifth terminal region super-junction doping unit 2083 are formed on the upper surface layer of the fifth epitaxial layer 2081 by ion implantation.
Referring to fig. 11 again, the step S5 is performed: annealing is performed to make the first, second, third, fourth and fifth unit super-junction doping units 2022, 2042, 2063, 2065 and 2802 diffusion connect to form a unit cell super-junction column 210, so that the first, second, third, fourth and fifth unit super-junction doping units 2023, 2043, 2064, 2066 and 2083 diffusion connect to form a terminal super-junction column 211.
Specifically, the purpose of the annealing treatment is to diffuse ions in each doping unit through the high temperature effect to obtain a super junction column connected into a sugarcoated haw shape, the annealing treatment can be realized in a furnace tube, and the specific annealing temperature can be adjusted according to actual conditions.
Specifically, as shown in fig. 11, the cell region superjunction column 210 includes a first cell region superjunction diffusion region a, a second cell region superjunction diffusion region B, a third cell region superjunction diffusion region C and a fourth cell region superjunction diffusion region D sequentially connected from bottom to top, the first cell region superjunction diffusion region a includes a first cell region superjunction diffusion unit 2101, the second cell region superjunction diffusion region B includes one or a plurality of second cell region superjunction diffusion units 2102 stacked in a thickness direction, the second cell region superjunction diffusion units 2102 are located right above the first cell region superjunction diffusion units 2102, the third cell region superjunction diffusion region C includes one or a plurality of third cell region superjunction sub diffusion regions E stacked in the thickness direction, the third cell region superjunction diffusion region E includes a third cell region superjunction diffusion unit 2103 and a fourth cell region superjunction diffusion unit 2104 stacked in a thickness direction, the third cell region superjunction diffusion unit 2103 deviates from the first cell region superjunction diffusion unit 2101 by a preset distance in a first side in a width direction, the fourth cell region superjunction diffusion unit 2104 deviates from the first cell region superjunction diffusion unit 2101 by a preset distance in a second side opposite to the first side in the width direction, the fourth cell region superjunction diffusion region D includes one or a plurality of fifth cell region superjunction diffusion units 2105 stacked in the thickness direction, and the fifth cell region superjunction diffusion unit 2105 is located right above the first cell region superjunction diffusion unit 2101. That is, the cell region superjunction pillars 210 are staggered in a certain section (the third cell region superjunction diffusion region C) and the positions of some diffusion units (the third cell region superjunction diffusion units 2103 and the fourth cell region superjunction diffusion units 2104) are staggered.
Specifically, in the process of forming the superjunction column, the surface of the device is balanced between the P type and the N type through the photomask definition, and the positions of some diffusion units of the superjunction column 210 in the cellular region are staggered left and right, so that the distribution of carriers (such as holes) of the device under a short-circuit working condition can be improved, the density of carriers originally concentrated in the center of the superjunction column is uniformly distributed to the superjunction diffusion region C in the third cellular region, thereby obtaining better short-circuit tolerance capability, and meanwhile, the breakdown voltage of the device is kept unchanged, so that no loss is caused to the process window of the ion implantation of the superjunction column.
Specifically, as shown in fig. 11, the terminal region superjunction pillar 211 is composed of a first terminal region superjunction diffusion unit 2111, at least one second terminal region superjunction diffusion unit 2112, at least one third terminal region superjunction diffusion unit 2113, at least one fourth terminal region superjunction diffusion unit 2114 and at least one fifth terminal region superjunction diffusion unit 2115, and in some embodiments, the first terminal region superjunction diffusion unit 2111, the second terminal region superjunction diffusion unit 2112, the third terminal region superjunction diffusion unit 2113, the fourth terminal region superjunction diffusion unit 2114 and the fifth terminal region superjunction diffusion unit 2115 that compose the terminal region superjunction pillar 211 are located on a straight line in a thickness direction.
As an example, the preparation method of the multilayer epitaxial super junction field effect transistor of the present invention further comprises the following steps:
referring to fig. 12, a field oxide layer 212 is formed on the fourth semiconductor layer 208, wherein the field oxide layer 212 covers the terminal region super junction pillar 211.
As an example, forming the field oxide layer 212 includes the steps of:
(1) Growing a silicon dioxide layer with a certain thickness by a furnace tube wet oxygen method;
(2) Forming a photoresist layer 213, defining an active region through the photoresist;
(3) The silicon dioxide layer of the active region is etched cleanly by wet etching, and the silicon dioxide layer which is not removed is blocked by photoresist to serve as the field oxide layer 212.
Referring to fig. 13, a gate structure 214 is formed on the fourth semiconductor layer 208, the gate structure 214 is located at one side of the super junction pillar 210 in the cellular region, and the gate structure 214 includes a gate dielectric layer 2141 and a gate conductive layer 2142 located on the gate dielectric layer 2141.
As an example, forming the gate structure 214 includes the steps of:
(1) Growing a silicon dioxide layer with a certain thickness by a furnace tube thermal oxidation method;
(2) Growing a layer of polysilicon with a certain thickness on the surface of the silicon dioxide layer through a furnace tube process;
(3) Defining a gate region through the photoresist;
(4) Polysilicon and silicon dioxide in other areas are removed by dry etching.
As an example, a portion of the polysilicon remains on the field oxide layer 212.
Referring to fig. 14, a body 215 is formed on the top surface of the fourth semiconductor layer 208, the body 215 is opposite to the fifth cell super junction doped unit 2082, and the bottom surface of the body 215 is higher than the bottom surface of the fifth cell super junction doped unit 2082 (i.e., the fifth cell super junction diffusion unit 2105) located at the top layer and after diffusion, and then a source 216 is formed on the top surface of the body 215.
As an example, when a P-pillar is selected for the superjunction pillar, the body 215 is also P-type, and the source 216 is N-type, and in some embodiments, the body 215 is formed by boron ion implantation, and the source is defined by photoresist, and then the N-type heavily doped source 216 is formed by phosphorus ion implantation. Here, "heavily doped" is a relative concept, and a specific doping concentration may be set according to actual needs, and the present invention is not particularly limited.
Referring to fig. 15, an interlayer dielectric layer 217 is formed on the fourth semiconductor layer 208 to cover the gate structure 214, and a contact hole 218 is formed in the interlayer dielectric layer 217.
In some embodiments, a layer of borosilicate glass with a certain thickness and a plasma enhanced tetraethyl orthosilicate (PE-TEOS) are grown as the interlayer dielectric layer 217 by a chemical vapor deposition process, and then a contact hole area is defined by photoresist, and the contact hole 218 is etched by dry method.
Referring to fig. 16, a front metal interconnect layer 219 is formed on the interlayer dielectric layer 217 and in the contact hole 218.
In some embodiments, the front metal interconnect layer 219 is formed by physical vapor deposition of a metal layer having a certain thickness, then patterning the interconnect layer by photoresist, and then dry etching.
As an example, the material of the front metal interconnect layer 219 may be aluminum copper alloy or other suitable material.
Referring to fig. 17, the substrate 101 is thinned from the back side, and a back side metal layer 220 is formed on the back side of the substrate 101.
By way of example, the back metal layer 220 may be selected from a Ti/Ni/Au stack or other suitable metal stack.
In the preparation method of the multilayer epitaxial superjunction field effect transistor, the superjunction column of the cellular region is formed by diffusion connection of a first superjunction doping unit of the cellular region, a second superjunction doping unit of the cellular region, a superjunction doping unit of the ternary region, a superjunction doping unit of the quaternary region and a superjunction doping unit of the quinary region, wherein the superjunction doping unit of the ternary region deviates from the superjunction doping unit of the first cellular region by a preset distance in the width direction, and the superjunction doping unit of the quaternary region deviates from the superjunction doping unit of the first cellular region by a preset distance in the width direction, and the superjunction column of the cellular region can improve the short-circuit tolerance capability of the multilayer epitaxial superjunction field effect transistor, and particularly can improve the short-circuit tolerance time and reduce the heating during the short-circuit, for example, when the superjunction device works under a short-circuit working condition, the short-circuit tolerance time can be increased by 25%, and the device temperature before the short-circuit protection is started can be reduced by 30-50 ℃.
Example two
The invention also provides a multilayer epitaxial superjunction field effect transistor which can be prepared by adopting the preparation method of the multilayer epitaxial superjunction field effect transistor as described in the first embodiment, and can also be prepared by adopting other suitable methods.
Specifically, referring to fig. 17, a schematic structural diagram of the multi-layer epitaxial superjunction field effect transistor is shown, which includes a substrate 101, an epitaxial layer, a cell region superjunction pillar 210 and a terminal region superjunction pillar 211, wherein the epitaxial layer is located on the substrate 101, the cell region superjunction pillar 210 and the terminal region superjunction pillar 211 are both located in the epitaxial layer, and the bottom surfaces of the cell region superjunction pillar 210 and the terminal region superjunction pillar 211 are both higher than the bottom surface of the epitaxial layer.
In particular, the epitaxial layers may be formed by stacking a plurality of sub-epitaxial layers, for example, as shown in fig. 17, including a first epitaxial layer 2021, two second epitaxial layers 2041, two third epitaxial layers 2061/fourth epitaxial layers 2062, and a fifth epitaxial layer 2081. In other embodiments, the number of sub-epi layers included in the epi layer may be increased or decreased as needed, which should not unduly limit the scope of the present invention.
Specifically, referring to fig. 11, the cell region superjunction column 210 includes a first cell region superjunction diffusion region a, a second cell region superjunction diffusion region B, a third cell region superjunction diffusion region C, and a fourth cell region superjunction diffusion region D sequentially connected from bottom to top, where the first cell region superjunction diffusion region a includes a first cell region superjunction diffusion unit 2101, the second cell region superjunction diffusion region B includes one or more second cell region superjunction diffusion units 2102 stacked in a thickness direction, the second cell region superjunction diffusion unit 2102 is located directly above the first cell region superjunction diffusion unit 2102, the third cell region superjunction diffusion region C includes one or more third cell region superjunction sub diffusion regions E stacked in the thickness direction, the third cell region superjunction diffusion region E includes a third cell region superjunction diffusion unit 2103 and a fourth cell region superjunction diffusion unit 2104 stacked in a thickness direction, the third cell region superjunction diffusion unit 2103 deviates from the first cell region superjunction diffusion unit 2101 by a preset distance in a first side in a width direction, the fourth cell region superjunction diffusion unit 2104 deviates from the first cell region superjunction diffusion unit 2101 by a preset distance in a second side opposite to the first side in the width direction, the fourth cell region superjunction diffusion region D includes one or a plurality of fifth cell region superjunction diffusion units 2105 stacked in the thickness direction, and the fifth cell region superjunction diffusion unit 2105 is located right above the first cell region superjunction diffusion unit 2101. That is, the cell region superjunction column 210 is in a certain section (the third cell region superjunction diffusion region C), and the positions of some diffusion units (the third cell region superjunction diffusion unit 2103 and the fourth cell region superjunction diffusion unit 2104) are staggered left and right, so that the cell region superjunction column structure can improve the distribution of carriers (such as holes) of the device under the short-circuit working condition, and uniformly distribute the density of carriers originally concentrated in the center of the superjunction column to the third cell region superjunction diffusion region C, thereby obtaining better short-circuit tolerance capability, and meanwhile, the breakdown voltage of the device is kept unchanged.
As an example, the third cell region superjunction diffusion unit 2103 is offset from the first cell region superjunction diffusion unit 2101 by a distance of 10% -40% of the width of the first cell region superjunction diffusion unit 2101 in the width direction, and the fourth cell region superjunction diffusion unit 2104 is offset from the first cell region superjunction diffusion unit 2101 by a distance of 10% -40% of the width of the first cell region superjunction diffusion unit 2101 in the width direction on the second side opposite to the first side.
Specifically, the terminal region superjunction pillar 211 is composed of a first terminal region superjunction diffusion unit 2111, at least one second terminal region superjunction diffusion unit 2112, at least one third terminal region superjunction diffusion unit 2113, at least one fourth terminal region superjunction diffusion unit 2114 and at least one fifth terminal region superjunction diffusion unit 2115, and in some embodiments, the first terminal region superjunction diffusion unit 2111, the second terminal region superjunction diffusion unit 2112, the third terminal region superjunction diffusion unit 2113, the fourth terminal region superjunction diffusion unit 2114 and the fifth terminal region superjunction diffusion unit 2115 that compose the terminal region superjunction pillar 211 are located on a straight line in a thickness direction.
As an example, the multi-layer epitaxial superjunction field effect transistor further includes a field oxide layer 212, a gate structure 214, a body region 215, a source region 216, an interlayer dielectric layer 217, a contact hole 218, a front metal interconnection layer 219, and a back metal layer 220, wherein the field oxide layer 212 is located on the epitaxial layer, the field oxide layer 212 covers the terminal region superjunction pillar 211, the gate structure 214 is located on the epitaxial layer and is disposed on one side of the cell region superjunction pillar 210, the gate structure 214 includes a gate dielectric layer 2141 and a gate conductive layer 2142 located on the gate dielectric layer 2141, the body region 215 is located on an upper surface layer of the epitaxial layer and faces the fifth cell region superjunction diffusion unit 2105, the bottom surface of the body region 215 is higher than the bottom surface of the fifth cell region superjunction diffusion unit 2105 located on the topmost layer, the interlayer dielectric layer 217 is located on the epitaxial layer and covers the gate structure 214, the body region 215 is located on the contact hole 218 is located on the front metal interconnection layer 101 and the back metal layer 220.
In the multilayer epitaxial superjunction field effect transistor of the invention, the first superjunction diffusion unit 2101, the second superjunction diffusion unit 2102, the third superjunction diffusion unit 2103 and the fourth superjunction diffusion unit 2104 which form the superjunction column 210 are not in the same straight line in the thickness direction, and the unit positions of some sections of the superjunction column are staggered left and right, so that the carrier distribution of the device under the short-circuit working condition is improved, and the device obtains better short-circuit tolerance capability.
In summary, in the multilayer epitaxial superjunction field effect transistor and the preparation method thereof, the superjunction column of the cellular region is formed by diffusion connection of the superjunction doping unit of the first cellular region, the superjunction doping unit of the second cellular region, the superjunction doping unit of the third cellular region, the superjunction doping unit of the fourth cellular region and the superjunction doping unit of the fifth cellular region, wherein the superjunction doping unit of the third cellular region deviates from the superjunction doping unit of the first cellular region by a preset distance in the width direction, the superjunction doping unit of the fourth cellular region deviates from the superjunction doping unit of the first cellular region by a preset distance in the width direction in the second side opposite to the first side, and the superjunction column of the cellular region can improve the short-circuit tolerance capability of the multilayer epitaxial superjunction field effect transistor. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the multilayer epitaxial super junction field effect transistor is characterized by comprising the following steps of:
providing a substrate, forming a first semiconductor layer on the substrate, wherein the first semiconductor layer comprises a first epitaxial layer, a first unitary cell area super junction doping unit and a first terminal area super junction doping unit, wherein the first unitary cell area super junction doping unit and the first terminal area super junction doping unit are positioned on the upper surface layer of the first epitaxial layer;
forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises at least one second epitaxial layer, a second cell region super-junction doping unit and a second terminal region super-junction doping unit are formed on the upper surface layer of each second epitaxial layer, and the second cell region super-junction doping unit is positioned right above the first cell region super-junction doping unit;
Forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer comprises at least one double-layer structure, each double-layer structure comprises a third epitaxial layer and a fourth epitaxial layer positioned on the third epitaxial layer, a third cell region superjunction doping unit and a third terminal region superjunction doping unit are formed on the upper surface layer of each third epitaxial layer, a fourth cell region superjunction doping unit and a fourth terminal region superjunction doping unit are formed on the upper surface layer of each fourth epitaxial layer, the third cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction, and the fourth cell region superjunction doping unit deviates from the first cell region superjunction doping unit by a preset distance in the width direction on a second side opposite to the first side;
forming a fourth semiconductor layer on the third semiconductor layer, wherein the fourth semiconductor layer comprises at least one fifth epitaxial layer, a fifth cell region super-junction doping unit and a fifth terminal region super-junction doping unit are formed on the upper surface layer of each fifth epitaxial layer, and the fifth cell region super-junction doping unit is positioned right above the first cell region super-junction doping unit;
And annealing treatment is carried out so that the first cell region superjunction doping unit, the second cell region superjunction doping unit, the third cell region superjunction doping unit, the fourth cell region superjunction doping unit and the fifth cell region superjunction doping unit are in diffusion connection to form a cell region superjunction column, and the first terminal region superjunction doping unit, the second terminal region superjunction doping unit, the third terminal region superjunction doping unit, the fourth terminal region superjunction doping unit and the fifth terminal region superjunction doping unit are in diffusion connection to form a terminal region superjunction column.
2. The method of manufacturing a multilayer epitaxial superjunction field effect transistor of claim 1, wherein: the first terminal region super-junction doping unit, the second terminal region super-junction doping unit, the third terminal region super-junction doping unit, the fourth terminal region super-junction doping unit and the fifth terminal region super-junction doping unit are positioned on the same straight line in the thickness direction.
3. The method of manufacturing a multilayer epitaxial superjunction field effect transistor of claim 1, wherein: the widths of the first cell region superjunction doping unit, the second cell region superjunction doping unit, the third cell region superjunction doping unit, the fourth cell region superjunction doping unit and the fifth cell region superjunction doping unit are the same, and the widths of the first terminal region superjunction doping unit, the second terminal region superjunction doping unit, the third terminal region superjunction doping unit, the fourth terminal region superjunction doping unit and the fifth terminal region superjunction doping unit are the same.
4. The method of manufacturing a multilayer epitaxial superjunction field effect transistor of claim 1, wherein: the distance of the third cell region superjunction doping unit deviating from the first cell region superjunction doping unit to the first side in the width direction is 10% -40% of the width of the first cell region superjunction doping unit, and the distance of the fourth cell region superjunction doping unit deviating from the first cell region superjunction doping unit to the second side opposite to the first side in the width direction is 10% -40% of the width of the first cell region superjunction doping unit.
5. The method of manufacturing a multilayer epitaxial superjunction field effect transistor of claim 1, wherein: the number of the cell area superjunction columns is a plurality, and the cell area superjunction columns are sequentially and alternately arranged in the width direction of the cell area superjunction columns; the number of the terminal area super-junction columns is multiple, and the terminal area super-junction columns are sequentially and alternately arranged in the width direction; the width of the terminal area super junction column is larger than that of the cell area super junction column, and the distance between two adjacent terminal area super junction columns is larger than that between two adjacent cell area super junction columns.
6. The method of fabricating a multilayer epitaxial superjunction field effect transistor of claim 1, further comprising the steps of:
Forming a field oxide layer on the fourth semiconductor layer, wherein the field oxide layer covers the terminal area super junction column;
forming a gate structure on the fourth semiconductor layer, wherein the gate structure is positioned at one side of the superjunction column of the cellular region and comprises a gate dielectric layer and a gate conducting layer positioned on the gate dielectric layer;
forming a body region on the upper surface layer of the fourth semiconductor layer, wherein the body region is opposite to the fifth cell region super-junction doping unit, and the bottom surface of the body region is higher than the bottom surface of the fifth cell region super-junction doping unit which is positioned at the topmost layer and after diffusion;
forming a source region on the upper surface layer of the body region;
forming an interlayer dielectric layer covering the gate structure on the fourth semiconductor layer;
forming a contact hole in the interlayer dielectric layer;
forming a front metal interconnection layer on the interlayer dielectric layer and in the contact hole;
thinning the substrate from the back side;
and forming a back metal layer on the back of the substrate.
7. The method of manufacturing a multilayer epitaxial superjunction field effect transistor of claim 1, wherein: the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the fifth epitaxial layer are all of a first conductivity type, the cell region superjunction column and the terminal region superjunction column are both of a second conductivity type opposite to the first conductivity type, and the first conductivity type is N-type or P-type.
8. A multilayer epitaxial superjunction field effect transistor, comprising:
a substrate;
an epitaxial layer on the substrate;
the cell region superjunction column is positioned in the epitaxial layer, the bottom surface of the cell region superjunction column is higher than the bottom surface of the epitaxial layer, the cell region superjunction column comprises a first cell region superjunction diffusion region, a second cell region superjunction diffusion region, a third cell region superjunction diffusion region and a fourth cell region superjunction diffusion region which are sequentially connected from bottom to top, the first cell region superjunction diffusion region comprises a first cell region superjunction diffusion unit, the second cell region superjunction diffusion region comprises one or a plurality of second cell region superjunction diffusion units stacked in the thickness direction, the second cell region superjunction diffusion unit is positioned right above the first cell region superjunction diffusion unit, the first cell region superjunction diffusion region comprises one or a plurality of first cell region superjunction diffusion regions stacked in the thickness direction, the first cell region superjunction diffusion region comprises a third cell region superjunction diffusion unit and a fourth cell region superjunction diffusion unit stacked in the thickness direction, the second cell region superjunction diffusion unit is positioned on one side of the first cell region and the side of the first cell diffusion unit, the first cell region is positioned on the side of the first cell diffusion unit in the thickness direction, and the first cell region is positioned on the side of the first cell diffusion unit in the first cell region;
And the terminal area super junction column is positioned in the epitaxial layer, and the bottom surface of the terminal area super junction column is higher than the bottom surface of the epitaxial layer.
9. The multilayer epitaxial superjunction field effect transistor of claim 8, wherein: the distance of the third cell area superjunction diffusion unit deviating from the first cell area superjunction diffusion unit towards the first side in the width direction is 10% -40% of the width of the first cell area superjunction diffusion unit, and the distance of the fourth cell area superjunction diffusion unit deviating from the first cell area superjunction diffusion unit towards the second side opposite to the first side in the width direction is 10% -40% of the width of the first cell area superjunction diffusion unit.
10. The multilayer epitaxial superjunction field effect transistor of claim 8, further comprising:
the field oxide layer is positioned on the epitaxial layer and covers the terminal area super junction column;
the grid structure is positioned on the epitaxial layer and arranged on one side of the superjunction column of the cellular region, and comprises a grid dielectric layer and a grid conducting layer positioned on the grid dielectric layer;
the body region is positioned on the upper surface layer of the epitaxial layer and is opposite to the fifth cell region superjunction diffusion unit, and the bottom surface of the body region is higher than the bottom surface of the fifth cell region superjunction diffusion unit positioned on the topmost layer;
The source region is positioned on the upper surface layer of the body region;
the interlayer dielectric layer is positioned on the epitaxial layer and covers the grid structure;
the contact hole is positioned in the interlayer dielectric layer;
the front metal interconnection layer is positioned on the interlayer dielectric layer and in the contact hole;
and the back metal layer is positioned on the back of the substrate.
CN202311789978.6A 2023-12-22 2023-12-22 Multilayer epitaxial super-junction field effect transistor and preparation method thereof Pending CN117711948A (en)

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