CN117709260A

CN117709260A - Chip design method and device, electronic equipment and readable storage medium

Info

Publication number: CN117709260A
Application number: CN202410146610.6A
Authority: CN
Inventors: 任睿; 唐丹; 包云岗
Original assignee: Beijing Open Source Chip Research Institute
Current assignee: Beijing Open Source Chip Research Institute
Priority date: 2024-02-01
Filing date: 2024-02-01
Publication date: 2024-03-15
Anticipated expiration: 2044-02-01

Abstract

The embodiment of the invention provides a chip design method, a chip design device, electronic equipment and a readable storage medium, and relates to the technical field of computers, wherein the method comprises the following steps: acquiring a target top-level template file and a configuration file template; the target top-level template file comprises top-level logic codes for realizing target design requirements; generating a target configuration file based on the configuration file template and at least two target modules; the target configuration file is used for recording module configuration information corresponding to at least two target modules; and generating target chip codes meeting target design requirements based on the target top-level template file and the target configuration file. In the embodiment of the invention, a user does not need to write codes manually, the whole chip design process is automatic, the chip design flow is simplified, the chip design complexity is reduced, and the chip design efficiency is improved on the premise of ensuring the chip design effect.

Description

Chip design method and device, electronic equipment and readable storage medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a chip design method, a device, an electronic apparatus, and a readable storage medium.

Background

A System on Chip (SoC), also known as a System on Chip, is an integrated circuit that integrates a compute processor and other electronic systems into a single Chip.

In the design process of the system-in-chip, an engineer often writes codes manually according to design requirements to obtain SoC codes. However, because the connection relationship between each module in the SoC is complex and the parameters are numerous, the chip design time spent by manually writing the code is long and the chip design efficiency is low.

Disclosure of Invention

The embodiment of the invention provides a chip design method, a chip design device, electronic equipment and a readable storage medium, which can solve the problem of lower chip design efficiency in the related technology.

In order to solve the above problems, an embodiment of the present invention discloses a chip design method, which includes:

acquiring a target top-level template file and a configuration file template; the target top-level template file comprises top-level logic codes for realizing target design requirements;

generating a target configuration file based on the configuration file template and at least two target modules; the target configuration file is used for recording module configuration information corresponding to the at least two target modules;

And generating target chip codes meeting the target design requirements based on the target top-level template file and the target configuration file.

In another aspect, an embodiment of the present invention discloses a chip design apparatus, including:

the template acquisition module is used for acquiring a target top-level template file and a configuration file template; the target top-level template file comprises top-level logic codes for realizing target design requirements;

the file generation module is used for generating a target configuration file based on the configuration file template and at least two target modules; the target configuration file is used for recording module configuration information corresponding to the at least two target modules;

and the code generation module is used for generating target chip codes meeting the target design requirements based on the target top-layer template file and the target configuration file.

In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions which enable the processor to execute the chip design method.

The embodiment of the invention also discloses a readable storage medium, which enables the electronic equipment to execute the chip design method when the instructions in the readable storage medium are executed by the processor of the electronic equipment.

The embodiment of the invention has the following advantages:

the embodiment of the invention provides a chip design method, which can be used for generating a target configuration file based on a configuration file template and at least two target modules by acquiring a target top layer template file and a configuration file template, and automatically generating a target chip code meeting target design requirements based on the target top layer template file and the target configuration file. In the embodiment of the invention, a user does not need to write codes manually, the whole chip design process is automatic, the chip design flow is simplified, the chip design complexity is reduced, and the chip design efficiency is improved on the premise of ensuring the chip design effect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of steps of an embodiment of a chip design method of the present invention;

FIG. 2 is a flowchart illustrating steps of an embodiment of a chip design method according to the present invention;

FIG. 3 is a block diagram of an embodiment of a chip design apparatus of the present invention;

fig. 4 is a block diagram of an electronic device for chip design according to an example of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.

Method embodiment

Referring to fig. 1, a flowchart illustrating steps of an embodiment of a chip design method of the present invention is shown, and the method may specifically include the steps of:

step 101, acquiring a target top-level template file and a configuration file template; the target top-level template file comprises top-level logic codes for realizing target design requirements;

102, generating a target configuration file based on the configuration file template and at least two target modules; the target configuration file is used for recording module configuration information corresponding to the at least two target modules;

and step 103, generating a target chip code based on the target top-level template file and the target configuration file.

In the embodiment of the invention, the target top-level template file comprises top-level logic codes for realizing target design requirements. The target top-level template file may be obtained by rewriting a determined and executable preset top-level code file based on preset rules. The preset top-level code file is determined and executable chip code, such as SoC code, and may be verilog code. verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form, and may represent logic circuit diagrams, logic expressions, and logic functions performed by a digital logic system. Illustratively, the preset top-level code file in the embodiment of the present invention may include basic components of a generic SoC chip and necessary supporting tools, such as UART, QSPI, chipLink, VGA and SDRAM, and may further include some basic interface components. The preset rule may be a design specification of the target code language, and specifically may include a code writing specification and a template engine specification of the target code language, where the process of writing the preset top-level code file needs to conform to the code writing specification and the template engine specification. And (3) rewriting the preset top-level code file based on a preset rule to obtain a top-level logic code for generating the target chip code, namely the target top-level template file.

SoC (System on Chip), i.e. a system-on-chip, also called system-on-chip, means that it is a product, which is an integrated circuit with dedicated targets, containing the complete system and having the entire contents of embedded software. The configuration of the system-on-chip may include a system-on-chip control logic module, a microprocessor/microcontroller core module, a digital signal processing (Digital Signal Processing, DSP) module, an embedded memory module, a port module for communicating with the outside, an analog front end module containing an analog-to-digital converter/digital-to-analog converter (Analog to Digital Converter/Digital to Analog Converter, ADC/DAC), a power supply and power management module, and the like. It can be understood that the chip design method provided by the embodiment of the invention is used for designing the SoC chip, and correspondingly, the target chip code in the embodiment of the invention is the SoC code.

In order to further improve the chip design efficiency, a configuration file template may be predefined, where the configuration file template may include module information and configuration parameter information of the module.

It should be noted that, the target module (or module) in the embodiment of the present invention refers to IP (Intellectual Property) in the chip, that is, an integrated circuit module with intellectual property, which may also be referred to as an IP Core (IP Core), and is a mature design of a circuit module with an independent function in the chip, and the circuit module design may be applied to other chip design projects including the circuit module, so as to reduce design workload, shorten design period, and improve success rate of chip design. An IP core may also be understood as an intermediate component of a chip design.

Illustratively, the target module may be an IP selected by the user from a preset IP library to be integrated in the SoC chip, and may include, but is not limited to: core module, peripheral hardware module and storage module etc.. The Core modules may include RISC-V processor cores (RISC-V cores), and the like; the peripheral modules may include Universal Asynchronous Receiver Transmitter (UART), integrated circuit bus (Inter-Integrated Circuit, I2C), serial Peripheral Interface (SPI), etc.; the Memory module may include a static random access Memory (Static Random Access Memory, SRAM), a dynamic random access Memory (Dynamic Random Access Memory, DRAM), a Read-Only Memory (ROM), and the like. The different target modules have different functions and different applicable fields, and at least two target modules meeting the design requirements of the user can be determined according to the design requirements of the user.

Alternatively, the target module may be a self-grinding IP of the user. It will be appreciated that if a user were to generate SoC codes based on self-lapping IP, it would be necessary to provide the IP design codes and configuration parameters of the self-lapping IP. IP design code refers to HDL text of a circuit module designed in hardware description language (Hardware Description Language, HDL) with independent functions, such as Register-Transfer Level (RTL) code. The configuration parameters are used for reflecting the integration requirements corresponding to the self-research IP of the user, and specifically can comprise the parameters corresponding to the IP core, the interface protocol, the signal mapping relation, the bit width requirements and the like which need to be integrated.

The target configuration file is used for recording module configuration information corresponding to the at least two target modules, for example, the target configuration file may include module information of the target module, association information between the target module and other modules, and the like. The module information of the target module may include a module name or a module identifier of the target module, interface information (including input interface input, output interface output, and bidirectional interface in/output, etc.), configuration parameters (such as interface protocol, signal mapping relation, bit width requirement, etc.), and module start information (including a port list corresponding to the target module and a module name of the target module, etc.). The association information is used for reflecting the connection relation and the time sequence relation between the target module and other modules.

In the embodiment of the invention, the target configuration file can be generated by a template engine based on a predefined configuration file template and at least two target modules. For example, the module names or module identifications corresponding to at least two target modules may be determined first, then the module information and the associated information corresponding to the target modules are obtained based on the module names or the module identifications, and further the required target configuration file is rendered through the template engine based on the predefined configuration file template, the module information and the associated information corresponding to the at least two target modules. The template engine is a general tool for generating output text (such as an HTML web page, an email, a configuration file, source code, etc.) based on templates and parameter data. The template engine can separate the program implementation interface from data, separate the service code from the logic code, effectively improve the code development efficiency, and facilitate code reuse through the design of the template code. By way of example, the Python template engine may include Mako, jinja2, and the like.

Finally, based on the target top-level template file and the target configuration file, a target chip code meeting the target design requirement can be generated. The target chip code may include RTL codes of respective functional modules on the SoC chip, such as a functional code corresponding to a core (core), a code corresponding to an interrupt module, a code corresponding to a clock module, and so on. For example, the IP design code corresponding to the target module may be inserted into the target top-level template file based on the target configuration file, to obtain the target chip code. For example, signals with mapping relation between the target module and other modules in the target top-level template file can be renamed according to the signal mapping relation between the target module and other modules in the target top-level template file, and interface conversion is performed on interface components in the target module based on an interface protocol, so that the interface components are adapted to the interface components in the target top-level template file. In addition, the target module and the target top template file can be subjected to bit width matching based on bit width requirements, and the like.

In an alternative embodiment of the present invention, step 101 of obtaining the target top-level template file may include the following steps:

step S11, dividing a preset top-level code file to obtain a first code sub-file and a second code sub-file; the first code sub file is a chip code for realizing a general function; the second code subfile is a chip code for realizing a specific function;

and step S12, based on the design specification of the target code language, rewriting the first code subfile and the second code subfile, and determining a target top template file.

In the embodiment of the present invention, the preset top-level code file may be an executable top-level code file written in advance, for example, an executable top-level verilog code written by an encoding engineer. The preset top-level code file comprises a first code sub-file corresponding to a general module for realizing a general function and a second code sub-file corresponding to a special module for realizing a specific function. The first code sub-file can include code content with similar format and content in the chip design process of different fields. In general, the first code subfile may be a chip code (SoC code) that is commonly used in a chip design process. By way of example, the general functions may include storage, communication, and the like, and the general modules may be modules for implementing the storage function, modules for implementing the communication function, and the like. The second code subfile may include code contents corresponding to a specific module designed based on different design requirements or design requirements of different chip design fields for implementing a specific function. It is understood that in the chip design process, the specific code content written in the adaptive design according to different design requirements or design requirements in different chip design fields can be divided into the second code subfiles. For example, the specific function may be a bluetooth function, and accordingly, the specific module may be a bluetooth module. Wherein, the first code subfiles for realizing the general functions in the top-level code files of different chip design fields may be the same, and the second code subfiles for realizing the specific functions in the top-level code files of different chip design fields may be different.

Dividing a first code sub-file and a second code sub-file in a preset top-level code file, and rewriting the first code sub-file and the second code sub-file based on design specifications of the first code sub-file, the second code sub-file and the target code language, which are obtained by dividing, so as to obtain a target top-level template file. For example, a first code subfile may be rewritten to a first template statement conforming to a design specification of the target code language and a second code subfile may be rewritten to a second template statement conforming to the design specification of the target code language, respectively. And determining the rewritten preset top-level code file as a target top-level template file.

In the embodiment of the invention, the target top-level template file is determined by taking the preset top-level code file which is determined in advance and can be executed as a standard and rewriting the first code sub-file and the second code sub-file in the preset top-level code file, and the target top-level template file can be rewritten into a universal target top-level template file based on the code content of the preset top-level code file, so that the automatic design of the SoC chip can be realized directly based on the target top-level template file in the chip design process.

Optionally, step 102 generates a target profile based on the profile template and at least two target modules, and may include the steps of:

step S21, receiving first operation information input by a user;

step S22, determining at least two target modules selected by the user based on the first operation information;

step S23, based on the at least two target modules, module codes corresponding to the at least two target modules and module connection information of the at least two target modules and other modules are obtained from a preset module library;

and step S24, rendering the configuration file template by using a configuration file generator based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target configuration file.

In the embodiment of the invention, the first operation information input by the user and corresponding to the interactive operation can be received through the interactive operation generated by the user on the interactive interface, wherein the mode of the module input information can be words, voices and the like, and the embodiment of the invention is not limited to the words, voices and the like. The interaction modes of the interaction operations generated by the user on the interaction interface include, but are not limited to: input operation, click operation, slide operation, and the like. The first operation information may be determined based on the target design requirement, and may include module names corresponding to at least two target modules on the chip that are desired to be generated. And receiving first operation information input by a user, analyzing and processing based on the first operation information, and determining at least two target modules.

For example, the at least two target modules and the module connection information of the at least two target modules with other modules may include:

ip: uart, spi_device, rv_core, ip_module1, ip_module2, etc.

Connect：uart.input1-ip_module1.output1

spi_device.input2 -ip_module2.output2

Wherein, IP is used for representing the target module; uart is used to represent the target module "universal asynchronous receiver transmitter"; the spi_device is used for representing a target module of 'serial peripheral interface'; rv_core is used to represent the target module "RISC-V processor core"; ip_module1 is used to represent "target module 1"; ip_module2 is used to represent "target module 2". The uart.input1-ip_module1.output1 is used for indicating that the universal asynchronous receiver transmitter input interface 1 is connected with the output interface 1 of the target module 1; the spi_device.input2-ip_module2.output2 is used to indicate that the input interface 2 of the serial peripheral interface is connected to the output interface 2 of the target module2.

As an example, the preset module library may be an IP library, and the preset module library may include module configuration information corresponding to each module. The module configuration information may include a module code corresponding to each module, interface information (including input interface input, output interface output, bidirectional interface input, etc.) of at least two target modules, configuration parameter information, and module start information (including a port list corresponding to a module, a module name of a module, etc.), and association information between each module. The module code may be an RTL code, and the association information may include connection relations of different ports between the modules. The module configuration information corresponding to each module in the preset module library can be predefined by the user according to the design requirement and the design requirement. The module codes and the module configuration information of all the modules in the preset module library are correspondingly stored. For example, the related information of the modules in the preset module library may be stored in the form of key value pairs. For any module, the module name of the module can be used as a main key, and the module configuration information such as the module code corresponding to the module can be used as a key value for corresponding storage.

Based on the module name or the module identifier of the target module, the module configuration information corresponding to at least two target modules can be searched in a preset module library, for example, the module configuration information can include module codes corresponding to the target modules and module connection information of at least two target modules and other modules. The other modules may be at least two target modules, or may be other modules integrated in the SoC chip except for the at least two target modules.

After the module codes and the module connection information corresponding to the at least two target modules are determined, rendering the configuration file template based on the module codes and the module connection information corresponding to the at least two target modules, and thus obtaining the target configuration file. The object configuration file may include a top layer name, interface information (including input interface input, output interface output, and bidirectional interface in/output, etc.), and at least two object modules that need to be integrated. The target profile may be in json format or hjson format, i.e., the target profile may be a json profile or hjson profile. It will be appreciated that the embodiments of the present invention do not limit the form of the target profile. And rendering the configuration file template into a target configuration file based on the module codes and the module configuration information corresponding to the at least two target modules through the configuration file generator. The configuration file generator may be a SoC TOP configuration file generator, and the configuration file generator may be a template engine.

By way of example, the target profile may be:

{

###########main module info##########################

"topname":"top"

"input":[ 'clk,'' rst n,'' [2:0] key in,'miso."]

"output":['output [31:0] out1;']

"wire":['wire [31:0] line1']

"ip_module":

['testname' #(.A(a).B(b))' 'u_testname( ' '.clk(clk)'' .rst(rst)' '.in(in)' '.out(line1)'');'

'testname1' '#(.C(a).D(b))' 'u_testname1( ' ' .clk1(ck)'' .rst1(rst) ' '.in(line1) '' .out(out)'');'

}

according to the embodiment of the invention, the target configuration file meeting the design requirement of the user can be automatically determined based on the module input information and the configuration file template by receiving the module input information input by the user, so that the acquisition efficiency of the target configuration file and the convenience of chip design are improved.

Optionally, step 103 generates a target chip code that meets the target design requirement based on the target top-level template file and the target configuration file, and may include the following steps:

and S31, inputting the target configuration file and the target top-level template file into a chip code generator.

And step S32, rendering the target top template file based on the target configuration file through the chip code generator to obtain the target chip code.

In the embodiment of the invention, after the target configuration file and the target top-level template file are determined, a chip code generator (SoC generator) can be utilized to generate target chip codes, specifically, the target configuration file and the target top-level template file can be input into the chip code generator, and the chip code generator can render the target top-level template file based on the target configuration file to generate final target chip codes. The chip code generator may be a template engine, for example, a Python template engine or a java template engine, where the Python template engine specifically may include: mako, jinja2, etc., the java template engine may specifically include: velocity, freemaker, etc. For example, the target top-level template file may use a special placeholder identifier expression and a code block, and the chip code generator may replace the placeholder included in the target top-level template file based on the parameter information in the target configuration file in the process of generating the target chip code, that is, in the actual process of generating the target chip code, the target top-level template file needs to be subjected to template parsing and template rendering, where the special placeholder included in the target top-level template file is replaced with an actual value representing the corresponding parameter configuration data.

In the embodiment of the invention, the target configuration file and the target top-layer template file are input into the chip code generator, so that the target chip code is automatically generated based on the parameter rendering mode, the chip design time is reduced, and the integration efficiency of SoC top-layer integration is improved.

Optionally, step S24 uses a configuration file generator to render the configuration file template based on the module codes corresponding to the at least two target modules and the module connection information, so as to obtain the target configuration file, and may include the following steps:

step S41, determining the position of the parameter to be rendered based on a preset identifier in the configuration file template;

and step S42, performing parameter rendering on the parameter position to be rendered based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target configuration file.

In the embodiment of the invention, the preset identifier is arranged in the configuration file template, and the preset identifier occupies a space in the configuration file template and is particularly used for indicating the position of the code needing parameter rendering in the configuration file template, so that the code needing parameter rendering can be represented by the preset identifier when the configuration file template is predefined. Accordingly, in the process of generating the target configuration file, the position of the parameter to be rendered needs to be determined based on the preset identifier in the configuration file template, and the position of the parameter to be rendered is used for representing the code part, which needs to be filled with specific parameter content, in the configuration file template. The parameter position to be rendered can be determined by analyzing according to grammar by a configuration file generator, and parameter rendering is carried out on the parameter position to be rendered based on module codes and module connection information corresponding to at least two target modules, for example, the module codes and the module connection information corresponding to the at least two target modules are respectively filled into the parameter position to be rendered according to grammar logic, so that a target configuration file is obtained.

In the embodiment of the invention, the target configuration file is obtained by filling the module codes and the module connection information corresponding to at least two target modules into the positions of the parameters to be rendered, and the target configuration file can be quickly determined by combining the configuration file template, so that the determination efficiency of the target configuration file is improved.

Optionally, step S12 rewrites the first code subfile and the second code subfile based on the design specification of the target code language, and determines the target top-level template file, which may include the steps of:

step S51, generating a first template sentence which accords with the design specification of the target code language based on a first code sub-file in the preset top-level code file;

step S52, a second code subfile in the preset top-level code file is rewritten into a second template sentence which accords with the design specification of the target code language, and a template engine sentence corresponding to the second template sentence is generated; the template engine statement is used for indicating whether the code corresponding to the second template statement is generated in the process of generating the target chip code.

In the embodiment of the invention, the preset top-level code file is a determined executable SoC code, the code content in the preset top-level code file can be carded, key code content, such as key code lines and parameter information, in the preset top-level code file is extracted, and a target top-level template file which accords with the design specification of a target code language is written through a template engine based on the key code content. The preset top code file may include a code corresponding to a general module, i.e., a first code sub-file, and a code corresponding to a special module, i.e., a second code sub-file, where the general module refers to a common module that needs to be included in an SoC chip to implement a general function in a chip design process in different chip design fields, for example: universal Asynchronous Receiver Transmitter (UART), integrated circuit bus (Inter-Integrated Circuit, I2C), serial Peripheral Interface (SPI), and other universal modules. The special module refers to a non-universal module designed in the SoC chip to realize a specific function according to the difference of the design requirements in the process of chip design according to the chip design requirements in different chip design fields.

And utilizing a template engine to rewrite the first code sub-file with a corresponding template sentence conforming to the design specification of the target code language so as to determine the first template sentence. Illustratively, the template engine may be SoC.

Aiming at a second code subfile in a preset top-level code file, due to the differences of different chip design fields and different chip design requirements, when a template engine is utilized to rewrite the second code subfile by using a template sentence conforming to the design specification of the target code language, a template engine sentence corresponding to the second template sentence can be generated while the second template sentence is generated. The template engine statement may be a statement for controlling a program flow, specifically, when generating the target chip code based on the target top-level template file and the target configuration file, the template engine statement may be used to indicate whether a SoC code of a second template statement corresponding to the template engine statement needs to be generated in a process of generating the target chip code, and the template engine statement may control a code generation process of the target chip code. The template engine statements may be Python code, including conditional statements (e.g., if/else), loop statements (e.g., while and for), or other types of template engine statements (e.g., try/except), and so forth. For example: in the process of generating the target chip code, when a template engine statement in a target top-level template file is a conditional statement (for example, if/else), judging the condition corresponding to the template engine statement first and then determining whether to execute a corresponding second template statement; when the template engine statement in the target top-level template file is a loop statement (e.g., while and for), it is necessary to determine whether loop execution is required, and then execute the corresponding second template statement. Illustratively, in the target top-level template file, "%" may be used to mark the beginning and end of the template engine statements. Specifically, in the case where the template engine sentence characterizes the end of the flow control, "% end < name >" may be used as a control terminator (end mark of the template engine sentence), where "< name >" may reserve a word for Python of the template engine sentence.

For example, assuming that an if statement is included in the target top-level template file, when generating the target chip code, the chip code generator needs to make grammar judgment based on the if statement, if it is judged that a second template statement in a certain specific field needs to be added, parameter rendering corresponding to the part of the second template statement corresponding to the template engine statement is executed, so as to generate a corresponding SoC code; otherwise, the part of the second template sentence can be skipped, and parameter rendering is not performed.

Illustratively, the target top-level template file may be:

module top_${top["name"]} #(

// Manually defined parameters

% if not lib. Is_rom_ctrl (top [ "module" ]) # template engine statement

parameter BootRomInitFile = "",

% endif

// Auto-inferred parameters

% for m in top["module"]:

% if not lib.is_inst(m):

<% continue %>

% endif

The content between "%" is the template engine statement in the target top-level template file.

Optionally, the embodiment of the invention further comprises the following steps:

step S61, generating and displaying a template recommendation interface; the template recommendation interface is used for displaying at least two top-level template files to a user;

step S62, receiving second operation information input by the user;

and step S63, determining a target top-level template file which is selected by the user from the at least two top-level template files and meets the target design requirement based on the second operation information.

In the embodiment of the invention, different chip design fields can correspond to different design requirements, at least two top-layer template files can be predefined in advance based on the different design requirements, and each top-layer template file is also configurable, namely, some parameters in the top-layer template files can be set according to different SoC chips. The modules contained in different top-level template files are different, the functions which can be realized are different, and the applicable application fields are different. Under the condition that the target design requirement of the chip is determined, a user can select a target top-level template file meeting the target design requirement from at least two pre-defined top-level template files.

As an example, at least two top-level template files may be presented to a user based on the template recommendation interface, second operation information corresponding to an interactive operation performed by the user on the template recommendation interface is received, and a target top-level template file selected by the user from the at least two top-level template files and meeting a target design requirement is determined. The user can select the template through the template recommendation interface, and under the condition that second operation information input by the user is received, the target top-level template file is determined.

In one possible implementation manner, different top-level template files can be set according to different chip design fields, and target top-level template files meeting target design requirements are selected according to actual target design requirements; the method can also obtain executable preset top-level code files in different chip design fields in advance, extract the same parts in each preset top-level code file based on a plurality of executable preset top-level code files, rewrite the same parts to obtain first template sentences, respectively set a plurality of groups of second template sentences and template engine sentences in different parts in each preset top-level code file, and determine target top-level template files based on the first template sentences, the plurality of groups of second template sentences and corresponding template engine sentences.

In the embodiment of the invention, a plurality of top-layer template files are predefined, and the target top-layer template files meeting the target design requirements are selected according to the target design requirements and applied to the subsequent chip design process, so that comprehensive and diversified top-layer template files are provided for meeting different chip design fields, namely different chip design requirements, and the universality of the chip design method in the embodiment of the invention is improved.

Exemplary, an embodiment of the present invention provides a flowchart of specific steps of a chip design method, as shown in fig. 2, where a preset module library includes module configuration information corresponding to a plurality of modules, where the plurality of modules includes a Universal Asynchronous Receiver Transmitter (UART), a processor core (e.g., RISC-V processor core), an integrated circuit bus (Inter-Integrated Circuit, I2C), a Serial Peripheral Interface (SPI), and so on. And determining module codes and module connection information corresponding to at least two target modules from a preset module library, and obtaining a target configuration file based on a configuration file generator. And inputting the target configuration file and the target top template file into a chip code generator to obtain a target chip code.

In summary, the embodiment of the invention provides a chip design method, which can obtain a target top-layer template file and a configuration file template, generate a target configuration file based on the configuration file template and at least two target modules, and automatically generate a target chip code meeting target design requirements based on the target top-layer template file and the target configuration file. In the embodiment of the invention, a user does not need to write codes manually, the whole chip design process is automatic, the chip design flow is simplified, the chip design complexity is reduced, and the chip design efficiency is improved on the premise of ensuring the chip design effect.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.

Device embodiment

Referring to fig. 3, which shows a block diagram of a chip design apparatus of the present invention, the apparatus 20 may specifically include:

the template acquisition module 201 is configured to acquire a top-level template file and a configuration file template of a target; the target top-level template file comprises top-level logic codes for realizing target design requirements;

a file generating module 202, configured to generate a target configuration file based on the configuration file template and at least two target modules; the target configuration file is used for recording module configuration information corresponding to the at least two target modules;

and the code generating module 203 is configured to generate a target chip code that meets the target design requirement based on the target top-level template file and the target configuration file.

Optionally, the file generation module 202 includes:

the first receiving module is used for receiving first operation information input by a user;

a first determining module for determining at least two target modules selected by the user based on the first operation information;

the first acquisition module is used for acquiring module codes corresponding to the at least two target modules and module connection information of the at least two target modules and other modules from a preset module library based on the at least two target modules;

and the first rendering module is used for rendering the configuration file template by using a configuration file generator based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target configuration file.

Optionally, the first rendering module includes:

the second determining module is used for determining the position of the parameter to be rendered based on the preset identifier in the configuration file template;

and the first rendering sub-module is used for performing parameter rendering on the parameter position to be rendered based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target configuration file.

Optionally, the code generation module 203 includes:

The first input module is used for inputting the target configuration file and the target top-level template file into a chip code generator;

and the second rendering sub-module is used for rendering the target top-layer template file based on the target configuration file through the chip code generator to obtain the target chip code.

Optionally, the template obtaining module 201 includes:

the first dividing module is used for dividing a preset top-level code file to obtain a first code sub-file and a second code sub-file; the first code sub file is a chip code for realizing a general function; the second code subfile is a chip code for realizing a specific function;

and the first rewriting module is used for rewriting the first code subfile and the second code subfile based on the design specification of the target code language, and determining a target top template file.

Optionally, the first rewrite module includes:

the first generation module is used for generating a first template statement conforming to the design specification of the target code language based on a first code sub-file in the preset top-level code file;

the second generation module is used for rewriting a second code subfile in the preset top-level code file into a second template sentence which accords with the design specification of the target code language, and generating a template engine sentence corresponding to the second template sentence; the template engine statement is used for indicating whether the code corresponding to the second template statement is generated in the process of generating the target chip code.

Optionally, the apparatus 20 may specifically further include:

the third generation module is used for generating and displaying a template recommendation interface; the template recommendation interface is used for displaying at least two top-level template files to a user;

the second receiving module is used for receiving second operation information input by the user;

and the third determining module is used for determining a target top-level template file which is selected by the user from the at least two top-level template files and meets the target design requirement based on the second operation information.

In summary, the embodiment of the invention provides a chip design device, which is used for obtaining a target top-layer template file and a configuration file template, generating a target configuration file based on the configuration file template and at least two target modules, and automatically generating a target chip code meeting target design requirements based on the target top-layer template file and the target configuration file. In the embodiment of the invention, a user does not need to write codes manually, the whole chip design process is automatic, the chip design flow is simplified, the chip design complexity is reduced, and the chip design efficiency is improved on the premise of ensuring the chip design effect.

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

The specific manner in which the various modules perform the operations in relation to the processor of the above-described embodiments have been described in detail in relation to the embodiments of the method and will not be described in detail herein.

Referring to fig. 4, a block diagram of an electronic device for chip design according to an embodiment of the present invention is shown. As shown in fig. 4, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions that cause the processor to execute the chip design method of the foregoing embodiment.

The processor may be a CPU (Central Processing Unit ), general purpose processor, DSP (Digital Signal Processor ), ASIC (Application Specific Integrated Circuit, application specific integrated circuit), FPGA (Field Programmable Gate Array ) or other editable device, transistor logic device, hardware components, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.

The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.

The Memory may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory ) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory ), a CD-ROM (Compact Disc Read Only Memory, compact disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, and the like.

Embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device (server or terminal), enables the processor to perform the chip design method shown in fig. 1.

It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The foregoing describes in detail a memory access method, apparatus, electronic device and readable storage medium provided by the present invention, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above description of the examples is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. A method of chip design, the method comprising:

2. The method of claim 1, wherein generating a target profile based on the profile template and at least two target modules comprises:

receiving first operation information input by a user;

determining at least two target modules selected by the user based on the first operation information;

based on the at least two target modules, module codes corresponding to the at least two target modules and module connection information of the at least two target modules and other modules are obtained from a preset module library;

and rendering the configuration file template by using a configuration file generator based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target configuration file.

3. The method according to claim 2, wherein the rendering the profile template with the profile generator based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target profile includes:

determining a parameter position to be rendered based on a preset identifier in the configuration file template;

and carrying out parameter rendering on the parameter position to be rendered based on the module codes corresponding to the at least two target modules and the module connection information to obtain the target configuration file.

4. The method of claim 1, wherein generating the target chip code that meets the target design requirement based on the target top-level template file and the target configuration file comprises:

inputting the target configuration file and the target top template file into a chip code generator;

and rendering the target top-level template file based on the target configuration file through the chip code generator to obtain the target chip code.

5. The method of claim 1, wherein the obtaining the target top-level template file comprises:

Dividing a preset top-level code file to obtain a first code sub-file and a second code sub-file; the first code sub file is a chip code for realizing a general function; the second code subfile is a chip code for realizing a specific function;

and based on the design specification of the target code language, rewriting the first code subfile and the second code subfile to determine a target top template file.

6. The method of claim 5, wherein the writing the first code subfile and the second code subfile based on the design specification of the object code language to determine an object top level template file comprises:

generating a first template sentence which accords with the design specification of the target code language based on a first code sub-file in the preset top-level code file;

rewriting a second code subfile in the preset top-level code file into a second template sentence conforming to the design specification of the target code language, and generating a template engine sentence corresponding to the second template sentence; the template engine statement is used for indicating whether the code corresponding to the second template statement is generated in the process of generating the target chip code.

7. The method according to claim 1, wherein the method further comprises:

generating and displaying a template recommendation interface; the template recommendation interface is used for displaying at least two top-level template files to a user;

receiving second operation information input by the user;

and determining a target top-level template file selected by the user from the at least two top-level template files and meeting the target design requirement based on the second operation information.

8. A chip design apparatus, the apparatus comprising:

9. An electronic device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is configured to store executable instructions that cause the processor to perform the chip design method of any one of claims 1 to 7.

10. A readable storage medium, characterized in that instructions in the readable storage medium, when executed by a processor of an electronic device, enable the processor to perform the chip design method according to any one of claims 1 to 7.