CN113177020A

CN113177020A - Data processing method and device

Info

Publication number: CN113177020A
Application number: CN202110517508.9A
Authority: CN
Inventors: 连络; 侯化成; 梁雨; 徐宁仪
Original assignee: Shanghai Power Tensors Intelligent Technology Co Ltd
Current assignee: Shanghai Power Tensors Intelligent Technology Co Ltd
Priority date: 2021-03-31
Filing date: 2021-05-12
Publication date: 2021-07-27

Abstract

The disclosure relates to the technical field of chips, and particularly provides a data processing method and device. A data processing method, comprising: acquiring information texts corresponding to all register modules in a chip; the information text records the description information of each register in the register module; and generating a design code and a verification code of each register module according to each information text. The method can automatically generate the design and verification codes without manually and repeatedly modifying the codes, reduces the risk of careless mistakes, improves the efficiency of chip design and verification and shortens the research and development time.

Description

Data processing method and device

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a data processing method and apparatus.

Background

With the continuous progress of the process, the structure of the Chip tends to be complicated, and the number of registers required in the Chip is increasing, for example, for a SoC (System on Chip) Chip, the number of registers can reach tens of thousands. The chip needs to continuously modify the relevant information of the register in the design and verification processes, so that a large amount of repeated iterative work is generated, and the research and development efficiency of the chip is reduced.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a data processing method, including:

acquiring information texts corresponding to all register modules in a chip; the information text records the description information of each register in the register module;

and generating a design code and a verification code of each register module according to each information text.

In some embodiments, the obtaining of the information text corresponding to each register module in the chip includes:

acquiring a description text file and a configuration text file corresponding to each register module, wherein the description text file records the description information of each register in the register module;

generating a design code and a verification code of each register module according to each information text, comprising:

addressing according to the configuration text files to obtain the description text files;

integrating to obtain a target information list based on the description information of each description text file;

generating the design code and the verification code based on the description information in the target information list.

In some embodiments, the integrating to obtain the target information list based on the description information of each of the description text files includes:

integrating to obtain a first information list based on the description information of each description text file;

and filling the description information in the first information list to obtain the target information list.

In some embodiments, the data processing method of the present disclosure further includes:

and generating a description file of each register module according to each information text.

In some embodiments, the generating a description file of each register module according to each information text includes:

filling the information text according to the description information corresponding to each information text to obtain a first description file corresponding to each register module;

carrying out format conversion based on the first description file to obtain a second description file; and/or

And integrating and processing the first description files to obtain the top layer description files of the register modules.

In some embodiments, generating a verification code for each register module based on each of the message texts comprises:

and generating a verification code corresponding to each register module and a top verification code of all the register modules according to each information text.

In a second aspect, an embodiment of the present disclosure provides a chip design and verification method, including:

acquiring design codes and verification codes of all register modules of a chip; the design code and the verification code are obtained according to the data processing method of any one of the embodiments of the first aspect;

instantiating the chip according to the design code;

and verifying the chip according to the verification code.

In a third aspect, an embodiment of the present disclosure provides a data processing apparatus, including:

the first acquisition module is configured to acquire information texts corresponding to the register modules in the chip; the information text records the description information of each register in the register module;

and the code generation module is configured to generate a design code and a verification code of each register module according to each information text.

In some embodiments, the first obtaining module is specifically configured to:

and acquiring a description text file and a configuration text file corresponding to each register module, wherein the description text file records the description information of each register in the register module.

In some embodiments, the code generation module is specifically configured to:

In some embodiments, the data processing apparatus of the present disclosure further comprises:

and the file generation module is configured to generate a description file of each register module according to each information text.

In some embodiments, the file generation module is specifically configured to:

In some embodiments, the code generation module is specifically configured to:

In a fourth aspect, an embodiment of the present disclosure provides a chip design and verification apparatus, including:

the second acquisition module is configured to acquire the design codes and the verification codes of the register modules of the chip; the design code and the verification code are obtained according to the data processing method of any one of the embodiments of the first aspect;

an instantiation module configured to instantiate the chip according to the design code;

and the verification module is configured to verify the chip according to the verification code.

In a fifth aspect, the present disclosure provides an electronic device, including:

a processor; and

a memory storing computer instructions readable by the processor, the processor performing the method according to any of the embodiments of the first or second aspect when the computer instructions are read.

In a sixth aspect, the disclosed embodiments provide a storage medium for storing computer-readable instructions for causing a computer to perform the method according to any one of the embodiments of the first or second aspect.

The data processing method of the embodiment of the disclosure comprises the steps of obtaining information texts corresponding to all register modules in a chip, and generating design codes and verification codes of all register modules according to all the information texts. In the process of designing and verifying the chip register module, when the register configuration information is modified, the design and verification codes can be automatically generated only by modifying the corresponding information text, the codes are not required to be modified manually and repeatedly, the risk of careless mistakes caused by manual work is reduced, the efficiency of designing and verifying the chip is improved, and the research and development time is shortened. And the design and verification codes can be simultaneously generated based on the information text of the register module, so that the complete automatic flow of the design and verification stages is realized, and the codes of the two stages have uniform coding styles and are convenient to maintain.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flow chart of a data processing method according to some embodiments of the present disclosure.

Fig. 2 is a flow chart of a data processing method according to some embodiments of the present disclosure.

Fig. 3 is a flow chart of a data processing method according to some embodiments of the present disclosure.

Fig. 4 is a flow chart of a data processing method in some embodiments according to the present disclosure.

FIG. 5 is a schematic diagram of a chip design and verification method according to some embodiments of the present disclosure.

FIG. 6 is a schematic diagram of a data processing method in some embodiments according to the present disclosure.

Fig. 7 is a flow chart of a chip design and verification method in some embodiments according to the present disclosure.

Fig. 8 is a block diagram of a data processing apparatus according to some embodiments of the present disclosure.

FIG. 9 is a block diagram of a chip design and verification apparatus according to some embodiments of the present disclosure.

FIG. 10 is a block diagram of a computer system suitable for implementing the disclosed method.

Detailed Description

The technical solutions of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. In addition, technical features involved in different embodiments of the present disclosure described below may be combined with each other as long as they do not conflict with each other.

The register is a storage unit used for storing data in the chip to realize a specific function, with the continuous progress of the process, the design of the chip tends to be gradually complicated, and the number of registers required in the chip is more and more, for example, for some SoC chips, the number of registers can reach tens of thousands. Such a large number of registers can cause serious problems on the chip once the registers are faulty, and therefore, the registers need to be designed, verified and maintained in the chip development stage.

For a chip with a complex structure, the chip is often split from a top layer into a plurality of bottom functional modules, and different functional modules have different functions, such as a computing module and a recombination module. Different functional modules correspond to register modules required for realizing respective functions, and in the stage of chip design and verification, different functional modules are often required to be developed by different engineers. During the design and verification process of the chip, register information needs to be continuously modified to complete the design and verification, such as register addresses, initial values of domains, domain lengths, and the like. The corresponding design code and verification code need to be modified, which results in a large number of repetitive iterations.

In the related art, an engineer is required to manually perform iterative design and verification for register development, and corresponding code modification is directly performed in a design or verification environment, so careless mistakes are easily caused, the risk of chip errors is increased, a large amount of time is consumed for manual modification, and the register development period is prolonged. Moreover, since design and verification are usually performed by different engineers, the design code and the verification code have poor uniformity, which brings inconvenience to verification and maintenance work.

Based on the above-mentioned defects in the related art, the embodiments of the present disclosure provide a data processing method and apparatus, a chip design and verification method, an electronic device, and a storage medium, and aim to improve the development efficiency of a chip register.

In a first aspect, the disclosed embodiments provide a data processing method. As shown in fig. 1, in some embodiments, the data processing method of the present disclosure includes:

and S110, acquiring information texts corresponding to the register modules in the chip.

As mentioned above, different functional modules of a chip are generally designed by different departments or engineers, and for each register module, specific configuration parameter information of each register in the register module, such as name, offset address, type, read-write permission, signal name of each signal field, bit segment definition, default value, comment, etc. needs to be provided at the beginning stage of design or verification. The configuration parameter information corresponding to each register is the description information of the register.

In some embodiments, during the initial stage of design or verification, engineers of each register module may fill in the description information of the respectively responsible register module as an information text, so that the description information of all registers can be obtained by reading the content of the information text. Hereinafter, the detailed description will be omitted.

And S120, generating design codes and verification codes of the register modules according to the information texts.

Specifically, after the information text corresponding to each register module is obtained, the content of each information text, that is, the description information of each register recorded in the information text, can be identified and read, so as to automatically generate the design code and the verification code for each register module according to the specific description information.

It is to be understood that the design code described in the embodiments of the present disclosure refers to instantiation code based on a Register design language, for example, RTL (Register Transfer Level) design code based on Verilog language. Similarly, the verification code according to the embodiments of the present disclosure refers to a Register verification model-based verification code, such as a RAL (Register Abstraction Layer) verification code based on a UVM verification methodology.

In some embodiments, the description information of each information text may be read based on a computer executable program, and then the design code and the verification code of each register module may be generated according to the description information. The specific process is described in the following, and will not be detailed here.

Therefore, in the data processing method according to the embodiment of the present disclosure, the design code and the verification code are generated based on the information text, so that in the design and verification process of the chip register unit, when the register information is modified, the modified design and verification code can be generated only by modifying the description information of the corresponding information text, the code does not need to be modified manually and repeatedly, the risk of careless mistakes caused by manual work is reduced, the efficiency of chip design and verification is improved, and the development time is shortened. And moreover, the design and verification codes are simultaneously generated on the basis of the information text of the register module, so that the complete automatic flow of the design and verification stages is realized, and the codes of the two stages have uniform coding styles and are convenient to maintain.

In some embodiments, a flow of a data processing method according to embodiments of the present disclosure is shown in fig. 2, and is described below with reference to fig. 2.

As shown in fig. 2, in some embodiments, the data processing method of the present disclosure includes:

s210, obtaining the description text file and the configuration text file corresponding to each register module.

Specifically, in the beginning stage of design or verification, the engineer of each register module may fill out the information text of the register module in charge of each register module, and the information text includes two text files, namely, a description text file and a configuration text file.

The description text file is used for recording the description information of each register in the register module, such as the name, offset address, type, read-write permission, signal name of each signal field, bit segment definition, default value, comment and the like of each register.

In one example, the descriptive text file may be in the form of a Word document in which the relevant descriptive information is filled by the engineer.

The configuration text file is used for pointing to the corresponding description text file, and the configuration text file is used for recording the name of the corresponding description text file and the name of the corresponding register module. In some embodiments, the configuration text file may also record the name and contact address of the engineer. The information of the configuration text file may be displayed at a later stage in the header of the code file as an annotation of the code file, thereby facilitating viewing of the relevant information.

In one example, the configuration text file may be in the Txt format file, with the engineer filling in Txt files with relevant configuration information.

After the preparation work is completed, the data processing method of the embodiment of the present disclosure may be started to be executed, and the description text file and the configuration text file corresponding to each register module may be obtained by integrating all the description text files and configuration text files.

And S220, addressing according to the configuration text files to obtain the description text files.

As can be seen from the foregoing, the configuration text file is in one-to-one correspondence with the description text file, and is used to point to the description text file corresponding thereto. Therefore, the description text file corresponding to each register module can be obtained by addressing according to the content of each configuration text file.

In one example, the keyword information in each configuration text file can be identified by a script program, so that the description text file corresponding to each register module is obtained by addressing.

And S230, integrating to obtain a target information list based on the description information of each description text file.

Specifically, after obtaining each descriptive text file, the descriptive information recorded in each descriptive text file can be identified.

As can be known from the foregoing, the content recorded in each description text file is the specific configuration information, i.e., the description information, of each register in the register module. Therefore, all the description information can be integrated into a target information list by reading the description information content of all the description text files.

It is understood that the purpose of this step is to integrate the description information of all registers into information that can be recognized by the computer, i.e. the description information of all registers is included in the target information list.

And S240, generating a design code and a verification code based on the description information in the target information list.

Specifically, after obtaining the target information list, the computer runs a corresponding executable program to generate design code and verification code based on the description information in the target information list.

Therefore, according to the data processing method disclosed by the embodiment of the disclosure, the design codes and the verification codes of the register module can be automatically identified and generated only by inputting the written description text file and the configuration text file by the user, when the register information needs to be modified, the modified design codes and verification codes can be generated only by modifying the corresponding description text file, the codes do not need to be modified repeatedly, the risk of manual careless mistakes is reduced, meanwhile, the efficiency of chip design and verification is improved, and the research and development time is shortened. Moreover, the complete automatic flow of the design and verification stages is realized, and meanwhile, the configuration information of the two stages has a uniform coding style, so that the maintenance is convenient.

In some embodiments, in order to further improve the efficiency of developing the register, the user may not be required to complete the partial description information in the description text file. For example, offset addresses of registers in the same register module, for example, reserved bits in the register module, and repeated register information, etc. are manually filled by a user, which requires repeated work and takes time. Thus, in some embodiments of the present disclosure, such information may be filled in by a computer program, as described below in conjunction with fig. 3.

As shown in fig. 3, in some embodiments, the data processing method of the present disclosure includes:

and S310, integrating the description information of the description text files to obtain a first information list.

And S320, filling the description information in the first information list to obtain a target information list.

Specifically, after obtaining the description text file of each register module, the description information recorded in each description text file can be identified, so that all the description information can be integrated into a first information list by reading the description information content of all the description text files.

It should be noted that, because the description information in each description text file is missing, the integrated first information list is also a missing list, and the description information of the first information list needs to be filled and complemented, so that the computer generates the design and verification code based on the completed complete list information.

The process of populating the first list of information may include one or more of the following examples:

1) an offset address is calculated.

Each register needs to be assigned with an address, and when the number of registers included in the register module is large, it takes much time if the offset address of each register is manually filled by an engineer. Therefore, in the embodiment of the disclosure, in the preparation stage, the engineer only needs to fill in the first register address in the register module, and the offset addresses of the remaining registers may be omitted from not filling in.

In this case, in this embodiment, the computer program needs to sequentially calculate offset addresses of all registers in the register module according to the address and bit width parameter of the first register of the register module, and fill and complete the calculated offset addresses in the first information list.

2) The reserved bits are computed.

In the register unit of the chip, it is often necessary to set some units which do not store data, and these units are called reserved bits. Therefore, in this embodiment, the reserved bits in the register module can be calculated according to the related parameters, and the reserved bit parameters can be filled and completed in the first information list.

3) And searching for a repeated position.

When a plurality of registers with the same continuous description information exist in the register module, if the user repeatedly fills in the description information, a large amount of time is also occupied. Therefore, it is possible to fill in only the description information of the first register in the description text file and then set a repeat instruction. When the computer identifies the repeat instruction, the register description information of the repeat position can be filled and supplemented in the first information list according to the repeat instruction.

It is to be understood that the filling process for the first information list in the embodiment of the present disclosure is not limited to the above example, and a person skilled in the art may certainly implement other embodiments based on the above example, which is not described in detail herein.

Therefore, the data processing method of the embodiment of the disclosure can fill and complement the missing information based on the description information of each description text file, so that complete description information does not need to be filled in at an early stage, the time of preparation work is saved, the workload of engineers is reduced, and the research and development efficiency is improved.

In some embodiments, design and verification code is used for subsequent engineers while knowing global information. In the embodiment of the disclosure, when the design code and the verification code are generated based on the information text, a file after format conversion can be generated based on the original information text file, or an integrated top-level description file can be generated, so that an engineer can read related information to conveniently use the generated configuration information.

As shown in fig. 4, in an embodiment of the present disclosure, a data processing method includes:

s410, filling the information texts according to the description information corresponding to each information text to obtain first description files corresponding to each register module.

Specifically, in some embodiments, each information text filled by an engineer may be a text file with missing information, so that the information text is filled first, and the process of filling the description information is referred to in the foregoing description, which is not described in detail in this disclosure.

After the description information of each information text is filled and supplemented, each complete information text can be obtained, that is, the file format of the first description file corresponding to each register module is the same as that of the information text.

And S420, carrying out format conversion based on the first description file to obtain a second description file.

It will be appreciated that the purpose of format conversion is to convert the first description file into a file that is more readable to the user.

In some embodiments, the first description file is a Word document, i.e., a file in the. The second description file is an Excel file, i.e., a file in the format of. xls/. xlsx. It can be understood that, for the table-type information such as the description information, the information of the Excel file is more intuitive, and the Excel file is convenient for the user to look up and has higher readability.

In one example, the name of the sub-page (sheet) of the converted Excel file can be modified into the name of the register module, so that the converted second description file is more convenient to refer to.

And S430, integrating and processing the first description files to obtain the top layer description files of the register modules.

It should be noted that, in conjunction with the foregoing, the chip is split from the top layer into a plurality of bottom functional modules. In the embodiment of the disclosure, not only the description file of the register module corresponding to each functional module is generated, but also integration processing is performed based on each first description file to obtain a top-level description file. The top-level description file records global information of the whole register unit, so that an engineer can conveniently read global configuration information based on the top-level description file.

In one example, the top-level description file is an Excel file recorded with global information, i.e., a file in the format of. xls/. xlsx. The file comprises sub-pages (sheets) recorded with description information of each register module, and the name of each sub-page (sheet) can be modified to the name of the corresponding register module.

Therefore, the data processing method according to the embodiment of the disclosure generates the description file of each register module according to each information text, so that a user can conveniently refer to each register configuration information. And the description file comprises a second description file with better readability after format conversion, so that a user can know the configuration information more conveniently, and meanwhile, the description file also comprises a top-level description file of the global information, so that the user can read the global configuration information more conveniently based on the top-level description file, and the research and development efficiency is improved.

In some embodiments, when the disclosed data processing method generates the verification code according to the information text, in addition to generating the verification code corresponding to each register module, the top-level verification code of the whole register unit can also be generated. The top verification code represents the global verification code of the register unit, so that an engineer does not need to integrate the part of code independently, development time is saved, and verification efficiency is improved.

Fig. 5 to 6 show a specific embodiment of the data processing method of the present disclosure, and the flow and the principle of the data processing method of the present disclosure will be described in detail with reference to fig. 5 to 6.

In the embodiment shown in fig. 5, the flow of the data processing method of the present disclosure is explained from the following three stages:

(I) preparation phase

The chip is generally split into a plurality of functional modules from the top layer, and different engineers are responsible for the development of different functional modules. Therefore, each engineer can fill in the description information of each register in the register module corresponding to the functional module in charge of the engineer.

In this embodiment, each register module is recorded as a Word document in which an editable table in a fixed format is provided. In one example, the table style within the document of register module _ A may be as shown in "table one" as follows:

watch 1

In table one, the user needs to fill out the following contents:

(1) the name of the register. The name of the register is filled in, e.g. reg.

(2) offset. The offset address of the register in the register module _ a is filled, only the address of the first register can be filled, and the addresses of other registers can be omitted.

(3) type of the user. The register types are filled, for example, cfg (configuration register, software read-write, hardware read-only), cmd (start register, signal in pulse form, software write-only, hardware read-only), status (status register, software read-only, hardware write-only), mem (not supported), slave (extended cascade), and the like.

(4) And (4) spec. Indicating the register's characteristics, may be left unfilled, or filled in shadow (shadow register), repeat (register set, generated register name automatically added with an underlined suffix with a numeric ending).

(5) SW/HW. The read-write authority of the register is shown, and RO/WO/RW can be filled in.

(6) The name of the signal. The fields filling out the registers may be discrete bit segments, and the generated verification code automatically computes and completes the reserved bits. For example, the two signals given in Table one, will be automatically complemented to generate reserved _1[7:2], reserved _2[31:16 ].

After the completion of the filling, a description text file corresponding to the register module _ a can be obtained, which is a Word document. Meanwhile, each engineer is required to fill in a corresponding configuration text file, which is an Txt file, Txt file can specify the name of the corresponding word file and the name of the register module _ a, and also can fill in the name and contact information of the designer.

Summarizing the information texts of each engineer to obtain a description text file (Word document) and a configuration text file (Txt file) corresponding to each register module.

For example, as shown in fig. 6, module _ a.doc and module _ a.txt indicate that register module a corresponds to a description text file and a configuration text file, module _ b.doc and module _ b.txt indicate that register module B corresponds to a description text file and a configuration text file … …, and so on.

(II) File Generation phase

In this example, the scripting tool may be written in the python language or the executable file (. exe) may be packaged by python script. The script tool and the executable file are computer executable instructions, and when the computer executes the script, the data processing method described in any one of the above embodiments can be realized.

Exe indicates that the executable file is packaged by a python script, for example, as shown in fig. 6.

Specifically, when the script tool is operated by a computer, the Word document corresponding to each register module is obtained by addressing according to the configuration information of the Txt file. And then reading the register table information in each Word document, and integrating the description information of all registers into an information list which can be processed by a computer, namely a first information list. Then, the filling processing is performed on the missing information in the first information list, for example, calculating an offset address, calculating a reserved bit, searching for a duplicate position, and the like, which is referred to in the foregoing embodiments and is not described herein again. After filling processing is carried out on the missing information of the first information list, a complete target information list can be obtained. And finally, generating a configuration file and a description file based on the target information list.

Referring to fig. 5, in the present embodiment, after the script tool completes executing, 3 folders, named rtl, doc, and sv, are generated under the execution directory.

1) rtl folder.

The Verilog design codes of the register modules are generated under the folder, for example, module _ a _ csr _ slave.v and module _ a _ csr _ slave _ reg.v shown in fig. 6 represent the design codes corresponding to the register modules a, module _ B _ csr _ slave.v and module _ B _ csr _ slave _ reg.v represent the design codes … … corresponding to the register modules B, and so on.

In one example, the design code generated in the rtl folder is as follows:

2) sv folder

And generating a RAL model file based on a UVM verification methodology under the folder. In this embodiment, the sv folder includes the authentication codes of the respective register modules, for example, as shown in fig. 6, module _ a _ rgm.v denotes the authentication code of register module a, module _ B _ rgm.v denotes the authentication code … … of register module B, and so on.

It should be noted that, in the present embodiment, the sv folder not only generates the verification codes of the respective register modules, but also generates the top-level verification code of the whole register unit, i.e., top _ rgm.v shown in fig. 6, so that the verification engineer does not need to integrate the top-level verification code separately, thereby reducing the workload.

In one example, the verification code is represented in SystemVerilog language as follows:

3) doc folder

Under the folder, a new Word document, namely a first description file, is generated after the description information of the Word document of each register module is filled. The process of the filling process is described above, and is not described herein again.

In the example of fig. 6, module _ a.doc represents the first description file of register module a and module _ b.doc represents the first description file of register module B. . . . . . And so on.

Meanwhile, an Excel file with a converted format of the Word document of each register module is generated under the doc folder, namely a second description file corresponding to each register module. From the foregoing, the purpose of the first description file is to make the readability of the description information in the Word document higher.

In the example of fig. 6, module _ a.xlsx represents the second description file of register module a, module _ b.xlsx represents the second description file … … of register module B, and so on. The sheet name of each Excel may be modified to be the corresponding register module name, for example, the sheet name of the Excel corresponding to the register module a is modified to be module _ a.

In this embodiment, the table format in the generated Excel file can be shown in the following table two:

watch two

The meaning of each parameter in table two can be explained by referring to the table one, which is not repeated.

In this embodiment, as shown in fig. 6, a top-level description file of all register modules is generated under the doc folder, which is also an Excel file. The top-level description file can contain the description information of all register modules, wherein each sheet of the top-level description file correspondingly records the description information of one register module, and the name of each sheet can be modified into the name of the corresponding register module, so that an engineer can conveniently and quickly look up the information. For example, the sheet name of Excel corresponding to the register module a is modified to module _ a.

(III) design and verification stage

After the design code, the verification code and the description file are generated, engineers at various stages can use the generated code and file to realize the design and verification of the register unit.

The design engineer can use verilog design code under the rtl folder to integrate and instantiate the code in the design code at the top layer of the register unit, so as to realize instantiation of the register unit.

The verification engineer can instantiate the verification code under the sv folder into the verification environment, for example, the verification engineer can directly use various built-in register sequences carried by the UVM verification method to replace the manually built-up register test sequences.

In one example, uvm _ reg _ hw _ reset _ seq may check whether the register model reset value is consistent with the hardware reset value; uvm _ reg _ bit _ bash _ seq can write and read 1 and 0 to the bit supporting reading and writing; uvm _ reg _ access _ seq can be read back by the front gate writing register and the back gate, and then by the front gate writing and the front gate reading back, the numerical comparison is carried out.

In addition, the generated verification code is also internally provided with a function coverage rate, and the function coverage rate collection of the registers can be directly carried out, so that the verification requirement of a large number of registers in the project is met.

It can be understood that when some information of the register needs to be changed, only the relevant information in the originally filled description text file needs to be changed, the modified design code and the verification code can be generated by one key when the script is run, and meanwhile, the generated description file is automatically updated, so that the maintenance of the register unit is facilitated.

By the data processing method, when the register information is modified, the modified design and verification codes can be generated only by modifying the description information of the corresponding information text, manual repeated code modification is not needed, the risk of careless mistakes is reduced, the efficiency of chip design and verification is improved, and the research and development time is shortened. And moreover, the design and verification codes are simultaneously generated on the basis of the information text of the register module, so that the complete automatic flow of the design and verification stages is realized, and the codes of the two stages have uniform coding styles and are convenient to maintain. The missing information can be filled and supplemented based on the description information of each description text file, so that complete description information does not need to be filled in at the early stage, the time of preparation work is saved, the workload of engineers is reduced, and the research and development efficiency is improved. And generating a description file of each register module according to each information text, thereby facilitating a user to look up the configuration information of each register. The top-level description file and the top-level verification code of the global information are more convenient for a user to read the global configuration information based on the top-level description file, and meanwhile, the verification code of a base layer and a top layer is not needed independently, so that the research and development efficiency is improved.

In a second aspect, on the basis of the foregoing, embodiments of the present disclosure provide a chip design and verification method, which aims to improve the design and verification efficiency of a chip register unit and shorten a research and development cycle.

As shown in fig. 7, in some embodiments, a chip design and verification method according to embodiments of the present disclosure includes:

and S710, acquiring design codes and verification codes of all register modules of the chip.

S720, instantiating the chip according to the design code; and verifying the chip according to the verification code.

It can be understood that the design code and the verification code can be obtained according to the data processing method of any embodiment of the first aspect, and for the specific process of designing and verifying the chip, those skilled in the art can understand and fully implement the design code and the verification code with reference to the foregoing description, and will not be described herein again.

By the above, according to the chip design and verification method in the embodiment of the present disclosure, when the register information is modified, only the description information of the corresponding information text needs to be modified, so as to generate the modified design and verification codes, and the codes do not need to be modified manually and repeatedly, thereby reducing the risk of careless mistakes, improving the efficiency of chip design and verification, and shortening the research and development time. And moreover, the design and verification codes are simultaneously generated on the basis of the information text of the register module, so that the complete automatic flow of the design and verification stages is realized, and the codes of the two stages have uniform coding styles and are convenient to maintain.

In a third aspect, the disclosed embodiments provide a data processing apparatus. As shown in fig. 8, in some embodiments, the disclosed data processing apparatus includes:

a first obtaining module 810 configured to obtain information texts corresponding to the register modules in the chip; the information text records the description information of each register in the register module;

and a code generation module 820 configured to generate a design code and a verification code of each register module according to each of the information texts.

Therefore, the data processing device according to the embodiment of the disclosure generates the design code and the verification code based on the information text, so that in the design and verification process of the chip register unit, when the register information is modified, the modified design and verification code can be generated only by modifying the description information of the corresponding information text, the code is not required to be modified repeatedly, the risk of careless mistakes caused by manual work is reduced, meanwhile, the efficiency of chip design and verification is improved, and the development time is shortened. And moreover, the design and verification codes are simultaneously generated on the basis of the information text of the register module, so that the complete automatic flow of the design and verification stages is realized, and the codes of the two stages have uniform coding styles and are convenient to maintain.

In some embodiments, the first obtaining module 810 is specifically configured to:

In some embodiments, code generation module 820 is specifically configured to:

In some embodiments, the file generation module is specifically configured to:

In some embodiments, code generation module 820 is specifically configured to:

In a fourth aspect, the disclosed embodiments provide a chip design and verification apparatus. As shown in fig. 9, in some embodiments, the chip design and verification apparatus of the present disclosure includes:

a second obtaining module 910, configured to obtain the design code and the verification code of each register module of the chip; the design code and the verification code are obtained according to the data processing method of any one of the embodiments of the first aspect;

an instantiation module 920 configured to instantiate the chip according to the design code;

a verification module 930 configured to verify the chip according to the verification code.

By the above, when the register information is modified, the chip design and verification device according to the embodiment of the present disclosure can generate the modified design and verification codes only by modifying the description information of the corresponding information text, so that the codes do not need to be modified manually and repeatedly, the risk of careless mistakes is reduced, the efficiency of chip design and verification is improved, and the research and development time is shortened. And moreover, the design and verification codes are simultaneously generated on the basis of the information text of the register module, so that the complete automatic flow of the design and verification stages is realized, and the codes of the two stages have uniform coding styles and are convenient to maintain.

a processor; and

In particular, fig. 10 shows a schematic structural diagram of a computer system 600 suitable for implementing the method of the present disclosure, and the corresponding functions of the processor and the storage medium can be implemented by the system shown in fig. 10.

As shown in fig. 10, the computer system 600 includes a processor 601 that can perform various appropriate actions and processes according to a program stored in a memory 602 or a program loaded from a storage section 608 into the memory 602. In the memory 602, various programs and data required for the operation of the system 600 are also stored. The processor 601 and the memory 602 are connected to each other by a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, a mouse, and the like; an output portion 607 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The driver 610 is also connected to the I/O interface 605 as needed. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 610 as necessary, so that a computer program read out therefrom is mounted in the storage section 608 as necessary.

In particular, the above method processes may be implemented as a computer software program according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program comprising program code for performing the above-described method. In such embodiments, the computer program may be downloaded and installed from a network through the communication section 609, and/or installed from the removable medium 611.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

It should be understood that the above embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the present disclosure may be made without departing from the scope of the present disclosure.

Claims

1. A data processing method, comprising:

2. The method according to claim 1, wherein the obtaining of the information text corresponding to each register module in the chip comprises:

3. The method according to claim 2, wherein the integrating of the description information based on each of the description text files to obtain the target information list comprises:

4. The method of claim 1, further comprising:

5. The method according to claim 4, wherein generating a description file for each register module according to each information text comprises:

6. The method of claim 1, wherein generating an authentication code for each register module based on each of the message texts comprises:

7. A chip design and verification method is characterized by comprising the following steps:

acquiring design codes and verification codes of all register modules of a chip; the design code and the verification code are obtained according to the data processing method of any one of claims 1 to 6;

instantiating the chip according to the design code;

and verifying the chip according to the verification code.

8. A data processing apparatus, comprising:

9. The apparatus of claim 8, wherein the first obtaining module is configured to:

the code generation module is configured to:

10. The apparatus of claim 9, wherein the code generation module is configured to:

11. The apparatus of claim 8, further comprising:

12. The apparatus of claim 11, wherein the file generation module is configured to:

13. The apparatus of claim 8, wherein the code generation module is configured to:

14. A chip design and verification apparatus, comprising:

the second acquisition module is configured to acquire the design codes and the verification codes of the register modules of the chip; the design code and the verification code are obtained according to the data processing method of any one of claims 1 to 6;

15. An electronic device, comprising:

a processor; and

a memory storing computer instructions readable by the processor, the processor performing the method of any of claims 1 to 6 or performing the method of claim 7 when the computer instructions are read.

16. A storage medium storing computer readable instructions for causing a computer to perform the method of any one of claims 1 to 6 or to perform the method of claim 7.