WO2021031110A1 - Configuration file generation method and device, and storage medium - Google Patents

Abstract

A configuration file generation method and device, and a storage medium. The configuration file generation method comprises: acquiring a description file associated with a target chip (S100); and uniformly generating configuration files for a plurality of chip development modules according to the description file, the configuration file enabling the plurality of chip development modules to develop the target chip (S200). The method may improve the chip development efficiency.

Description

Configuration file generation method, device and storage medium Technical field

The present invention relates to the technical field of chip development, in particular to a method and device for generating configuration files, and a storage medium.

Background technique

Due to the rapid development of embedded application products, embedded chips such as DSP (digital signal processing) chips, ARM (Advanced RISC Machines, Advanced Reduced Instruction Set Processor) chips, SOC (system-on-chip), etc., are used in many different industries . For example, industries such as multimedia, wireless communications, network terminals, medical education, and even the latest artificial intelligence and deep learning. Faced with different application scenarios, it is necessary to design chips that meet different needs.

The development of the chip is usually realized by means of multiple development modules. Taking the DSP chip as an example, at least the software simulation module, the RTL code integration module and the EDA verification module are needed to implement software simulation, RTL code integration, EDA verification, etc., respectively.

In the development process, once the requirements change, the chip specifications need to be modified in time, and all development modules need to be modified consistently, which usually requires manual modifications one by one, resulting in low chip development efficiency.

Summary of the invention

The invention provides a configuration file generation method, device and storage medium, which can improve the efficiency of chip development.

The first aspect of the embodiments of the present invention provides a configuration file generation method, including:

Obtain description files related to the target chip;

According to the description file, a configuration file of multiple chip development modules is uniformly generated, and the configuration file is used to enable the multiple chip development modules to develop the target chip.

In a second aspect of the embodiments of the present invention, a configuration file generation device is provided, including: a processor and a memory;

The memory is used to store program code;

The processor is used to call the program code, and when the program code is executed, it is used to perform the following operations:

Obtain description files related to the target chip;

According to the description file, a configuration file of multiple chip development modules is uniformly generated, and the configuration file is used to enable the multiple chip development modules to develop the target chip.

A third aspect of the embodiments of the present invention provides a computer-readable storage medium,

The computer-readable storage medium stores computer instructions, and when the computer instructions are executed, the configuration file generation method described in the foregoing embodiment is implemented.

Based on the above technical solution, in the embodiment of the present invention, when developing the target chip, only the description file related to the target chip needs to be obtained, and the configuration files of multiple chip development modules can be uniformly generated according to the obtained description file. These chip development modules The target chip can be developed based on the configuration file. No matter how the requirements change during the development process, the configuration file that meets the demand can be quickly obtained, without the need to manually modify the configuration files of each chip development module, which improves the efficiency of chip development.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings needed in the embodiments of the present invention. Obviously, the drawings in the following description are only some implementations recorded in the present invention. For example, for those of ordinary skill in the art, other drawings can be obtained from these drawings of the embodiments of the present invention.

FIG. 1 is a schematic flowchart of a configuration file generation method according to an embodiment of the present invention;

Figure 2 is a schematic diagram of a DSP chip development process according to an embodiment of the present invention;

FIG. 3 is a schematic flowchart of step S200 in FIG. 1 according to an embodiment of the present invention;

4 is a schematic diagram of generating a configuration file by executing step S200 according to an embodiment of the present invention;

Figure 5 is a schematic diagram of a description file of an embodiment of the present invention;

Fig. 6 is a structural block diagram of an apparatus for generating a configuration file according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention. In addition, if there is no conflict, the following embodiments and the features in the embodiments can be combined with each other.

The terms used in the present invention are only for the purpose of describing specific embodiments, rather than limiting the present invention. The singular forms of "a", "said" and "the" used in the present invention and the claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should be understood that the term "and/or" as used herein refers to any or all possible combinations of one or more associated listed items.

Although the terms first, second, third, etc. may be used in the present invention to describe various information, the information should not be limited to these terms. These terms are used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information. Depending on the context, in addition, the word "if" used can be interpreted as "when", or "when", or "in response to certainty."

The configuration file generation method of the embodiment of the present invention will be described in detail below, but this should not be used as a limitation.

In an embodiment, referring to FIG. 1, a configuration file generation method may include the following steps:

S100: Obtain a description file related to the target chip;

S200: Generating configuration files of multiple chip development modules uniformly according to the description file, where the configuration files are used to enable the multiple chip development modules to develop the target chip.

The configuration file generation method of the embodiment of the present invention may be applied to an electronic device, and more specifically may be a processor of the electronic device. The electronic device may be, for example, a computer device. Of course, the specific type is not limited as long as it has a certain processing capability.

In step S100, a description file related to the target chip is obtained.

The description file related to the target chip can be preset locally, and only the description file needs to be read locally. Alternatively, the description file related to the target chip can also be obtained from an external device, or generated based on the input information of the developer. The specific method of obtaining the description file is not limited, as long as the description file related to the target chip can be obtained.

There can be one or more description files. When there is one description file, the target chip is completely described through the one description file. When there are multiple description files, the target chip is described cooperatively through the obtained description files.

The description file can specifically describe the configuration of the core in the target chip, the configuration of the components in the core, the composition of the components, and so on. As long as the overall configuration of the target chip can be clarified according to the obtained description file.

In step S200, a configuration file of multiple chip development modules is uniformly generated according to the description file, and the configuration file is used to enable the multiple chip development modules to develop the target chip.

The target chip can be any kind of digital circuit chip, and more specifically can be a processor chip such as a DSP chip, an ARM chip, or a SOC chip. Of course, the specific chip type is not limited, as long as it needs to go through multiple development processes, during which multiple chip development modules are used.

Taking a DSP chip as an example, referring to Figure 2, the development process of a DSP chip can include: a software simulation stage, an RTL top-level design stage, and a header file design stage.

In the software simulation stage, a software simulation module is needed, such as the simulator shown in Figure 2, or more specifically, a Cmodel. After the corresponding configuration file is applied to the software simulation module, a DSP chip software simulator can be simulated. Can carry on the function simulation of DSP chip.

In the RTL top-level design stage, RTL (Register Transfer Level) code integration module is needed, as shown in Figure 2, RTL Integrate, which can also be called RTL code integration module; and EDA verification module, as shown in Figure 2. EDA Verification issued.

Since the circuit structure of the chip is generally more complicated, the code corresponding to each functional module is written in hardware language. These codes are the configuration files of the RTL code integration module and the EDA verification module. The RTL integration of these codes on the RTL code integration module can present a complete circuit architecture of the chip. Applying these codes to the EDA verification module, a DSP chip hardware emulator can be simulated, on which the performance of the DSP chip can be simulated.

The header file design stage may include the ASM header file design stage, where the ASM Heaher file design shown in Figure 2 is performed; and the C header file design stage, the C Heaher file design shown in Figure 2 is performed. The ASM header file and the C header file are the header files required by each chip development module for users.

The files supported by different chip development modules may be different, such as content representation, file format, and file language. However, in the configuration files of each chip development module, the specific configuration content is basically the same.

Therefore, configuration files of multiple chip development modules can be uniformly generated according to the description file, and these chip development modules can develop the target chip based on the corresponding configuration files. The generation method of the configuration file may include: code conversion, code assembly, etc. The specific generation method is not limited, as long as the required configuration file can be obtained according to the description file.

Assuming that when developing a chip, the requirements are repeatedly changing. According to the existing method, after manually writing the configuration files of each chip development module, each time the requirements are changed, in order to ensure the consistency of the configuration of all chip development modules, manual labor is required. Modifying the configuration files of each chip development module one by one, the efficiency of the entire development process is too low.

In the embodiment of the present invention, when developing the target chip, only the description file related to the target chip needs to be obtained, and the configuration files of multiple chip development modules can be uniformly generated based on the obtained description files. These chip development modules can be based on the configuration files. To develop the target chip, no matter how the requirements change during the development process, the configuration file that meets the demand can be quickly obtained, without the need to manually modify the configuration files of each chip development module, which improves the efficiency of chip development.

In one embodiment,

A description file set can be preset locally, and there are multiple description files in the description file set. The description file set may include: at least one core description file, each core description file containing component information in a single core; and multiple component description files, each component description file containing composition information of a single component.

Among them, the component information in each core description file may include the configuration information, component identification and connection relationship of each component; the composition information in each component description file may include the configuration information of each component and the connection relationship of each component . Of course, this is only an example of the information contained in these description files, not as a limitation.

Optionally, obtaining a description file related to the target chip may specifically include the following steps:

Obtain the externally input chip description file of the target chip, the chip description file at least contains the core identification of each core in the target chip;

According to the core identification in the chip description file, select the core description file corresponding to each core identification from the description file set;

According to the component identification in each selected core description file, select the component description file corresponding to each component identification from the description file set;

The obtained chip description file and the selected core description file and component description file are used as description files related to the target chip.

The above method of obtaining the description file is just an example. Of course, there are other methods. For example, when selecting the core description file and the component description file from the description file set, the selection can be made under the instruction of an external input instruction.

In an embodiment, referring to FIG. 3, in step S200, generating configuration files of multiple chip development modules according to the description file may include the following steps:

S201: Generate a specification description file of the target chip according to the description file;

S202: uniformly determine configuration files of multiple chip development modules of the target chip according to the specification description file.

A specification description file can be generated based on the obtained description file, and the specification description file can be used to describe the specifications of the target chip. Taking the target chip as DSP as an example, the specification description file is obtained by loading and parsing the description file. It can be used as a complete DSP model (preferably the dsp.hsd file) to realize the overall configuration of the DSP chip development module.

Specifically, the obtained description file format may all be an xml format file. A program that supports xml format files and can implement step S200 can be pre-written. For example, the program that implements step S200 is a configurator through the python language. Calling the configurator can complete the loading and parsing of the xml format file, as well as the parsed The information in the xml format file is used to generate the specification description file.

In the case of determining the specification description file, the configuration files of multiple chip development modules of the target chip can be determined according to the specification description file. The information content related to the specifications in each configuration file is derived from the specification description file. The content is basically the same.

The acquired description files can be multiple description files, and different specification description files can be generated by replacing at least one of the description files. Therefore, in the development process, when the requirements change, a description file that matches the requirement can be found, and the corresponding specification description file can be generated. According to the specification description file, the configuration file that meets the requirement can be determined.

Therefore, the embodiment of the present invention can support the configuration of chips of different specifications, and is more versatile.

In one embodiment, the description file includes:

A chip description file of the target chip, where the chip description file contains core information in the target chip;

The core description file of each core in the target chip, and each core description file contains the component information in the corresponding core;

And, the component description file of each component in each core in the target chip, and each component description file contains the composition information of the corresponding component.

The chip description file, core description file, and component description file of the target chip can form a certain hierarchical structure. For example, the chip description file is the first-level file, which contains the core information required by the target chip. The core information can include core identification, etc.; the core description file is the second-level file, and each core description file corresponds to a core identification. , Contains the component information of the components required by the corresponding core. The component information can include component identification, component name, connection relationship between components, external connection relationship between components, etc.; the component description file is a third-level file, and each component description file They all correspond to a component identifier and contain the composition information of the component parts required by the corresponding component. The composition information may include the component component name, the connection relationship of the component component, and the external connection relationship of the component component.

Of course, the chip description file, core description file, and component description file may also contain other information. For example, the chip description file may also include the size of DDR (Double Rate Synchronous Dynamic Random Access Memory). DDR can be used as an external storage unit to store data and instructions during software simulation.

Optionally, the file format of each file adopts xml (extensible markup language) format, that is, the file is written in xml language. Of course, it is not limited to this, and the file can also be written in other scripting languages.

Further, the program that implements the method of the embodiment of the present invention can be written in the python language, so that the portability of the program can be guaranteed. For example, the program that implements step S200 is called a configurator, and the configurator can be written in python language. Of course, the program for implementing the method of the embodiment of the present invention can also be written in other languages.

Taking the target chip as a DSP chip as an example, combining Figure 1 and Figure 4, input dsp.xml, cell0.xml, cell1.xml, Component_0.xml, Component_1.xml, Component_2.xml, and Component_3.xml into the configurator Then, the Dsp_0.hsd required by the simulator software simulation, the Dsp_0_top.v and the Asm header file required for the synthesis of the EDA Verification hardware simulation and RTL Integrate code can be generated uniformly asm_header.h, the header files required for the EDA Verification simulation. The header file crf_lst.vh, and the header file c_headers.h required for C header file design.

Among them, continue to refer to Figure 4, dsp.xml is the chip description file, dsp.xml contains the core information of the cell0 and cell1 cores, indicating that the DSP chip needs two cores, so the description file input to the configurator is also Including cell0.xml and cell1.xml. Cell0.xml contains the component information of Component_0 and Component_1, indicating that these two components are required in core cell0. Therefore, the description file input to the configurator also includes Component_0.xml and Component_1.xml. Cell1.xml contains the component information of Component_2 and Component_3, indicating that these two components are required in core cell1. Therefore, the description file input to the configurator also includes Component_2.xml and Component_3.xml.

Of course, the specific components included in each core are not limited. For example, each core includes at least one of the following components: a control unit, a vector execution unit (for performing vector operations), a storage unit, a data transmission bus, and an accelerator.

Each component can be configured with corresponding components as needed. Taking the control unit as an example, the component can be configured with data interface, control register group, control register, bit field of the component register, external interface, and Storage sub-units, etc.

More specifically, referring to Figure 5, dsp.xml is the chip description file, as the first level file, which contains the core information of the two cores cell0 and cell1, corresponding to the two core description files, cell0.xml and cell1. xml; cell0.xml and cell1.xml, as the second-level files, contain the component information of each component. Taking cell0.xml as an example, it can include a simplified instruction set processor risc, a storage unit vmem, and vectors for performing multiplication and addition Component information of the execution unit veu, the vector execution unit valu for performing shift operations, and the vector execution unit vfpu for performing floating-point operations; Figure 5 only shows the third-level file corresponding to cell0.xml, including risc. xml, vmem.xml, veu.xml, valu.xml, vfpu.xml are used to describe the composition information of risc, vmem, veu, valu, and vfpu, respectively.

It can be understood that the specific content of the above description file is merely an example for ease of understanding and should not be taken as a limitation.

In one embodiment, in step S201, generating the specification description file of the target chip according to the description file includes:

S2011: Generate a core assembly file according to at least one of the core description files and corresponding component description files;

S2012: Generate the specification description file according to the chip description file and each core assembly file.

In this embodiment, the core description file in the description file and the corresponding component description file can be assembled first to generate a core assembly file corresponding to each core description file; then the chip description file and each core assembly file are assembled, To generate the specification description file of the target chip.

Refer to Figure 5, first assemble risc.xml, vmem.xml, veu.xml, valu.xml, and vfpu.xml into cell0.xml. The same is true for cell1.xml, and then the assembled cell0.xml and cell1.xml Assemble into dsp.xml to obtain a specification description file containing complete specification information of the target chip.

Of course, this embodiment is only an example of generating a specification description file, and of course, there may be other ways in practice. For example, first assemble the chip description file and the core description file to obtain the chip assembly file, and then assemble the component description file corresponding to each core description file to the corresponding position of the chip assembly file to obtain the specification description file.

In one embodiment,

Each core description file includes the corresponding core identification;

In step S2011, generating a core assembly file according to at least one of the core description file and the corresponding component description file includes:

S20111: According to the core identification corresponding to each core description file, check whether the core assembly file corresponding to the core identification currently exists;

S20112: If not, obtain the component description file corresponding to the core description file from all component description files, and generate the core assembly file of the core description file according to the obtained component description file and the core description file.

The core description file of each core has the core identification of the core (the core identification can be used as the name of the core description file, and/or recorded in the core description file), in other words, each core description file includes the corresponding core identification. The core assembly file is based on the core description file and the corresponding component description file, so the core assembly file will also contain the core identification in the core description file, that is, the core assembly file also corresponds to the core identification.

It is possible to check whether a core assembly file corresponding to the core identification currently exists for the core identification contained in each core description file. It can be pre-configured with storage space for storing nuclear assembly files, and each time a nuclear assembly file is generated, it is stored in the storage space. In this way, when subsequent assembly is required, the storage space can be used to find whether there is a required nuclear assembly file.

If the nuclear assembly file corresponding to the nuclear identification does not currently exist, it means that the nuclear assembly file corresponding to the nuclear identification has not been assembled before, and the nuclear assembly file corresponding to the nuclear identification needs to be newly generated. Since all component description files are the component description files of the components contained in all cores, it is necessary to obtain the component description file corresponding to the core description file from all the component description files, and then generate the core according to the obtained component description file and the core description file. The nuclear assembly file describing the file.

In one embodiment, the method further includes:

S20113: If the core assembly file corresponding to the core identifier currently exists, determine the core assembly file as the core assembly file of the core description file.

If the nuclear assembly file corresponding to the nuclear identification currently exists, it means that the nuclear assembly file corresponding to the nuclear identification has been assembled before and can be used directly without regenerating it. In other words, if the core assembly file corresponding to the core identifier is found in the storage space, then the found assembly file is determined as the core assembly file of the core description file.

In this embodiment, when a nuclear assembly file is needed, you can first check whether the required nuclear assembly file already exists. If it exists, it can be obtained directly, and if it does not exist, it can be generated again, which can save the processing time of regenerating the nuclear assembly file. , Speed up the processing speed, improve the efficiency of generating specification description files.

In one embodiment,

The component information includes at least a component identification;

In step S20112, obtain component description files required by the core description file from all component description files, including:

S201121: According to the component identifier in the core description file, obtain the component description file corresponding to the core description file from all the component description files.

The component information in the core description file may include the component identification. Of course, the component information may also include other information.

A core description file can contain multiple component information, that is, multiple component identifiers. According to the component identifiers in the core description file, the component description file corresponding to the core description file can be found from the component description file.

An association relationship can be established between the component identifier of a component and the component description file, and thus the component description file that has an association relationship with the component identifier can be found according to the component identifier. In this way, all component description files corresponding to the core description file can be found.

For example, the component identifiers contained in the core description file cell0.xml are risc, vmem, veu, valu, and vfpu. Then, according to these component identifiers, risc.xml, vmem.xml, veu.xml, valu.xml, vfpu can be found .xml these component description files.

In this embodiment, the required component description file is obtained according to the component identification, and the obtaining method is simpler and faster.

In one embodiment,

Each component description file includes the corresponding component identification;

Step S201121: According to the component identification in the core description file, obtain the component description file corresponding to the core description file from all the component description files, including:

According to each component identifier in the core description file, the component description file corresponding to the component identifier is selected from all component description files, and the selected component description file is determined as the component description file corresponding to the core description file.

The component description file of each component has the component identification of the component (the component identification can be used as the name of the component description file, and/or recorded in the component description file), in other words, each component description file includes the corresponding component identification.

In this way, the component description file can be obtained more conveniently based on the component identification. As long as for each component identifier in the core description file, find the component description file containing the component identifier, and the found component description file is the component description file corresponding to the core description file.

In one embodiment,

The component information includes at least a component identification;

Each component description file includes the corresponding component identification;

In step S20112, generating a core assembly file of the core description file according to the obtained component description file and the core description file, including:

S201122: Determine the component description file corresponding to each component identifier according to the component identifier in the core description file;

S201123: Assemble the component description file corresponding to each component identifier into the core description file to obtain the core assembly file of the core description file.

The component description file of each component has the component identification of the component (the component identification can be used as the name of the component description file, and/or recorded in the component description file), in other words, each component description file includes the corresponding component identification.

The component information in the core description file may include the component identification. Of course, the component information may also include other information.

A core description file can contain multiple component information, that is, multiple component identifiers. According to the component identifiers in the core description file, the component description file corresponding to each component identifier can be determined; the component description file corresponding to each component identifier is assembled into the core description file to obtain the core assembly file of the core description file.

For example, the component identifiers contained in cell0.xml are risc, vmem, veu, valu, vfpu, then risc.xml, vmem.xml, veu.xml, valu.xml, vfpu.xml can be assembled according to these component identifiers To cell0.xml, risc.xml can be assembled to the position corresponding to the component identifier risc in cell0.xml, vmem.xml can be assembled to the position corresponding to the component identifier vmem in cell0.xml, and veu.xml can be assembled to cell0.xml The position corresponding to the middle component identifier veu, and so on, the similarities are not repeated here.

In this way, the assembly of the core description file and the corresponding component description file can be completed, and the core assembly file corresponding to each core description file can be obtained. The core assembly file is a file that completes the component information of each component in the core.

In one embodiment, in step S201123, assembling the component description file corresponding to each component identifier into the core description file may include the following two methods:

A1: Replace the component information where each component identifier is located in the core description file with the content in the component description file corresponding to each component identifier;

A2: Insert all the component information in the component description file corresponding to each component identifier into the component information where each component identifier in the core description file is located.

In method A1, the component information in the core description file does not need to be retained, but replaced with the content in the component description file corresponding to each component identifier, and the obtained core assembly file contains the content in the component description file corresponding to each component identifier. Of course, the core identification and other necessary information in the core description file have not been replaced.

In this method, the component information in the core description file can be information used to help developers understand the component overview, but it is not the information required by the final specification description file, so it is sufficient to use alternative means.

For example, the component identifiers contained in cell0.xml are risc, vmem, veu, valu, vfpu. Taking risc as an example, the component information where risc is located in cell0.xml is a code fragment, which can be used as risc as a whole. Replace the code in xml, so that the core assembly file corresponding to cell0.xml integrates the code in risc.xml, vmem.xml, veu.xml, valu.xml, and vfpu.xml.

In method A2, the component information in the core description file still needs to be retained. All the component information in the component description file corresponding to each component identifier is inserted into the component information where each component identifier in the core description file is located. The component description file It may also contain other information such as component identification, but because the component identification already exists in the core description file, this part of the repeated information does not need to be inserted into the core description file.

In this method, the component information in the core description file can not only help the developer understand the component overview, but also the information required by the final specification description file, so the insertion method is used.

For example, the component identifiers contained in cell0.xml are risc, vmem, veu, valu, vfpu. Taking risc as an example, the component information where risc is located in cell0.xml is a code fragment, and the composition information in risc.xml can be Multiple code snippets, the multiple code snippets in risc.xml can be inserted into the code snippet where risc is located. The specific insertion position can be marked in the core description file, so that the core assembly file corresponding to cell0.xml is not only integrated The codes in risc.xml, vmem.xml, veu.xml, valu.xml, and vfpu.xml also retain the original component information of cell0.xml.

Of course, the above two methods are only preferred methods for assembling the component description file to the core description file, but should not be used as a limitation, and other methods that can be assembled are also applicable.

In one embodiment,

The nuclear information includes at least a nuclear identifier;

Each core assembly file includes the corresponding core identification;

In step S2012, generating the specification description file according to the chip description file and each core assembly file includes:

S20121: Determine the core assembly file corresponding to each core identification according to the core identification in the chip description file;

S20122: Assemble the core assembly file corresponding to each core identifier into the chip description file to obtain the specification description file.

The core information in the chip description file may include the core identification, of course, the core information may also include other information. For example, the chip description file may contain two core identifiers, cell0 and cell1, which respectively indicate the corresponding cores.

The core description file of each core has the core identification of the core (the core identification can be used as the name of the core description file, and/or recorded in the core description file), in other words, each core description file includes the corresponding core identification. The core assembly file is based on the core description file and the corresponding component description file, so the core assembly file will also contain the core identification in the core description file, that is, the core assembly file also corresponds to the core identification.

A chip description file contains at least one core information, that is, at least one core identifier. According to the core identification in the chip description file, the core assembly file corresponding to each core identification can be determined; the core assembly file corresponding to each core identification is assembled into the chip description file to obtain the specification description file.

If the chip description file contains only one core identification, it means that the target chip to be developed is a single-core chip; if the chip description file contains two core identifications, it means that the target chip to be developed is a dual-core chip, and so on.

For example, the core identifiers contained in dsp.xml are cell0 and cell1, then the core assembly files corresponding to cell0.xml and cell1.xml can be assembled into dsp.xml based on these core identifiers, and cell0.xml can be assembled into the core identification At the location corresponding to cell0, cell1.xml can be assembled to the location corresponding to the core identifier cell1.

In this way, the assembly of the chip description file and the corresponding core assembly file can be completed to obtain the specification description file. The specification description file is a file that completes all the composition information of all components in all cores in the target chip.

In one embodiment,

In step S20122, assembling the core assembly file corresponding to each core identifier into the chip description file may include the following two methods:

B1: Replace the core information where each core identifier is located in the chip description file with the content in the core assembly file corresponding to each core identifier;

B2: Insert all component information in the core assembly file corresponding to each core identifier into the core information where each core identifier is located in the chip description file.

In method B1, the core information in the chip description file does not need to be retained, but is replaced with the content in the core assembly file corresponding to each core identifier, and the obtained specification description file contains the content in the core assembly file corresponding to each core identifier. Of course, the nuclear identification and other necessary information in the nuclear assembly file have not been replaced.

In this method, the core information in the chip description file can be information used to help developers understand the component overview, but it is not the information required by the final specification description file, so only replacement means can be used.

For example, dsp.xml contains the core identifiers cell0 and cell1. Taking cell0 as an example, the core information of cell0 in dsp.xml is a code fragment, which can be used in the core assembly file corresponding to cell0.xml. The code in cell0.xml and cell1.xml are integrated in the resulting specification description file.

In method B2, the core information in the chip description file still needs to be retained. All the component information in the core assembly file corresponding to each core identification is inserted into the core information where each core identification in the chip description file is located. It may contain other information such as core identification, but since the core identification already exists in the chip description file, this part of the repeated information does not need to be inserted into the chip description file.

In this method, the core information in the chip description file can not only help developers understand the core overview, but also the information required by the final specification description file, so the insertion method is used.

For example, dsp.xml contains core identifiers cell0 and cell1. Taking cell0 as an example, the core information of cell0 in dsp.xml is a code fragment, and the component information in the core assembly file corresponding to cell0.xml can be multiple Code snippets, these multiple code snippets can be inserted into the code snippet where cell0 is located. The specific insertion position can be marked in the chip description file, so that the specification description file not only integrates the codes in all core assembly files, but also retains the dsp .xml original nuclear information, DDR size, etc.

Of course, the above two methods are only preferred methods for assembling the core assembly file into the chip description file, but should not be used as a limitation, and other methods that can be assembled are also applicable.

In one embodiment, the target chip is a DSP chip.

In the embodiment of the present invention, the configuration files required by multiple chip development modules of the DSP chip in the development phase can be generated, so that when the specifications of the DSP chip to be developed need to be modified, only the description file needs to be modified to obtain a new description File, based on the new description file, you can get the configuration files of multiple chip development modules. These configuration files can meet the needs. There is no need to modify the configuration files of multiple chip development modules one by one, which improves the development efficiency of DSP chips. .

Of course, the target chip in the embodiment of the present invention can also be other types of chips, such as ARM chips, SOC chips, etc., as long as it will go through multiple chip development modules during the development phase and these chip development modules are required The corresponding configuration file is fine.

In an embodiment, the multiple chip development modules at least include: a software simulation module, an RTL code integration module, and an EDA verification module;

In step S202, uniformly determining the configuration files of multiple chip development modules of the target chip according to the specification description file includes:

S2021: Determine the software configuration file required by the software simulation module according to the specification description file;

S2022: Determine the RTL top-level code file required by the RTL code integration module and the EDA verification module according to the specification description file.

The software simulation module can be used to realize the functional simulation of the DSP chip. The RTL code integration module can be used to implement RTL code integration, and the EDA verification module can be used to implement performance simulation of DSP chips.

Due to different modules, the required configuration files will be different. Specifically, the software configuration file required by the software simulation module, the RTL top-level code file required by the RTL code integration module and the EDA verification module are different. The difference is mainly reflected in the different programming languages.

The software configuration file is written in a software programming language, and the specific language can be determined according to the language supported by the software simulation module. The RTL top-level code files are written in hardware programming languages, such as Verilog, VHDL, etc. Of course, in the case of different languages, the code format will be different.

The information content related to the specification in the specification description file is also required by the software configuration file and the RTL top-level code file. Therefore, the software configuration file required by the software simulation module and the RTL top-level code file required by the RTL code integration module and the EDA verification module can be determined according to the specification description file.

The main difference between the specification description file, the software configuration file and the RTL top-level code file also lies in the programming language. The specification description file can be written in XML format, and the specific writing language is not limited.

Of course, if the writing language of the specification description file and the software configuration file are the same, the specification description file can be directly determined as the software configuration file. RTL top-level code files are similar.

In one embodiment, in step S2021, determining the software configuration file required by the software simulation module according to the specification description file includes:

S20211: Convert the specification description file to generate the software configuration file, so that the software configuration file can be applied to the software simulation module.

Specifically, converting the specification description file to generate the software configuration file may include the following two methods:

C1: Prepare a template of the software configuration file in advance. The template is complete except for the value of the required key information; find the value of the key information required by the template from the specification description file, and find the value Write it into the corresponding key information of the template to obtain the required software configuration file.

C2: The language conversion relationship between the specification description file and the code with the same meaning in the software configuration file can be established. In this way, the code in the specification description file can be converted from the current language to the software configuration file according to the language conversion relationship. Language, get the software configuration file.

Of course, the above two methods are just examples for ease of understanding and should not be used as a limitation. Of course, there may be other methods to determine the required configuration file, for example, the above two methods can also be combined.

It can be understood that the method for determining the RTL top-level code file according to the specification description file may also adopt the above method, and the similarities are not repeated here.

In one embodiment, in step S202, uniformly determining the configuration files of multiple chip development modules of the target chip according to the specification description file, further including the following steps:

S2023: Extract user-oriented configuration information from the specification description file;

S2024: Generate the first header file required by the software simulation module, the RTL code integration module, and the EDA verification module according to the extracted configuration information.

The specification description file can contain a variety of configuration information, some of which need to be user-oriented, such as control register related information (such as address), etc., which need to be used to generate software simulation modules, RTL code integration modules and EDA verification The first header file used by users in modules, etc.

Therefore, the user-oriented configuration information can be extracted from the specification description file, such as extracting all the relevant information of the control register. Of course, the user-oriented configuration information is not limited to the register address, and can be determined according to needs. .

After extracting the user-oriented configuration information, the first header files required by the software simulation module, the RTL code integration module and the EDA verification module can be generated based on the configuration information. The header file template can be prepared in advance, and the configuration information can be filled in the corresponding position in the template to generate the corresponding header file.

In an embodiment, the first header file includes: a C language header file and an ASM header file.

The first header file required by the DSP chip in the development stage may include a C language header file and an ASM header file. C language header files and ASM header files can include DSP control registers, interrupt macro definitions, etc.

Of course, the first header file is not limited to this. As the development platform and DSP chip technology evolve, the required first header file may also change accordingly, such as a header file written in another language.

In one embodiment,

In step S202, uniformly determining the configuration files of multiple chip development modules of the target chip according to the specification description file, and further includes the following steps:

S2025: Extract the register address used for EDA verification from the specification description file;

S2026: Generate a second header file required by the EDA verification module according to the extracted register address.

Since the EDA verification module needs to rely on some registers (such as used to store data, instructions, etc.) when verifying, it is necessary to extract the register address required for EDA verification, and generate the EDA verification module required by the extracted register address The second header file.

The method of generating the second header file based on the register address is similar to the method of generating the first header file based on the configuration information, and will not be repeated here.

The above is the relevant description content of the configuration file generation method in the embodiment of the present invention. Based on the above content, the efficiency of chip development can be improved.

Based on the same inventive concept as the above method, the present invention also provides a configuration file generating device. Referring to FIG. 6, the configuration file generating device 100 may include a processor 102 and a memory 101.

In one embodiment, the memory is used to store program code;

The processor is used to call the program code, and when the program code is executed, it is used to perform the following operations:

Obtain description files related to the target chip;

According to the description file, a configuration file of multiple chip development modules is uniformly generated, and the configuration file is used to enable the multiple chip development modules to develop the target chip.

In one embodiment,

When the processor uniformly generates configuration files of multiple chip development modules according to the description file, it is specifically used for:

Generating a specification description file of the target chip according to the description file;

The configuration files of multiple chip development modules of the target chip are uniformly determined according to the specification description file.

In one embodiment, the description file includes:

A chip description file of the target chip, where the chip description file contains core information in the target chip;

The core description file of each core in the target chip, and each core description file contains the component information in the corresponding core;

And, the component description file of each component in each core in the target chip, and each component description file contains the composition information of the corresponding component.

In an embodiment, when the processor generates the specification description file of the target chip according to the description file, it is specifically used for:

Generating a core assembly file according to at least one of the core description files and corresponding component description files;

The specification description file is generated according to the chip description file and each core assembly file.

In one embodiment,

Each core description file includes the corresponding core identification;

When the processor generates a core assembly file according to at least one of the core description file and the corresponding component description file, it is specifically configured to:

According to the core identification corresponding to each core description file, check whether the core assembly file corresponding to the core identification currently exists;

If not, obtain the component description file corresponding to the core description file from all component description files, and generate the core assembly file of the core description file according to the obtained component description file and the core description file.

In an embodiment, the processor is further configured to:

If the core assembly file corresponding to the core identifier currently exists, the core assembly file is determined as the core assembly file of the core description file.

In one embodiment,

The component information includes at least a component identification;

When the processor obtains the component description file required by the core description file from all component description files, it is specifically used for:

According to the component identification in the core description file, the component description file corresponding to the core description file is obtained from all the component description files.

In one embodiment,

Each component description file includes the corresponding component identification;

When the processor obtains the component description file corresponding to the core description file from all the component description files according to the component identifier in the core description file, it is specifically used for:

According to each component identifier in the core description file, the component description file corresponding to the component identifier is selected from all component description files, and the selected component description file is determined as the component description file corresponding to the core description file.

In one embodiment,

The component information includes at least a component identification;

Each component description file includes the corresponding component identification;

When the processor generates the core assembly file of the core description file according to the obtained component description file and the core description file, it is specifically used for:

Determine the component description file corresponding to each component identifier according to the component identifier in the core description file;

The component description file corresponding to each component identifier is assembled into the core description file to obtain the core assembly file of the core description file.

In one embodiment,

When the processor assembles the component description file corresponding to each component identifier into the core description file, it is specifically used for:

Replacing the component information where each component identifier is located in the core description file with the content in the component description file corresponding to each component identifier;

or,

All the component information in the component description file corresponding to each component identifier is inserted into the component information where each component identifier in the core description file is located.

In one embodiment,

The nuclear information includes at least a nuclear identifier;

Each core assembly file includes the corresponding core identification;

When the processor generates the specification description file according to the chip description file and each core assembly file, it is specifically used for:

Determining the core assembly file corresponding to each core identification according to the core identification in the chip description file;

The core assembly file corresponding to each core identifier is assembled into the chip description file to obtain the specification description file.

In one embodiment,

When the processor assembles the core assembly file corresponding to each core identifier into the chip description file, it is specifically used to:

Replacing the core information where each core identifier is located in the chip description file with the content in the core assembly file corresponding to each core identifier;

or,

Insert all component information in the core assembly file corresponding to each core identifier into the core information where each core identifier is located in the chip description file.

In one embodiment,

The target chip is a DSP chip.

In one embodiment,

The multiple chip development modules include at least: a software simulation module, an RTL code integration module, and an EDA verification module;

When the processor uniformly determines the configuration files of multiple chip development modules of the target chip according to the specification description file, it is specifically used for:

Determine the software configuration file required by the software simulation module according to the specification description file;

Determine the RTL top-level code file required by the RTL code integration module and the EDA verification module according to the specification description file.

In one embodiment, when the processor determines the software configuration file required by the software simulation module according to the specification description file, it is specifically used to:

The specification description file is converted to generate the software configuration file, so that the software configuration file can be applied to the software simulation module.

In one embodiment,

When the processor uniformly determines the configuration files of multiple chip development modules of the target chip according to the specification description file, it is further configured to:

Extract user-oriented configuration information from the specification description file;

According to the extracted configuration information, the first header files required by the software simulation module, the RTL code integration module and the EDA verification module are generated.

In one embodiment,

The first header file includes: C language header file and ASM header file.

In one embodiment,

When the processor uniformly determines the configuration files of multiple chip development modules of the target chip according to the specification description file, it is further configured to:

Extract the register address used for EDA verification from the specification description file;

Generate the second header file required by the EDA verification module according to the extracted register address.

Based on the same inventive concept as the above method, the present invention also provides a computer-readable storage medium having computer instructions stored thereon, and when the computer instructions are executed, the configuration described in the foregoing embodiment is realized File generation method.

The systems, devices, modules or units explained in the above embodiments may be implemented by computer chips or entities, or implemented by products with certain functions. A typical implementation device is a computer. The specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.

For the convenience of description, when describing the above device, the functions are divided into various units and described separately. Of course, when implementing the present invention, the functions of each unit can be implemented in the same one or more software and/or hardware.

Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may adopt the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

The present invention is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing equipment are generated It is a device that realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

Moreover, these computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device, The instruction device realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be loaded into a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, thereby executing instructions on the computer or other programmable equipment Provides steps for realizing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

The above descriptions are only embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (37)

1. A method for generating a configuration file is characterized in that it comprises:

   Obtain description files related to the target chip;

   According to the description file, a configuration file of multiple chip development modules is uniformly generated, and the configuration file is used to enable the multiple chip development modules to develop the target chip.
2. The method for generating a configuration file according to claim 1, wherein:

   According to the description file, the configuration files of multiple chip development modules are uniformly generated, including:

   Generating a specification description file of the target chip according to the description file;

   The configuration files of multiple chip development modules of the target chip are uniformly determined according to the specification description file.
3. The configuration file generating method according to claim 2, wherein the description file comprises:

   A chip description file of the target chip, where the chip description file contains core information in the target chip;

   The core description file of each core in the target chip, and each core description file contains the component information in the corresponding core;

   And, the component description file of each component in each core in the target chip, and each component description file contains the composition information of the corresponding component.
4. 5. The configuration file generation method of claim 3, wherein generating the specification description file of the target chip according to the description file comprises:

   Generating a core assembly file according to at least one of the core description files and corresponding component description files;

   The specification description file is generated according to the chip description file and each core assembly file.
5. The method for generating a configuration file according to claim 4, wherein:

   Each core description file includes the corresponding core identification;

   Generating a core assembly file according to at least one of the core description file and the corresponding component description file includes:

   According to the core identification corresponding to each core description file, check whether the core assembly file corresponding to the core identification currently exists;

   If not, obtain the component description file corresponding to the core description file from all component description files, and generate the core assembly file of the core description file according to the obtained component description file and the core description file.
6. 8. The configuration file generation method of claim 5, wherein the method further comprises:

   If the core assembly file corresponding to the core identifier currently exists, the core assembly file is determined as the core assembly file of the core description file.
7. The method for generating configuration files according to claim 5, wherein:

   The component information includes at least a component identification;

   Obtain the component description files required by the core description file from all component description files, including:

   According to the component identification in the core description file, the component description file corresponding to the core description file is obtained from all the component description files.
8. The method for generating a configuration file according to claim 7, wherein:

   Each component description file includes the corresponding component identification;

   According to the component identification in the core description file, obtain the component description file corresponding to the core description file from all the component description files, including:

   According to each component identifier in the core description file, the component description file corresponding to the component identifier is selected from all component description files, and the selected component description file is determined as the component description file corresponding to the core description file.
9. The method for generating configuration files according to claim 5, wherein:

   The component information includes at least a component identification;

   Each component description file includes the corresponding component identification;

   According to the obtained component description file and the core description file, the core assembly file for generating the core description file includes:

   Determine the component description file corresponding to each component identifier according to the component identifier in the core description file;

   The component description file corresponding to each component identifier is assembled into the core description file to obtain the core assembly file of the core description file.
10. The method for generating a configuration file according to claim 9, wherein:

    Assembling the component description file corresponding to each component identifier into the core description file includes:

    Replacing the component information where each component identifier is located in the core description file with the content in the component description file corresponding to each component identifier;

    or,

    All the component information in the component description file corresponding to each component identifier is inserted into the component information where each component identifier in the core description file is located.
11. The method for generating a configuration file according to claim 4, wherein:

    The nuclear information includes at least a nuclear identifier;

    Each core assembly file includes the corresponding core identification;

    Generating the specification description file according to the chip description file and each core assembly file includes:

    Determining the core assembly file corresponding to each core identification according to the core identification in the chip description file;

    The core assembly file corresponding to each core identifier is assembled into the chip description file to obtain the specification description file.
12. The configuration file generation method according to claim 11, wherein:

    Assembling the core assembly file corresponding to each core identifier into the chip description file includes:

    Replacing the core information where each core identifier is located in the chip description file with the content in the core assembly file corresponding to each core identifier;

    or,

    Insert all component information in the core assembly file corresponding to each core identifier into the core information where each core identifier is located in the chip description file.
13. The method for generating a configuration file according to any one of claims 1-12, wherein:

    The target chip is a DSP chip.
14. The method for generating a configuration file according to claim 13, wherein:

    The multiple chip development modules include at least: a software simulation module, an RTL code integration module, and an EDA verification module;

    According to the specification description file, the configuration files of the multiple chip development modules of the target chip are uniformly determined, including:

    Determine the software configuration file required by the software simulation module according to the specification description file;

    Determine the RTL top-level code file required by the RTL code integration module and the EDA verification module according to the specification description file.
15. The method for generating a configuration file according to claim 14, wherein determining the software configuration file required by the software simulation module according to the specification description file comprises:

    The specification description file is converted to generate the software configuration file, so that the software configuration file can be applied to the software simulation module.
16. The configuration file generating method according to claim 14, wherein:

    Uniformly determining the configuration files of the multiple chip development modules of the target chip according to the specification description file further includes:

    Extract user-oriented configuration information from the specification description file;

    According to the extracted configuration information, the first header file required by the software simulation module, the RTL code integration module and the EDA verification module is generated.
17. The configuration file generation method according to claim 16, wherein:

    The first header file includes: C language header file and ASM header file.
18. The configuration file generating method according to claim 14, wherein:

    Uniformly determining the configuration files of the multiple chip development modules of the target chip according to the specification description file further includes:

    Extract the register address used for EDA verification from the specification description file;

    Generate the second header file required by the EDA verification module according to the extracted register address.
19. A configuration file generating device, which is characterized by comprising: a processor and a memory;

    The memory is used to store program code;

    The processor is used to call the program code, and when the program code is executed, it is used to perform the following operations:

    Obtain description files related to the target chip;

    According to the description file, a configuration file of multiple chip development modules is uniformly generated, and the configuration file is used to enable the multiple chip development modules to develop the target chip.
20. The configuration file generating device according to claim 19, wherein:

    When the processor generates configuration files of multiple chip development modules of the target chip according to the description file, it is specifically used for:

    Generating a specification description file of the target chip according to the description file;

    The configuration files of multiple chip development modules of the target chip are determined according to the specification description file.
21. 22. The configuration file generating device according to claim 20, wherein the description file comprises:

    A chip description file of the target chip, where the chip description file contains core information in the target chip;

    The core description file of each core in the target chip, and each core description file contains the component information in the corresponding core;

    And, the component description file of each component in each core in the target chip, and each component description file contains the composition information of the corresponding component.
22. 21. The configuration file generating device according to claim 21, wherein when the processor generates the specification description file of the target chip according to the description file, it is specifically configured to:

    Generating a core assembly file according to at least one of the core description files and corresponding component description files;

    The specification description file is generated according to the chip description file and each core assembly file.
23. The configuration file generating device according to claim 22, wherein:

    Each core description file includes the corresponding core identification;

    When the processor generates a core assembly file according to at least one of the core description file and the corresponding component description file, it is specifically configured to:

    According to the core identification corresponding to each core description file, check whether the core assembly file corresponding to the core identification currently exists;

    If not, obtain the component description file corresponding to the core description file from all component description files, and generate the core assembly file of the core description file according to the obtained component description file and the core description file.
24. The configuration file generating device according to claim 23, wherein the processor is further configured to:

    If the core assembly file corresponding to the core identifier currently exists, the core assembly file is determined as the core assembly file of the core description file.
25. The configuration file generating device according to claim 23, wherein:

    The component information includes at least a component identification;

    When the processor obtains the component description file required by the core description file from all component description files, it is specifically used for:

    According to the component identification in the core description file, the component description file corresponding to the core description file is obtained from all the component description files.
26. The configuration file generating device according to claim 25, wherein:

    Each component description file includes the corresponding component identification;

    When the processor obtains the component description file corresponding to the core description file from all the component description files according to the component identifier in the core description file, it is specifically used for:

    According to each component identifier in the core description file, the component description file corresponding to the component identifier is selected from all component description files, and the selected component description file is determined as the component description file corresponding to the core description file.
27. The configuration file generating device according to claim 23, wherein:

    The component information includes at least a component identification;

    Each component description file includes the corresponding component identification;

    When the processor generates the core assembly file of the core description file according to the obtained component description file and the core description file, it is specifically used for:

    Determine the component description file corresponding to each component identifier according to the component identifier in the core description file;

    The component description file corresponding to each component identifier is assembled into the core description file to obtain the core assembly file of the core description file.
28. The configuration file generating device according to claim 27, wherein:

    When the processor assembles the component description file corresponding to each component identifier into the core description file, it is specifically used for:

    Replacing the component information where each component identifier is located in the core description file with the content in the component description file corresponding to each component identifier;

    or,

    All the component information in the component description file corresponding to each component identifier is inserted into the component information where each component identifier in the core description file is located.
29. The configuration file generating device according to claim 22, wherein:

    The nuclear information includes at least a nuclear identifier;

    Each core assembly file includes the corresponding core identification;

    When the processor generates the specification description file according to the chip description file and each core assembly file, it is specifically used for:

    Determining the core assembly file corresponding to each core identification according to the core identification in the chip description file;

    The core assembly file corresponding to each core identifier is assembled into the chip description file to obtain the specification description file.
30. The configuration file generating device according to claim 29, wherein:

    When the processor assembles the core assembly file corresponding to each core identifier into the chip description file, it is specifically used to:

    Replacing the core information where each core identifier is located in the chip description file with the content in the core assembly file corresponding to each core identifier;

    or,

    Insert all component information in the core assembly file corresponding to each core identifier into the core information where each core identifier is located in the chip description file.
31. The configuration file generating device according to any one of claims 19-30, wherein:

    The target chip is a DSP chip.
32. The configuration file generating device according to claim 31, wherein:

    The multiple chip development modules include at least: a software simulation module, an RTL code integration module, and an EDA verification module;

    When the processor uniformly determines the configuration files of multiple chip development modules of the target chip according to the specification description file, it is specifically used for:

    Determine the software configuration file required by the software simulation module according to the specification description file;

    Determine the RTL top-level code file required by the RTL code integration module and the EDA verification module according to the specification description file.
33. The configuration file generating device according to claim 32, wherein when the processor determines the software configuration file required by the software simulation module according to the specification description file, it is specifically configured to:

    The specification description file is converted to generate the software configuration file, so that the software configuration file can be applied to the software simulation module.
34. The configuration file generating device according to claim 32, wherein:

    When the processor uniformly determines the configuration files of multiple chip development modules of the target chip according to the specification description file, it is further configured to:

    Extract user-oriented configuration information from the specification description file;

    According to the extracted configuration information, the first header file required by the software simulation module, the RTL code integration module and the EDA verification module is generated.
35. The configuration file generating device according to claim 34, wherein:

    The first header file includes: C language header file and ASM header file.
36. The configuration file generating device according to claim 32, wherein:

    When the processor uniformly determines the configuration files of multiple chip development modules of the target chip according to the specification description file, it is further configured to:

    Extract the register address used for EDA verification from the specification description file;

    Generate the second header file required by the EDA verification module according to the extracted register address.
37. A computer-readable storage medium, characterized in that:

    Computer instructions are stored on the computer-readable storage medium, and when the computer instructions are executed, the method for generating a configuration file according to any one of claims 1-18 is realized.

Images