CN115758973A - Method, device and equipment for generating chip register design file and storage medium - Google Patents
Method, device and equipment for generating chip register design file and storage medium Download PDFInfo
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Abstract
The embodiment of the disclosure discloses a method and a device for generating a chip register design file, computer equipment and a storage medium. Wherein the method comprises the following steps: acquiring a description file of a register, and analyzing to acquire the description information of the register in the description file; generating a description document of the register according to the description information of the register and a preset register document template; and generating a code file related to the register according to the description information of the register and a preset register code template. By the method, labor and time are saved for chip development, and secondary development and maintenance of register design are facilitated.
Description
Technical Field
The present disclosure relates to, but not limited to, the field of semiconductor technologies, and in particular, to a method and an apparatus for generating a chip register design file, a computer device, and a storage medium.
Background
In the digital chip, a register is a window for mutual information interaction between hardware and software, and the definition, design and verification of the register are arranged in the front of tasks in the whole chip design period process, so that the information interaction between the hardware and the software is smooth only by ensuring the correct function of the register.
Most chip design companies adopt manual design or script semi-automatic generation design for design and verification of related functions of registers in the chip function development process, the task needs to take days to more than one week to complete convergence, and design verification of registers in different teams or projects of the same company is not uniform in flow, so that the later maintenance work is not facilitated.
Disclosure of Invention
In view of this, the embodiments of the present disclosure at least provide a method and an apparatus for generating a chip register design file, a computer device, and a storage medium.
In a first aspect, an embodiment of the present disclosure provides a method for generating a chip register design file, where the method includes:
acquiring a description file of a register, and analyzing to acquire the description information of the register in the description file;
generating a description document of the register according to the description information of the register and a preset register document template;
and generating a code file associated with the register according to the description information of the register and a preset register code template.
In some embodiments, the obtaining a description file of a register and parsing to obtain description information of the register in the description file includes:
loading the description file by using a first code language, and analyzing to obtain the description information of the register in the description file;
the method further comprises the following steps:
generating the register document template by using a second code language;
generating the description document of the register according to the description information of the register and a preset register document template, wherein the generating of the description document of the register comprises the following steps:
and calling the register document template by using the first code language, and filling the register document template according to the description information to generate a description document of the register.
In some embodiments, the method further comprises:
generating the register code template by using a third code language;
generating a code file associated with the register according to the description information of the register and a preset register code template, wherein the method comprises the following steps of:
and calling the register code template by using the first code language, and filling the register code template according to the description information to generate a code file of the register.
In some embodiments, said invoking said register document template using said first code language and populating said register document template with said description information to generate said register description document comprises:
calling the register document template by using the first code language, and analyzing the field names in the register document template;
and finding information associated with the field names in the description information of the register, and assigning the field names by using the information to generate the description document.
In some embodiments, the invoking the register code template with the first code language and populating the register code template with the description information to generate the code file of the register includes:
calling the register code template by using the first code language, and analyzing a variable name in the register code template;
and finding information associated with the variable name in the description information of the register, and generating the code file after assigning the variable name by using the information.
In some embodiments, said generating a code file associated with said register comprises:
register transfer level RTL code, validation code, software driver code, and validation stimulus code associated with the register are generated.
In some embodiments, the generating the description document of the register includes:
generating a description document in at least one of the following formats: PDF documents, HTML documents, DOC documents, IP-XACT XML documents.
In a second aspect, an embodiment of the present disclosure provides an apparatus for generating a chip register design file, where the apparatus includes:
the acquisition module is configured to acquire a description file of a register and analyze and acquire description information of the register in the description file;
the first generation module is configured to generate a description document of the register according to the description information of the register and a preset register document template;
and the second generation module is configured to generate a code file related to the register according to the description information of the register and a preset register code template.
In some embodiments, the obtaining module is configured to load the description file by using a first code language, and parse to obtain the description information of the register in the description file;
the device further comprises:
a third generation module configured to generate the register document template using a second code language;
the first generation module is configured to call the register document template by using the first code language, and fill the register document template according to the description information to generate the description document of the register.
In some embodiments, the apparatus further comprises:
a fourth generation module configured to generate the register code template using a third code language;
the second generation module is configured to call the register code template by using the first code language, and fill the register code template according to the description information to generate a code file of the register.
In some embodiments, the first generation module is configured to call the register document template using the first code language and analyze field names in the register document template; and finding information associated with the field names in the description information of the register, and assigning the field names by using the information to generate the description document.
In some embodiments, the second generation module is configured to call the register code template by using the first code language and analyze a variable name in the register code template; and finding information associated with the variable name in the description information of the register, and generating the code file after assigning the variable name by using the information.
In some embodiments, the second generation module is configured to generate register transfer level RTL code, validation code, software driver code, and validation stimulus code associated with the register.
In some embodiments, the first generation module is configured to generate the descriptive document in at least one of the following formats: PDF documents, HTML documents, DOC documents, IP-XACT XML documents.
In a third aspect, an embodiment of the present disclosure provides a computer device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the method of the first aspect.
In a fourth aspect, the embodiments of the present disclosure provide a storage medium on which a computer program is stored, which when executed by a processor implements the method described in the first aspect.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
in the embodiment of the disclosure, after the description file of the register is analyzed by the computer device to obtain the description information, the description file of the register is generated by combining with the preset register file template, and the code file of the associated register is generated by combining with the preset register code template, on one hand, a one-stop solution including codes and documents is generated in an automatic mode without depending on a commercial EDA tool, so that the related requirements of register design can be effectively solved, and the manpower and time are saved for chip development; on the other hand, if new register design requirements exist subsequently, the scheme of the embodiment of the disclosure can facilitate secondary development and maintenance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic flow chart illustrating an implementation of a method for generating a chip register design file according to an embodiment of the present disclosure;
FIG. 2 is a diagram of an example of a description document in register PDF format according to an embodiment of the present disclosure;
FIG. 3 is a diagram of an example of a description document in a register HTML format according to an embodiment of the present disclosure;
fig. 4 is a flowchart illustrating a method for generating a chip register design file according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an apparatus for generating a chip register design file according to an embodiment of the present disclosure;
fig. 6 is a hardware entity diagram of a computer device according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated with reference to the drawings and the following embodiments, which should not be construed as limiting the present disclosure, and all other embodiments obtained by a person of ordinary skill in the art without making creative efforts fall within the protection scope of the present disclosure.
Reference to the terms "first/second/third" in this disclosure are only to distinguish between similar objects and do not denote a particular order, but rather are to be understood that "first/second/third" may, where permissible, be interchanged in a particular order or sequence so that embodiments of the disclosure described herein can be practiced in other than that shown or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing the disclosure only and is not intended to be limiting of the disclosure.
Many chip design companies in the industry currently use a Register function definition description file in an IP-XACT XML format, which is a Register definition format of IEEE (IEEE-1685) standard, and the use of the IP-XACT format to define and describe Register information has the advantage of being able to be seamlessly interfaced with many EDA tools, such as ralgen tool of Synopsys, iregen tool of Cadence, register Assistant tool of Mentor, etc., and UVM (Universal Verification Methodology) Register model codes of corresponding modules can be automatically generated by using the Register description file in the IP-XACT format as input. However, the register information described by the IP-XACT XML format has the defects of poor readability, and the modification, updating, consulting and the like of the register information at the later stage are not convenient; and the most important point is that RTL (Register Transfer Level) codes and Register function documents related to Register design cannot be generated by the EDA tool; furthermore, plus if EDA tools are used, corresponding licensing is required, such as the business tool License.
Therefore, the related business EDA tools cannot support the code and document requirements in the register design process well, and the learning cost of the business EDA tools and the cost of the tools and the License matched with the business EDA tools are not small, so that the chip register design based on the business EDA tools is too limited.
In view of this, the disclosed embodiments provide a method for generating a chip register design file, which may be executed by a processor of a computer device. The computer device may be a server, a notebook computer, a tablet computer, or other device with data processing capability.
Fig. 1 is a schematic flow chart of an implementation process of a method for generating a chip register design file according to an embodiment of the present disclosure, as shown in fig. 1, the method includes the following steps:
s11, obtaining a description file of a register, and analyzing to obtain description information of the register in the description file;
s12, generating a description document of the register according to the description information of the register and a register document template;
and S13, generating a code file related to the register according to the description information of the register and the register code template.
In the embodiment of the present disclosure, the computer device obtains a description file of the register, where the description file is a file that is convenient for a user to edit and refer, such as an Excel format or a Word format. The description file includes description information of the register, and the description information may include: the register domain information comprises a domain name, a domain comment, an offset address of the domain, a read-write permission type of the domain, an initial value, register domain information and the like. Common types of read-write rights are, for example, a readable-writable (RW) type, a read-only (RO) type, a write-only (WO) type, a read-clear (RC) type, a write-1-clear (W1C) type, etc.
It should be noted that one or more registers may be included on one chip, and the concatenation of one or more bits (bits) of a register is referred to as a register field, and a register may be divided into one or more register fields. In the embodiment of the present disclosure, the description file may include description information of one or more registers, and may further include description information of one or more register fields of one register.
In one embodiment, the computer device searches the key fields in the description file according to pre-stored key fields, and acquires the content corresponding to the key fields according to a known format, thereby establishing mapping between the key fields and the content.
Illustratively, table 1 is an example of a part of contents in a description file in an Excel format, as shown in table 1:
TABLE 1 description of the registers
Wherein, register Name is the Name of the Register, register Description is the comment of the Register, register Address is the Register Address, register Width is the Register bit Width, register Access is the Register read-write authority, register Reset Value is the Register initial Value.
Generally, in an Excel format file, contents in each column of a first row are used for representing a key field, and corresponding contents are filled in each row except the first row according to the key field of the column. Thus, the computer device can obtain the mapping between the key fields and the content after parsing based on the known format and the pre-stored key fields.
In another embodiment, the contents in the description file may be parsed based on a deep learning model, so as to establish a mapping between the key fields and the contents, i.e., to obtain the description information of the registers. In the embodiment of the present disclosure, the Deep learning model may be obtained by training and tuning a network such as a Convolutional Neural Network (CNN) and a Deep learning network (Deep Neural network, DNN) based on training sample data and a label value. The training sample data comprises different field names of the registers and description contents of the registers, and the label value is the corresponding relation between the field names and the description contents. It should be noted that the field names characterizing the same meaning in the training sample data may include different description forms, such as the Name of a Register, which may be expressed by "Register Name" or "Register Name"; for another example, the Register read/write authority may be expressed by "Register Access", or "Register authority", and the corresponding type of authority supporting read/write may be expressed by "RW", or "read/write" or "readable/writable".
Based on the trained deep learning model, the content in the description file is input into the deep learning model, and the description information of the register can be obtained through the model. It can be understood that, based on the manner, the constraints on the arrangement format of the content in the description file and the description form of the content are small, and the user does not need to edit the description file according to a fixed format, so that the scheme based on deep learning model analysis in the embodiment of the present disclosure has higher flexibility and better universality.
In the embodiment of the present disclosure, the description information of the register obtained after parsing may be stored in the computer device according to the following format: [ { ' regName ': REG _ HEAD ', ' regDescription ': register header ', ' regAddr ': 0x00', ' regWidth ': 32', ' regAccess ': RW ', ' regretval ': 0x0' } ], exemplary ' regName ': REG _ HEAD ' is a mapping between a set of key fields and content.
In the embodiment of the present disclosure, after the computer device obtains the description information of the register by parsing, the computer device may generate the description document of the register by combining with a preset register document template. The register document template may be a code file stored in a computer, and includes field names associated with general register description information, and a layout style of the register description information, where the layout style includes a position of each field name, a position to be filled in field content, a field name, a font of the content to be filled, a font size, a font color, and the like.
It should be noted that, in the embodiment of the present disclosure, the register document template is a template that is not filled with specific register information, the description document of the register is a document after rendering and filling with the register information, and the description document of the register is a document saved in a file format, which is not a code file format.
In the embodiment of the present disclosure, after the computer device obtains the description information of the register by parsing, a code file associated with the register may be generated by combining with a preset register code template. The register code template may be a code file stored in a computer, and includes field names associated with register description information, and logic description of a register function, for example, a writable function of a register, where the logic description includes: writing data to the register; the register code template may also include function verification code, such as determining whether the contents of the register store and the register write are consistent. In addition, the register code template further includes a C/C + + model code, a software and hardware simulation excitation code, and the like, which is not limited in the embodiment of the present disclosure.
It should be noted that the preset register document template and the register code template may be developed in advance by a developer, for example, by collecting and analyzing the type requirement defined by the register in the chip design and the corresponding function implementation requirement and then developing. The template library can maximally encapsulate general data structures and methods related to the registers, and the register document template library can maximally encapsulate generation styles and the like of documents, so that the workload of developing the registers is saved, and the efficiency of register development is improved. Moreover, if the general requirements of the register are upgraded, developers can respond to the development requirements of the register by updating and upgrading the register document template and the register code template; in addition, if there is a personalized demand for register development, developers may also define their own required classes by extending, for example, base classes in a register code template, and add specific information of registers.
It can be understood that, in the embodiment of the present disclosure, after the computer device parses the description file of the register to obtain the description information, the description file of the register is generated in combination with the preset register file template, and the code file associated with the register is generated in combination with the preset register code template, on one hand, a one-stop solution including codes and files is generated in an automated manner without depending on a commercial EDA tool, which can effectively solve the related requirements of register design and save labor and time for chip development; on the other hand, if new register design requirements exist subsequently, the scheme of the embodiment of the disclosure can facilitate secondary development and maintenance.
As described above, in the embodiment of the present disclosure, the description file may be in an Excel format, and compared to the description file in the IP-XACT XML format, since the IP-XACT XML is a standard format defined by IEEE and belongs to a format that does not support human editing, and the visualization effect is poor for the user if the description file is directly opened for viewing, while the Excel table format is simpler for the user than the XML format, it can be understood that the readability and the usability of the description file format in which the Excel format is used as the register are also better.
In some embodiments, the obtaining a description file of a register and parsing to obtain description information of the register in the description file includes:
loading the description file by using a first code language, and analyzing to obtain the description information of the register in the description file;
the method further comprises the following steps:
generating the register document template by using a second code language;
generating the description document of the register according to the description information of the register and a preset register document template, wherein the generating of the description document of the register comprises the following steps:
and calling the register document template by using the first code language, and filling the register document template according to the description information to generate a description document of the register.
In the embodiment of the present disclosure, the first code language may be a Python language, or may be other code languages such as Ruby or Perl. Because the generation method of the register design file in the embodiment of the present disclosure is a method based on full software, the first code language may be selected as the Python language in consideration of the portability of the code across platforms, the convenience of using the code language (for example, the use of memory management or a standard library, etc.), and the extensibility of the code.
In the embodiment of the present disclosure, the second code language may include a Java language, and may also be a C/C + + code language. In view of the wide use of Python language and Java language, and the advantage that Java language also has a cross-platform advantage, and can be transplanted to different operating systems for running, the embodiments of the present disclosure may also use Java language to generate a register document template, use Python language to load and parse a description file to obtain description information, and use Python language to call the register document template of Java language to fill the description file of the generated register in the register document template according to the description information.
It can be understood that, in the embodiment of the present disclosure, in combination with the excellent idea of software development, on one hand, a register is modeled by software to generate a register document template, which facilitates subsequent maintenance and upgrade; on the other hand, different code languages are used to respectively execute respective functions, and the computer device utilizes the first code language to perform cross-platform interface calling (namely calling a register document template generated by the second code language), so that different functional modules are mutually decoupled, the technical limit on developers can be reduced, cooperation development is facilitated, and the method for generating the chip register design file provided by the embodiment of the disclosure has wider applicability.
In some embodiments, the method further comprises:
generating the register code template by using a third code language;
generating a code file associated with the register according to the description information of the register and a preset register code template, wherein the code file comprises:
and calling the register code template by using the first code language, and filling the register code template according to the description information to generate a code file of the register.
In the embodiment of the present disclosure, the third code language may include a code template language such as Mako language, jinja2, and the like, and may further include a hardware description language such as Verilog, and the like. Both Mako and Jinja2 are based on a Python template engine, and considering that the code template language supported by Mako has more functions, the embodiment of the disclosure may select the first code language as Python language, the third code language includes Mako language, the register code template is generated by using the Mako language, and the register document template generated based on Mako is called by using Python, so as to fill the code file of the register code template generation register according to the description information.
It can be understood that, in the embodiment of the present disclosure, in combination with the excellent idea of software development, on one hand, the register is modeled by software to generate a register code template, which facilitates subsequent maintenance and upgrade; on the other hand, different code languages respectively execute respective functions, and the computer device performs cross-platform interface calling (namely calling a register code template generated by the third code language) by using the first code language, so that different functional modules are decoupled from each other, technical limitations on developers are reduced, cooperative development is facilitated, and the method for generating the chip register design file provided by the embodiment of the disclosure has wider applicability.
In some embodiments, said invoking said register document template using said first code language and populating said register document template with said description information to generate said register description document comprises:
calling the register document template by using the first code language, and analyzing the field names in the register document template;
and finding information associated with the field names in the description information of the register, and assigning the field names by using the information to generate the description document.
In the embodiment of the present disclosure, after the computer device calls the Register document template by using the first code language, the field names in the Register document template are analyzed, for example, the computer device finds the field names such as "Address", "Register Name", "Description" and the like in the Register document template. It should be noted that the field names in the register document template are not limited to be described by english characters, and may also be described by any language, such as chinese, and the embodiment of the present disclosure is not limited thereto.
After the field names in the register document template are obtained through analysis, the computer equipment can inquire the information related to the field names in the description information of the register, and generates the description document after the field names are assigned by the information. It should be noted that, when querying information associated with a field name in the description information, the computer device preferentially searches the description information for a key field corresponding to the field name, and assigns a value to the field name by using content corresponding to the key field.
Illustratively, for the "Address" field in the register document template, the computer device preferentially searches the key field "regaddress" corresponding to the "Address" field in the description information, and then assigns a value to the "Address" field by using the content "0 x 00" corresponding to the "regaddress".
In some embodiments, the computer device may store a mapping relationship between the field names in the register document template and the key fields in the description information in advance, and based on the mapping relationship, the computer device may conveniently query and assign the information associated with the field names.
In other embodiments, the computer device further includes a semantic analysis model, and the computer device may identify semantics of the field names in the register document template and semantics of the key fields in the description information by using the semantic analysis model, and establish a mapping between the field names and the key fields with semantic similarity greater than a preset similarity threshold. The computer device may then query for information associated with the field name based on the mapping and assign a value.
It should be noted that, in the embodiment of the present disclosure, the semantic analysis model is a model capable of extracting important tags based on text content, for example, if the text content is "address of register" or "address", the extracted tags are "address". The semantic analysis model may also be obtained based on neural network model training, for example, obtained by performing training and parameter-tuning on a network such as CNN based on training sample data and a label value. The training sample data comprises different text contents, and the label value is a label corresponding to the text contents.
It can be understood that, based on the semantic analysis model, the mapping relationship between the field names in the register document template and the key fields in the description information does not need to be stored in advance, so that the constraint on developers is smaller, the cooperative development of different teams is facilitated, and the generation method of the chip register design file provided by the embodiment of the disclosure is more intelligent.
In the embodiment of the disclosure, the computer device analyzes the field names in the register document template, and transmits the analyzed description information to the corresponding field names in the register document template to render and generate the document, so that the scheme is simple and effective.
In some embodiments, the invoking the register code template with the first code language and populating the register code template with the description information to generate the code file of the register includes:
calling the register code template by using the first code language, and analyzing a variable name in the register code template;
and finding information associated with the variable name in the description information of the register, and assigning the variable name by using the information to generate the code file.
In the embodiment of the present disclosure, after the computer device calls the register code template by using the first code language, the variable name in the register code template is analyzed, for example, the computer device finds the variable name such as "fieldName", "width", "offset" in the register code template, then queries the information associated with the variable name in the description information of the register, and generates the code file after assigning the variable name with the information. It should be noted that, when querying information associated with a variable name in the description information, the computer device preferentially searches a key field corresponding to the variable name in the description information, and assigns a value to the variable name by using content corresponding to the key field.
Illustratively, for the "Width" variable name in the Register code template, the computer device preferentially finds the key field "Register Width" corresponding to the "Width" variable name in the description information, and then assigns a value to the "Width" variable name using the content "32" corresponding to the "Register Width".
It should be noted that, the computer device may also store in advance a mapping relationship between a variable name in the register code template and a key field in the description information, and based on the mapping relationship, the computer device is convenient to query information associated with the variable name and perform assignment.
In the embodiment of the disclosure, the computer device analyzes the variable names in the register code template, and transmits the analyzed description information to the corresponding variable names in the register code template to generate the code file, so that the scheme is simple and effective.
In some embodiments, said generating a code file associated with said register comprises:
register transfer level RTL code, validation code, software driver code, and validation stimulus code associated with the register are generated.
In the embodiment of the disclosure, the code file generated by the computer device according to the description information of the register and the register code template comprises an RTL code, a verification code, a software driver code and a verification excitation code, and also comprises an RTL interrupt code. The RTL code is a code description of register transmission level for realizing specific circuits of the register, and is used for describing the functions of the register and logic functions between the register and the register; the verification code is a code for verifying the register function, and may be, for example, a UVM model code, an SV verification code, or the like; the software driver code may be C/C + + driver code (i.e., C/C + + model code); the verification excitation code may be a software and hardware simulation verification excitation code, and the software and hardware simulation excitation code is used for exciting the UVM model and the register, respectively, and comparing whether an output value of the UVM model is consistent with an output value of the register, so as to verify whether the function of the register is correct.
In the embodiment of the present disclosure, the code file of the associated register may include a file in Verilog format, a file in Python format, a file in VHDL format, a file in C/C + + format, and the like, which is not limited in the embodiment of the present disclosure.
It can be understood that, in the embodiment of the present disclosure, the computer device generates the RTL code, the verification code, the software driver code, and the verification driver code according to the description information of the register and the preset register code template, and provides a complete scheme from the register requirement definition to the automatic generation of the design code to the automatic generation of the functional verification driver code.
In some embodiments, the generating the description document of the register includes:
generating a description document in at least one of the following formats: PDF documents, HTML documents, DOC documents, IP-XACT XML documents.
In the embodiment of the present disclosure, a computer device may support generating documents in multiple formats, fig. 2 is an exemplary diagram of a description document in a register PDF format provided in the embodiment of the present disclosure, and fig. 3 is an exemplary diagram of a description document in a register HTML format provided in the embodiment of the present disclosure. As shown in fig. 2 and fig. 3, the description document includes the address, name, description information, and other contents of the register, and for the same register, the contents in the description documents in different formats are the same, except that the layout style may be different.
It should be noted that, in the embodiment of the present disclosure, the computer device further supports generating an IP-XACT XML document, so that the generated description document may also be compatible with a third party EDA tool, and a trouble that a register document generated by a self-development tool cannot be introduced into the third party EDA tool, and thus secondary development and conversion are required is reduced.
It can be understood that the computer device supports document generation in various formats, and on one hand, compared with a scheme which only supports generation of UVM model codes and cannot automatically generate register description documents based on an EDA tool, the scheme provided by the embodiment of the disclosure has higher automation degree; on the other hand, the embodiment of the disclosure also supports documents in an IP-XACT XML format, is convenient to access an EDA tool, and can accelerate the development speed of chip functions.
Fig. 4 is a flowchart illustrating a method for generating a chip register design file according to an embodiment of the present disclosure, as shown in fig. 4, including the following steps:
s21, acquiring a register function requirement table in an Excel format;
in the embodiment of the present disclosure, the register function requirement table in the Excel format is a description file of a register acquired by a computer device.
S22, analyzing the function of a register;
in the disclosed embodiments, the computer device performs register function parsing to obtain description information of registers in the register function requirement table.
S23, establishing a register information database;
in the embodiment of the disclosure, the computer device establishes a register information database, that is, the description information obtained by parsing is stored according to the mapping between the key field and the content.
S24a-S24f, register RTL design code generation, register SV/UVM verification code generation, register C/C + + model code generation, register software and hardware simulation verification excitation code generation, register DOC/PDF/HTML document generation and register IP-XACT information file generation.
In the embodiment of the disclosure, an RTL design code, a register SV/UVM verification code, a C/C + + model code and a register software and hardware simulation verification excitation code all belong to code files of associated registers; DOC/PDF/HTML documents and register IP-XACT information files belong to the description documents of the registers.
In the embodiment of the disclosure, after the computer device analyzes the function requirement table of the register to obtain the register information, the description document of the register and the code file of the associated register are automatically generated, on one hand, a one-stop solution including the code and the document is generated in an automatic mode without depending on a commercial EDA tool, so that the related requirements of register design can be effectively solved, and the labor and the time are saved for chip development; on the other hand, if new register design requirements exist subsequently, the scheme of the embodiment of the disclosure can facilitate secondary development and maintenance.
Fig. 5 is a schematic structural diagram of a device for generating a chip register design file according to an embodiment of the present disclosure, and as shown in fig. 5, the device 500 for generating a chip register design file includes:
an obtaining module 501, configured to obtain a description file of a register, and analyze and obtain description information of the register in the description file;
a first generating module 502 configured to generate a description document of the register according to the description information of the register and a preset register document template;
the second generating module 503 is configured to generate a code file associated with the register according to the description information of the register and a preset register code template.
In some embodiments, the obtaining module 501 is configured to load the description file by using a first code language, and parse to obtain the description information of the register in the description file;
the device further comprises:
a third generation module configured to generate the register document template using a second code language;
the first generating module 502 is configured to call the register document template by using the first code language, and fill the register document template according to the description information to generate the description document of the register.
In some embodiments, the apparatus further comprises:
a fourth generation module configured to generate the register code template using a third code language;
the second generating module 503 is configured to call the register code template by using the first code language, and fill the register code template according to the description information to generate a code file of the register.
In some embodiments, the first generating module 502 is configured to call the register document template by using the first code language and analyze field names in the register document template; and finding information associated with the field names in the description information of the register, and assigning the field names by using the information to generate the description document.
In some embodiments, the second generating module 503 is configured to call the register code template by using the first code language, and analyze a variable name in the register code template; and finding information associated with the variable name in the description information of the register, and generating the code file after assigning the variable name by using the information.
In some embodiments, the second generating module 503 is configured to generate register transfer level RTL code, verification code, software driver code, and verification stimulus code associated with the register.
In some embodiments, the first generating module 502 is configured to generate the description document in at least one of the following formats: PDF documents, HTML documents, DOC documents, IP-XACT XML documents.
The above description of the apparatus embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. In some embodiments, functions of or modules included in the apparatuses provided in the embodiments of the present disclosure may be used to perform the methods described in the above method embodiments, and for technical details not disclosed in the embodiments of the apparatuses of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.
It should be noted that, in the embodiment of the present disclosure, if the method for generating a chip register design file is implemented in the form of a software functional module and is sold or used as a standalone product, the method may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present disclosure are not limited to any specific hardware, software, or firmware, or any combination thereof.
The embodiment of the present disclosure provides a computer device, which includes a memory and a processor, where the memory stores a computer program that can be run on the processor, and the processor implements some or all of the steps of the above method when executing the program.
The disclosed embodiments provide a computer-readable storage medium having stored thereon a computer program that, when executed by a processor, performs some or all of the steps of the above-described method. The computer readable storage medium may be transitory or non-transitory.
The disclosed embodiments provide a computer program comprising computer readable code, where the computer readable code runs in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.
The disclosed embodiments provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program that when read and executed by a computer performs some or all of the steps of the above method. The computer program product may be embodied in hardware, software or a combination thereof. In some embodiments, the computer program product is embodied in a computer storage medium, and in other embodiments, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.
Here, it should be noted that: the foregoing description of the various embodiments is intended to highlight various differences between the embodiments, which are the same or similar and all of which are referenced. The above description of the apparatus, storage medium, computer program and computer program product embodiments is similar to the description of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the disclosed apparatus, storage medium, computer program and computer program product, reference is made to the description of the embodiments of the method of the present disclosure for understanding.
Fig. 6 is a schematic diagram of hardware entities of a computer device according to an embodiment of the present disclosure, and as shown in fig. 6, the hardware entities of the computer device 600 include: a processor 601, a communication interface 602, and a memory 603, wherein:
the processor 601 generally controls the overall operation of the computer device 600.
The communication interface 602 may enable the computer device to communicate with other terminals or servers via a network.
The Memory 603 is configured to store instructions and applications executable by the processor 601, and may also buffer data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or already processed by the processor 601 and modules in the computer apparatus 600, and may be implemented by a FLASH Memory (FLASH) or a Random Access Memory (RAM). Data may be transferred between the processor 601, the communication interface 602, and the memory 603 via the bus 604.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, in various embodiments of the present disclosure, the sequence number of each step/process does not mean the execution sequence, and the execution sequence of each step/process should be determined by the function and the inherent logic of the step/process, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
Alternatively, the integrated unit of the present disclosure may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure.
Claims (10)
1. A method for generating a chip register design file, the method comprising:
acquiring a description file of a register, and analyzing to acquire the description information of the register in the description file;
generating a description document of the register according to the description information of the register and a preset register document template;
and generating a code file related to the register according to the description information of the register and a preset register code template.
2. The method according to claim 1, wherein the obtaining a description file of registers and parsing to obtain description information of the registers in the description file comprises:
loading the description file by using a first code language, and analyzing to obtain the description information of the register in the description file;
the method further comprises the following steps:
generating the register document template by using a second code language;
generating the description document of the register according to the description information of the register and a preset register document template, wherein the generating of the description document of the register comprises the following steps:
and calling the register document template by using the first code language, and filling the register document template according to the description information to generate a description document of the register.
3. The method of claim 2, further comprising:
generating the register code template by using a third code language;
generating a code file associated with the register according to the description information of the register and a preset register code template, wherein the code file comprises:
and calling the register code template by using the first code language, and filling the register code template according to the description information to generate a code file of the register.
4. The method of claim 2, wherein said invoking the register document template using the first code language and populating the register document template with the description information to generate the register description document comprises:
calling the register document template by using the first code language, and analyzing field names in the register document template;
and finding information associated with the field names in the description information of the register, and assigning the field names by using the information to generate the description document.
5. The method of claim 3, wherein said calling the register code template using the first code language and populating the register code template with the description information to generate the code file for the register comprises:
calling the register code template by using the first code language, and analyzing a variable name in the register code template;
and finding information associated with the variable name in the description information of the register, and generating the code file after assigning the variable name by using the information.
6. The method of any of claims 1 to 5, wherein the generating a code file associated with the register comprises:
register transfer level RTL code, verification code, software driver code, and verification stimulus code associated with the register are generated.
7. The method according to any one of claims 1 to 5, wherein the generating the description document of the register comprises:
generating a description document in at least one of the following formats: PDF documents, HTML documents, DOC documents, IP-XACT XML documents.
8. An apparatus for generating a chip register design file, comprising:
the acquisition module is configured to acquire a description file of a register and analyze and acquire description information of the register in the description file;
the first generation module is configured to generate a description document of the register according to the description information of the register and a preset register document template;
and the second generation module is configured to generate a code file related to the register according to the description information of the register and a preset register code template.
9. A computer device comprising a memory and a processor, the memory storing a computer program operable on the processor, wherein the processor implements the steps of the method of any one of claims 1 to 7 when executing the program.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115983173A (en) * | 2023-03-21 | 2023-04-18 | 湖北芯擎科技有限公司 | Register model generation method and device, computer equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115983173A (en) * | 2023-03-21 | 2023-04-18 | 湖北芯擎科技有限公司 | Register model generation method and device, computer equipment and storage medium |
| CN115983173B (en) * | 2023-03-21 | 2023-07-07 | 湖北芯擎科技有限公司 | Register model generation method, device, computer equipment and storage medium |
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