CN117677854A

CN117677854A - Current detection device and current detection method

Info

Publication number: CN117677854A
Application number: CN202280048795.6A
Authority: CN
Inventors: 夏木亮
Original assignee: Shindengen Electric Manufacturing Co Ltd
Current assignee: Shindengen Electric Manufacturing Co Ltd
Priority date: 2022-06-23
Filing date: 2022-06-23
Publication date: 2024-03-08
Also published as: JP7309088B1; JPWO2023248430A1; WO2023248430A1

Abstract

The current detection device of the present invention includes: a plurality of first rogowski coils for detecting a current flowing through the first switching element; a plurality of second rogowski coils for detecting a current flowing through the second switching element; the first integrating circuits are provided with a reset function, integrate the output of the first rogowski coil and then output a first detection signal; the plurality of second integrating circuits are provided with a reset function, and output second detection signals after integrating the output of the second rogowski coil; a detection processing unit that detects a current flowing through the inverter unit based on the first detection signal and the second detection signal; a first reset output unit that outputs a first reset signal for resetting the plurality of first integrating circuits during a first period in which all the first switching elements are in a non-conductive state; and a second reset output unit that outputs a second reset signal for resetting the plurality of second integrating circuits during a second period in which all the second switching elements are in a non-conductive state.

Description

Current detection device and current detection method

Technical Field

The present invention relates to a current detection device and a current detection method.

Background

In recent years, as a technique for detecting a current in motor drive control or the like, a technique using a rogowski coil has been known (for example, refer to patent document 1). In this prior art, the output of the rogowski coil is integrated using an integrator with a reset function, thereby detecting a current.

[ Prior Art literature ]

[ patent literature ]

[ patent document 1 ] International publication No. 2021/066153

However, in the above-described prior art, for example, when detecting the current flowing through the three-phase driven inverter section, it is necessary to provide one reset output circuit for each rogowski coil, which leads to a complication of the structure.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a current detection device and a current detection method that can simplify the structure.

Disclosure of Invention

A current detection device according to an aspect of the present invention includes a plurality of sets of first switching elements and second switching elements connected in series, and detects a current flowing through an inverter unit that generates ac signals of a plurality of phases, and includes: a plurality of first rogowski coils, which are respectively in one-to-one correspondence with the first switching elements, for detecting a current flowing through the first switching elements; a plurality of second rogowski coils, respectively corresponding to the second switching elements one by one, for detecting a current flowing through the second switching elements; the first integrating circuits are respectively in one-to-one correspondence with the first rogowski coils and have a reset function and are used for integrating the output of the first rogowski coils and then outputting a first detection signal; the second integrating circuits are respectively in one-to-one correspondence with the second rogowski coils and have a reset function and are used for integrating the output of the second rogowski coils and outputting a second detection signal; a detection processing unit configured to detect a current flowing through the inverter unit based on the first detection signal and the second detection signal; a first reset output unit that outputs a first reset signal for resetting the plurality of first integrated circuits during a first period in which all the first switching elements are in a non-conductive state; and a second reset output unit configured to output a second reset signal for resetting the plurality of second integrated circuits during a second period in which all the second switching elements are in a non-conductive state.

In the current detection device according to one aspect of the present invention, the first reset output unit outputs the first reset signal so that all of the plurality of first integrating circuits are in the reset state during a part of the first period, and the second reset output unit outputs the second reset signal so that all of the plurality of second integrating circuits are in the reset state during a part of the second period.

In one embodiment of the present invention, a current detection device includes: and a timing generation unit configured to generate a reset timing of the first integration circuit and a reset timing of the second integration circuit, wherein the first reset output unit outputs the first reset signal so that all of the plurality of first integration circuits are in a reset state according to the reset timing of the first integration circuit generated by the timing generation unit, and the second reset output unit outputs the second reset signal so that all of the plurality of second integration circuits are in a reset state according to the reset timing of the second integration circuit generated by the timing generation unit.

In one embodiment of the present invention, a current detection device includes: and a control unit configured to control switching of the first switching element and the second switching element, the control unit including the timing generation unit.

In one embodiment of the present invention, the timing generation unit includes a logic circuit that generates a reset timing of the first integration circuit based on a control signal of the first switching element corresponding to the plurality of phases, and generates a reset timing of the second integration circuit based on a control signal of the second switching element corresponding to the plurality of phases.

A current detection method according to an aspect of the present invention includes a plurality of sets of first switching elements and second switching elements connected in series, and detects a current flowing through an inverter unit that generates ac signals of a plurality of phases, and includes: a first integration step of integrating outputs of first rogowski coils, each of which detects a current flowing through the first switching element corresponding to each of the plurality of phases, by a plurality of first integration circuits, and outputting a first detection signal; a second integration step of integrating outputs of the first rogowski coils, each of which detects a current flowing through the second switching element corresponding to each of the plurality of phases, and outputting a second detection signal; a detection processing step of detecting a current flowing through the inverter unit based on the first detection signal and the second detection signal; a first reset step of outputting a first reset signal for resetting the plurality of first integrated circuits in a first period in which all the first switching elements are in a non-conductive state; and a second reset step of outputting a second reset signal for resetting the plurality of second integrated circuits in a second period in which all the second switching elements are in a non-conductive state.

Effects of the invention

According to the present invention, the current detection device outputs the first reset signal for resetting the plurality of first integrated circuits corresponding to the plurality of first rogowski coils during the first period in which all the first switching elements are in the non-conductive state, and outputs the second reset signal for resetting the plurality of second integrated circuits corresponding to the plurality of second rogowski coils during the second period in which all the second switching elements are in the non-conductive state. Accordingly, the current detection device can share the reset signals for the plurality of first integrating circuits, and can share the reset signals for the plurality of second integrating circuits. In this way, since the reset signal can be shared in two systems, the current detection device can be simplified in structure.

Drawings

Fig. 1 is a block diagram showing an example of a motor control device according to an embodiment of the present invention.

Fig. 2 is a block diagram showing an example of a current detection unit according to an embodiment of the present invention.

Fig. 3 is an exemplary circuit diagram showing an integrating circuit of an embodiment of the present invention.

Fig. 4 is a diagram showing a combined signal generation process according to an embodiment of the present invention.

Fig. 5 is an example flowchart showing a detection process of an output current of the current detection device of the embodiment of the present invention.

Fig. 6 is a diagram showing a generation process of a reset signal of the first integrating circuit in the embodiment of the present invention.

Fig. 7 is a flowchart showing an example of the timing generation section of the reset signal of the first integrating circuit according to the embodiment of the present invention.

Fig. 8 is a schematic diagram showing an example of the generation process of the reset signal of the second integrating circuit according to the embodiment of the present invention.

Fig. 9 is a flowchart showing a reset signal timing generation section of the second integrating circuit according to the embodiment of the present invention.

Fig. 10 is a modified diagram showing a timing generation section of the embodiment of the present invention.

Detailed Description

Hereinafter, a current detection device and a current detection method according to an embodiment of the present invention will be described with reference to the drawings.

Fig. 1 is a block diagram of an example of a motor control device 1 according to the present embodiment.

As shown in fig. 1, the motor control device 1 includes a dc power supply 2, a smoothing capacitor 4, a current detection device 10, an inverter unit 20, and a motor control unit 30.

The motor control device 1 is connected to a motor 3.

The dc power supply 2 is, for example, a battery or the like, and supplies dc power to the motor control device 1.

The motor 3 is, for example, a sine wave-driven 3-phase brushless motor, and is driven by an ac signal (U-phase signal, V-phase signal, W-phase signal) supplied from the inverter unit 20 of the motor control device 1.

The smoothing capacitor 4 is connected between a power supply line L1 connected to the positive terminal of the dc power supply 2 and a ground line L2 connected to the negative terminal of the dc power supply 2, and smoothes the dc voltage supplied from the dc power supply 2.

The inverter unit 20 generates ac signals (U-phase signals, V-phase signals, W-phase signals) for driving the motor 3 according to the control of the motor control unit 30. The inverter section 20 includes switching elements 21-1 to 21-3 and switching elements 22-1 to 22-3. The inverter section 20 generates, as a drive signal, a current signal of a three-phase sine wave, for example, phase-shifted by 120 degrees, by switching of the switching elements 21-1 to 21-3 and the switching elements 22-1 to 22-3.

In the present embodiment, the switching elements 21-1 to 21-3 are described as the switching elements 21 in the case where they correspond to the upper arm as the upper switching element (first switching element) and represent any upper switching element provided in the inverter unit 20, or in the case where there is no particular distinction.

The switching elements 22-1 to 22-3 are described as the switching elements 22 in the case where they correspond to the lower arm of the switching element (second switching element) on the lower side and are any of the switching elements on the lower side provided in the power table inverter section 20, or in the case where there is no particular difference.

The switching element 21 and the switching element 22 are connected in series between the power supply line L1 and the ground line L2, and constitute a full bridge circuit. The switching elements 21 (21-1 to 21-3) and the switching elements 22 (22-1 to 22-3) are constituted by, for example, n-type MOSFETs (metal oxide semiconductors). The switching element 21 and the switching element 22 are in an on state (conductive state) when the gate terminal (control terminal) is in a High state, and are in an off state (nonconductive state) when the gate terminal (control terminal) is in a Low state.

The switching element 21-1 and the switching element 22-1 are connected in series between the power supply line L1 and the ground line L2, and constitute a full bridge circuit that generates a U-phase signal as a U-phase drive signal. The switching elements 21-1 and 22-1 perform switching based on control signals (S1, S2) output from the motor control unit 30, and a U-phase signal is output from a node N1 between the switching elements 21-1 and 22-1 connected in series.

The switching element 21-2 and the switching element 22-2 are connected in series between the power supply line L1 and the ground line L2, and constitute a full bridge circuit that generates a V-phase signal as a V-phase drive signal. The switching elements 21-2 and 22-2 perform switching based on control signals (S3, S4) output from the motor control unit 30, and output a V-phase signal from a node N2 between the switching elements 21-2 and 22-2 connected in series.

The switching element 21-3 and the switching element 22-3 are connected in series between the power supply line L1 and the ground line L2, and constitute a full bridge circuit that generates a W-phase signal as a W-phase drive signal. The switching elements 21-3 and 22-3 are switched based on control signals (S5 and S6) output from the motor control unit 30, and a W-phase signal is output from a node N3 between the switching elements 21-3 and 22-3 connected in series.

As described above, the inverter unit 20 has a plurality of sets (for example, 3 sets) of switching elements 21 and 22 connected in series, and generates multiphase (for example, three-phase) ac signals (U-phase signal, V-phase signal, W-phase signal) having mutually different phases corresponding to the plurality of sets of switching elements 21 and 22, respectively.

The current detection device 10 detects a current flowing through the inverter section 20. The current detection device 10 detects, for example, an output current of a drive signal (ac signal) generated by the inverter unit 20 for each phase. The current detection device 10 detects an input current (input current of the inverter unit 20) from the dc power supply 2.

The current detection device 10 includes rogowski coils 11-1 to 11-3, rogowski coils 12-1 to 12-3, and a current detection section 13.

In the present embodiment, the rogowski coils 11-1 to 11-3 are air-core coils for detecting the current flowing through the switching elements 21 (21-1 to 21-3), and are described as the rogowski coils 11 when the rogowski coil (first rogowski coil) for any switching element 21 provided in the current detecting apparatus 10 is shown or when no distinction is made.

The rogowski coils 12-1 to 12-3 are air-core coils for detecting the current flowing through the switching elements 22 (22-1 to 22-3), and are described as the rogowski coils 12 when the rogowski coil (second rogowski coil) for any switching element 222 provided in the current detecting apparatus 10 is shown or when no distinction is made.

The rogowski coil 11 (first rogowski coil) detects a current flowing at the switching element 21. For example, the rogowski coil 11-1 is disposed on a signal line connecting the drain terminal of the switching element 21-1 and the power supply line L1, and detects a current flowing through the switching element 21-1. The rogowski coil 11-2 is disposed on a signal line connecting a drain terminal of the switching element 21-2 and the power supply line L1, and detects a current flowing through the switching element 21-2. The rogowski coil 11-3 is disposed on a signal line connecting a drain terminal of the switching element 21-3 and the power supply line L1 for detecting a current flowing through the switching element 21-3.

For example, the rogowski coil 12-1 is disposed on a signal line connecting the source terminal of the switching element 22-1 and the ground line L2, and detects a current flowing through the switching element 22-1. The rogowski coil 12-2 is disposed on a signal line connecting a source terminal of the switching element 22-2 and the ground line L2, and detects a current flowing through the switching element 22-2. The rogowski coil 12-3 is disposed on a signal line connecting a source terminal of the switching element 22-3 and the ground line L2, and detects a current flowing through the switching element 22-3.

As described above, the current detection device 10 includes the rogowski coil 11 and the rogowski coil 12 corresponding to the plural sets of the switching elements 21 and 22, respectively. That is, the plurality of (three) rogowski coils 11 are respectively in one-to-one correspondence with the switching elements 21, and detect the current flowing through the switching elements 21. The plurality of (three) the rogue coils 12 correspond to the switching elements 22 one to one, respectively, and detect the current flowing through the switching elements 22.

The current detection unit 13 performs a process of detecting a current flowing through the inverter unit 20. For example, the current detection unit 13 generates a synthesized signal in which the first detection signal integrated with the output of the rogowski coil 11 and the second detection signal integrated with the output of the rogowski coil 12 are added, and detects the output current of the ac signal based on the synthesized signal. The current detection section 13 generates a composite signal corresponding to each of the plurality of groups, and detects an output current of an alternating current signal different in each phase based on the composite signal. Specifically, the current detection unit 13 outputs the generated synthesized signal as a current signal indicating an output current of the drive signal (U-phase signal, V-phase signal, W-phase signal) of the motor 3.

The structure of the current detecting section 13 will be described in detail later with reference to fig. 2.

The motor control unit 30 is, for example, a processor including CPU (CentralProcessingUnit), and controls the current detection device 10 and the motor control device 1 in a unified manner. The motor control unit 30 executes various processes by causing the CPU to execute programs stored in a storage unit, not shown, for example.

The motor control unit 30 obtains a current signal indicating an output current of the drive signal (U-phase signal, V-phase signal, W-phase signal) output from the current detection unit 13, for example, via an ADC, and detects a current value of the current signal. The motor control unit 30 controls the switching of the switching elements 21 and 22 based on the current values of the detected drive signals (U-phase signal, V-phase signal, W-phase signal).

The motor control unit 30 includes a timing generation unit 31.

The timing generation unit 31 generates reset timings of the integrating circuits 41 and 42 of the current detection unit 13 described later, and supplies the timings to the current detection unit 13. The structure of the timing generation section 31 will be described in detail later with reference to fig. 2.

Next, the structure of the above-described current detecting portion 13 will be described in detail with reference to fig. 2.

Fig. 2 is a block diagram showing an example of the current detection unit 13 according to the present embodiment.

As shown in fig. 2, the current detection unit 13 includes integrating circuits 41-1 to 41-3 and integrating circuits 42-1 to 42-3, a detection processing unit 131, a first reset output unit 132, and a second reset output unit 133.

In the present embodiment, the integrating circuits 41-1 to 41-3 have the same configuration, and when an arbitrary integrating circuit corresponding to the rogowski coil 11 is shown, the integrating circuit 41 will be described. In the present embodiment, the integration circuit 41 is an example of a first integration circuit.

In the present embodiment, the integrator circuits 42-1 to 42-3 have the same configuration, and when any integrator circuit corresponding to the rogowski coil 12 is shown, the integrator circuit 42 will be described. In the present embodiment, the integration circuit 42 is an example of a second integration circuit.

The plurality of (three) integrating circuits 41 are respectively in one-to-one correspondence with the rogowski coils 11, and have a reset function, integrate the outputs of the rogowski coils 11, and output first detection signals (detection signals UH, VH, WH). Here, the detection signal UH, the detection signal VH, and the detection signal WH correspond to the first detection signal.

The plurality of (three) integrating circuits 42 are respectively in one-to-one correspondence with the rogowski coil 12 and have a reset function, integrate the output of the rogowski coil 12, and output the second detection signals (detection signal UL, detection signal VL, detection signal WL). Here, the detection signal UL, the detection signal VL, and the detection signal WL correspond to the second detection signal.

Specifically, the integrating circuit 41-1 is connected to the rogowski coil 11-1, and outputs a detection signal UH integrating the output of the rogowski coil 11-1. The integrating circuit 42-1 is connected to the rogowski coil 12-1, and outputs a detection signal UL integrating the output of the rogowski coil 12-1.

The integrating circuit 41-2 is connected to the rogowski coil 11-2, and outputs a detection signal VH obtained by integrating the output of the rogowski coil 11-2. The integrating circuit 42-2 is connected to the rogowski coil 12-2, and outputs a detection signal VL integrating the output of the rogowski coil 12-2.

The integrating circuit 41-3 is connected to the rogowski coil 11-3, and outputs a detection signal WH obtained by integrating the output of the rogowski coil 11-3. The integrating circuit 42-3 is connected to the rogowski coil 12-3 to output a detection signal WL integrating the output of the rogowski coil 12-3.

The integrating circuits 41 (41-1 to 41-3) and 42 (42-1 to 42-3) have a reset function, and integrate the outputs of the rogowski coils (11, 12). Here, the detailed configuration of the integrating circuit 41 (42) will be described with reference to fig. 3.

Fig. 3 is a circuit diagram showing an example of the integrating circuit 41 (42) according to the present embodiment.

As shown in fig. 3, the integrating circuit 41 (42) includes a resistor 43, an operational amplifier 44, a capacitor 45, and a reset switch 46.

The resistor 43 is connected between one end of the rogowski coil 11 (12) and the inverting input terminal of the operational amplifier 44. The capacitor 45 is connected between the inverting input terminal (node N5) of the operational amplifier 44 and the output terminal (node N5) of the operational amplifier 44.

The operational amplifier 44 functions as an integrating circuit by connecting the resistor 43 and the capacitor 45. An inverting input terminal of the operational amplifier 44 is connected to one end of the rogowski coil 11 (12) via a resistor 43, and the other end thereof is connected to a non-inverting input. The operational amplifier 44 outputs an output signal (OUT) obtained by integrating the output of the rogowski coil 11 (12) with the output of the rogowski coil 11 (12) as an input signal (IN).

The reset switch 46 is connected in parallel with the capacitor 45 between the inverting input terminal (node N4) of the operational amplifier 44 and the output terminal (node N5) of the operational amplifier 44. The reset switch 46 is a switch that resets the output potential of the integrating circuit 41 (42), and for example, controls the on state according to a pulse signal based on the control signal S. When resetting the integrating circuit 41 (42), the reset switch 46 is controlled to be in an on state (on state).

The control signal S of the integrating circuit 41 is supplied with a reset signal RST1 (first reset signal) output from the first reset output section 132. The reset signal RST2 (second reset signal) for output from the second reset output section 133 is supplied to the control signal S of the integrating circuit 42.

When the reset switch 46 is controlled to a non-conducting state (off state) according to the control signal S, the integrating circuit 41 (42) functions as an integrating circuit.

Returning to fig. 2, the detection processing unit 131 detects the current flowing through the inverter unit 20 based on the first detection signal (detection signal UH, detection signal VH, detection signal WH) and the second detection signal (detection signal UL, detection signal VL, detection signal WL).

The adders 50-1 to 50-3 have the same configuration, and are described as the adder 50 in the case where any adder included in the detection processing unit 131 is shown or in the case where no distinction is made.

Adder 50 is a two-input analog adder, and is implemented, for example, by an adder circuit using an operational amplifier. The adder 50 outputs a synthesized signal obtained by adding the two input signals.

For example, the detection signal UH and the detection signal UL are input to the adder 50-1 as two input signals, and the adder 50-1 outputs a combined signal that adds the detection signal UH and the detection signal UL as the U-phase current signal UC.

Adder 50-2 receives detection signal VH and detection signal VL as two input signals, and adder 50-2 outputs a synthesized signal obtained by adding detection signal VH and detection signal VL as V-phase current signal VC.

The detection signal WH and the detection signal WL are input as two input signals to the adder 50-3, and the adder 50-3 outputs a synthesized signal in which the detection signal WH and the detection signal WL are added as a W-phase current signal WC.

As described above, the detection processing unit 131 generates the composite signals (U-phase current signal UC, V-phase current signal VC, W-phase current signal WC) corresponding to the plurality of groups of the switching elements 21 and 22, and detects the output current of the drive signal (ac signal) having different phases from the composite signals. That is, the detection processing unit 131 outputs the generated synthesized signals (U-phase current signal UC, V-phase current signal VC, W-phase current signal WC) as current signals indicating the output currents of the respective drive signals (U-phase signal, V-phase signal, W-phase signal).

During a first period TRrst1 in which all the switching elements 21 are in the off state, the first reset output section 132 outputs a reset signal RST1 that resets a plurality of (e.g., three) integrating circuits 41. That is, the first reset output unit 132 sets a period in which all of the switching elements 21-1 to 21-3 are turned off as a first period TRrst1, and outputs the reset signal RST1 in the first period TRrst 1. The first reset output unit 132 outputs the reset signal RST1 so that all of the plurality of (for example, three) integrating circuits 41 are in the reset state during a part (for example, a central portion) of the first period TRrst 1.

The first reset output unit 132 is, for example, a conversion circuit that converts the logic signal output from the timing generation unit 31 of the motor control unit 30 into the signal for controlling the reset switch 46. The first reset output unit 132 outputs the reset signal RST1 according to the reset timing of the integrating circuits 41 generated by the timing generation unit 31, so that all the plurality (for example, three) of integrating circuits 41 are in the reset state. That is, the first reset output section 132 outputs the reset signal RST1 to the integrating circuits 41-1 to 41-3 based on the reset timing signal RT1 indicating the reset timing.

During the second period TRrst2 in which all the switching elements 22 are in the off state, the second reset output section 133 outputs the reset signal RST2 that resets the plurality of (e.g., three) integrating circuits 42. That is, the second reset output portion 133 sets the period in which all the switching elements 22-1 to 22-3 are turned off to the second period TRrst2, and outputs the reset signal RST2 in the second period TRrst 2. The second reset output section 133 outputs the reset signal RST2 during a part (for example, the central portion) of the second period TRrst2 so that all of the plurality of (for example, three) integrating circuits 42 are in the reset state.

The second reset output unit 133 is, for example, a conversion circuit that converts the logic signal output from the timing generation unit 31 of the motor control unit 30 into a signal for controlling the reset switch 46. The second reset output unit 133 outputs the reset signal RST2 so that all of the plurality of (for example, three) integrating circuits 42 are in the reset state, based on the reset timing of the integrating circuits 42 generated by the timing generating unit 31. That is, the second reset output unit 133 outputs the reset signal RST2 to the integrating circuits 41-1 to 41-3 based on the reset timing signal RT2 indicating the reset timing.

The timing generation section 31 generates a reset timing of the integration circuit 41 and a reset timing of the integration circuit 42. The timing generation unit 31 outputs the reset timing signal RT1 to the first reset output unit 132, for example, with the timing of the central segment of the first period TRrst1 in which all of the high-arm switching elements 21-1 to 21-3 are in the off state as the reset timing of the integration circuit 41.

The timing generation unit 31 outputs the reset timing signal RT2 to the second reset output unit 133, for example, with the timing of the central segment of the second period TRrst2 in which all of the lower arm switching elements 22-1 to 22-3 are in the off state as the reset timing of the integration circuit 42.

Next, the operation of the current detection device 10 according to the present embodiment will be described with reference to the drawings.

First, the generation process of the current signal by the detection processing section 131 of the current detection device 10 will be described with reference to fig. 4.

Fig. 4 is a diagram showing the generation processing of the synthesized signal in the present embodiment.

In fig. 4, a waveform W1 represents a voltage waveform of the detection signal UH, and a waveform W2 represents a voltage waveform of the detection signal UL. Waveform W3 represents the voltage waveform of U-phase current signal UC.

As shown in fig. 4, the integrating circuit 41-1 of the detection processing unit 131 integrates the output of the rogowski coil 11-1, and outputs a detection signal UH shown by a waveform W1.

The respective timings from the time Tr11 to the time Tr15 show the reset timing of the integrating circuit 41 generated by the timing generation section 31, and at this timing, the first reset output section 132 outputs the reset signal RST1 to the integrating circuit 41.

The detection processing unit 131 integrates the output of the rogowski coil 12-1 by the integrating circuit 42-1, and outputs a detection signal UL shown by a waveform W2.

At each of the timings Tr21 to Tr25, the reset timing of the integrating circuit 42 generated by the timing generation unit 31 is shown, and at this timing, the second reset output unit 133 outputs the reset signal RST2 to the integrating circuit 42.

Next, the adder 50-1 outputs the U-phase current signal UC as shown by the waveform W3 as a synthesized signal obtained by adding the detection signal UH as shown by the waveform W1 and the detection signal UL as shown by the waveform W2. The U-phase current signal UC is a signal obtained by converting the output current (positive current) of the U-phase drive signal into a voltage.

The detection processing unit 131 also generates and outputs the V-phase current signal VC and the W-phase current signal WC in the same manner as the U-phase current signal UC. That is, the detection processing unit 131 generates the U-phase current signal UC, the V-phase current signal VC, and the W-phase current signal WC according to the following equations (1) to (3).

U-phase current signal uc=detection signal uh+detection signal UL … (1)

V-phase current signal vc=detection signal vh+detection signal VL … (2)

W-phase current signal wc=detection signal wh+detection signal WL … (3)

The motor control unit 30 obtains the U-phase current signal UC, the V-phase current signal VC, and the W-phase current signal WC generated by the detection processing unit 131 via an ADC not shown, and detects zero-crossing points of output currents of the respective phases. The motor control unit 30 performs switching control of the switching elements 21-1 to 21-3 and the switching elements 22-1 to 22-3 based on the detected zero-crossing points.

Next, a current detection method of the current detection device 10 according to the present embodiment will be described with reference to fig. 5 to 7.

Fig. 5 is a flowchart showing an example of the output current detection process of the current detection device 10 according to the present embodiment.

As shown in fig. 5, when the current detection device 10 detects the output current (positive current) of each phase of the inverter section 20, first, the output of the rogowski coil 11 on the upper side is integrated to generate a first detection signal (step S101). For example, in the current detecting unit 13 of the current detecting device 10, the integrating circuit 41-1 integrates the output of the rogowski coil 11-1 to generate the detection signal UH, and the integrating circuit 41-2 integrates the output of the rogowski coil 11-2 to generate the detection signal VH. The integrating circuit 41-3 integrates the output of the rogowski coil 11-3 to generate a detection signal WH.

Next, the current detection device 10 integrates the output of the rogowski coil 12 on the lower side to generate a second detection signal (step S102). For example, in the current detecting unit 13, the integrating circuit 42-1 integrates the output of the rogowski coil 12-1 to generate the detection signal UL, and the integrating circuit 42-2 integrates the output of the rogowski coil 12-2 to generate the detection signal VL. The integrating circuit 42-3 integrates the output of the rogowski coil 12-3 to generate a detection signal WL.

Note that the current detecting section 13 may execute the processing of step S101 and the processing of step S102 in reverse order, or may execute them in parallel using the structure shown in fig. 2, for example.

Next, the current detection device 10 adds the first detection signal and the second detection signal to generate a composite signal (step S103). For example, in the detection processor 131 of the current detector 13, the adder 50-1 adds the detection signal UH and the detection signal UL to generate the U-phase current signal UC as a synthesized signal. Adder 50-2 adds detection signal VH and detection signal VL to generate V-phase current signal VC as a synthesized signal. Adder 50-3 adds detection signal WH and detection signal WL to generate W-phase current signal WC as a synthesized signal.

Next, the current detection device 10 detects an output current based on the synthesized signal (step S104). For example, the detection processing unit 131 of the current detection unit 13 outputs the U-phase current signal UC, the V-phase current signal VC, and the W-phase current signal WC to the motor control unit 30 as current signals indicating the output currents of the respective phases. After the processing of step S104, the current detection device 10 ends the detection processing of the output current.

Next, a process of generating a reset signal of the integrating circuit 41 (42) according to the present embodiment will be described with reference to fig. 6 to 9.

Fig. 6 is a diagram showing an example of the generation process of the reset signal RST1 of the first integrating circuit (integrating circuit 41) of the present embodiment.

In fig. 6, a waveform W4-1 shows a waveform of the U-phase control signal S1-1 of the switching element 21, and a waveform W5-1 shows a waveform of the V-phase control signal S3-1 of the switching element 21. The waveform W6 represents the waveform of the W-phase control signal S5 of the switching element 21, and the waveform W7 represents the waveform of the reset signal RST 1. The horizontal axis represents time.

The timing generation section 31 generates a first period TRrst1 in which all the switching elements 21 are in an off state from the U-phase control signal S1 (waveform W4), the V-phase control signal S3 (waveform W5), and the W-phase control signal S5 (waveform W6) in the upper arm switching elements 21, and generates a reset timing in a period in the center of the first period TRrst 1. The first reset output section 132 outputs the reset signal RST1 shown by the waveform W7 to the integrating circuits 41 (41-1 to 41-3) according to the reset timing generated by the timing generation section 31.

Fig. 7 is an example flowchart showing timing generation of the reset signal RST1 of the first integrating circuit (integrating circuit 41) of the present embodiment.

As shown in fig. 7, the timing generation unit 31 first determines whether all of the switching elements 21 (21-1 to 21-3) are in the off state (step S201). When all of the switching elements 21 (21-1 to 21-3) are in the off state (YES in step S202), the timing generation unit 31 advances the process to step S202. When any one of the switching elements 21 (21-1 to 21-3) is in the on state (step S201: NO), the timing generation unit 31 returns the process to step S201.

In step S202, the timing generation unit 31 generates the reset timing of the integration circuits 41 (41-1 to 41-3). The timing generation unit 31 generates a reset timing signal by resetting the integrating circuits 41 (41-1 to 41-3) in the central portion of the first period TRrst1 when all the switching elements 21 (21-1 to 21-3) are in the off state, for example

Next, the first reset output section 132 outputs the reset signal RST1 according to the reset timing (step S203). The first reset output section 132 converts the reset timing signal RT1 into a signal for controlling the reset switch 46 of the integration circuit 41, and outputs a reset signal RST1. After the process of step S203, the timing generation unit 31 returns the process to step S201.

Fig. 8 is a diagram showing an example of the generation process of the reset signal RST2 of the second integrating circuit (integrating circuit 42) of the present embodiment.

In fig. 8, a waveform W8 represents the waveform of the U-phase control signal S2 of the switching element 22, and a waveform W9 represents the waveform of the V-phase control signal S4 of the switching element 22. The waveform W10 represents the waveform of the W-phase control signal S6 of the switching element 22, and the waveform W11 represents the waveform of the reset signal RST 2. The horizontal axis represents time.

The timing generation section 31 generates a second period TRrst2 in which all the switching elements 22 are in the off state, based on the U-phase control signal S2 (waveform W8), the V-phase control signal S4 (waveform W9), and the W-phase control signal S6 (waveform W10) in the lower arm switching elements 22, and generates a reset timing during the center period of the second period TRrst 2. The second reset output unit 133 outputs the reset signal RST2 shown by the waveform W11 to the integrating circuits 42 (42-1 to 42-3) according to the reset timing generated by the timing generation unit 31.

Fig. 9 is a flowchart showing an example of timing generation of the reset signal RST2 of the second integrating circuit (integrating circuit 42) according to the present embodiment.

As shown in fig. 9, the timing generation unit 31 first determines whether all of the switching elements 22 (22-1 to 22-3) are in the off state (step S211). In the case where all the switching elements 22 (22-1 to 22-3) are in the off state (step S212: YES), the timing generation section 31 advances the process to step S212. When any one of the switching elements 22 (22-1 to 22-3) is in the on state (step S211: NO), the timing generation unit 31 returns the process to step S211.

In step S212, the timing generation unit 31 generates the reset timing of the integration circuits 42 (42-1 to 42-3). The timing generation unit 31 outputs the reset timing signal RT2 so that the integration circuits 42 (42-1 to 42-3) are reset at the center portion of TRrst2 during the second period in which all the switching elements 22 (22-1 to 22-3) are in the off state, for example.

Next, the second reset output section 133 outputs the reset signal RST2 based on the reset timing (step S213). The second reset output section 133 converts the reset timing signal RT2 into a signal for controlling the reset switch 46 of the integration circuit 42, thereby outputting a reset signal RST2. After the processing of step S213, the timing generation section 31 returns to step S211.

As described above, the current detection device 10 of the present embodiment is for detecting a current flowing through the inverter section 20, and includes: a plurality of rogowski coils 11 (first rogowski coil), a plurality of rogowski coils 12 (second rogowski coil), a plurality of integrating circuits 41 (first integrating circuits), a plurality of integrating circuits 42 (second integrating circuits), a detection processing section 131, a first reset output section 132, and a second reset output section 133. The inverter section 20 has a plurality of sets (e.g., three) of switching elements 21 (first switching elements) and 22 (second switching elements) connected in series for generating ac signals (U-phase signals, W-phase signals) of a plurality of phases (e.g., 3 phases). The plurality of rogowski coils 11 are respectively in one-to-one correspondence with the switching elements 21, and detect a current flowing through the switching elements 21. The plurality of rogowski coils 12 are respectively in one-to-one correspondence with the switching elements 22, and detect a current flowing through the switching elements 22. The integrating circuits 41 are respectively in one-to-one correspondence with the rogowski coils 11, and have a reset function for integrating the output of the rogowski coils 11 and outputting first detection signals (detection signals UH, VH, WH). The integrating circuits 42 are respectively in one-to-one correspondence with the rogowski coils 12, and have a reset function for integrating the outputs of the rogowski coils 12 and outputting second detection signals (detection signals UL, VL, WL). The detection processing section 131 detects the current flowing through the inverter section 20 based on the first detection signal and the second detection signal. The first reset output unit 132 outputs a reset signal RST1 (first reset signal) for resetting the plurality of integrating circuits 41 in a first period TRrst1 in which all the switching elements 21 are in an off state (non-on state). The second reset output section 133 outputs a reset signal RST2 (second reset signal) for resetting the plurality of integrating circuits 42 in the second period TRRST2 in which all the switching elements 22 are in the off state (non-on state).

As described above, the current detection device 10 of the present embodiment outputs the reset signal RST1 for resetting the plurality of integrating circuits 41 corresponding to the plurality of rogowski coils 11 in the first period TRrst1 in which all the switching elements 21 are in the off state (non-on state). The current detection device 10 of the present embodiment outputs the reset signal RST2 for resetting the plurality of integrating circuits 42 corresponding to the plurality of rogowski coils 12 during the second period TRrst2 in which all the switching elements 22 are in the off state (non-on state). Therefore, the current detection device 10 according to the present embodiment can share the reset signals for the plurality of integrating circuits 41, and can share the reset signals for the plurality of integrating circuits 42. Since the reset signal can be shared between two systems depending on the above, the current detection device 10 of the present embodiment can be simplified in structure.

In the present embodiment, the first reset output section 132 outputs the reset signal RST1 to put all the integration circuits 41 in the reset state during a part of the first period TRrst 1. The second reset output section 133 outputs the reset signal RST2 in a partial period in the second period TRrst2 so that all of the plurality of integrating circuits 42 become a reset state.

By so doing, since the current detection apparatus 10 of the present embodiment outputs the reset signal RST1 and the reset signal RST2 in a part of the period (for example, the center period) of the first period TRrst1 and a part of the period (for example, the center period) of the second period TRrst2, the plurality of integration circuits 41 and the plurality of integration circuits 42 can be reliably and appropriately reset (initialized) with the common reset signal. Therefore, the current detection device 10 of the present embodiment can improve the detection accuracy.

Since the current detection device 10 of the present embodiment includes the timing generation section 31, it generates the reset timing of the integration circuit 41 and the reset timing of the integration circuit 42. The first reset output section 132 outputs the reset signal RST1 according to the reset timing of the integrating circuits 41 generated by the timing generating section 31 so that all of the plurality of integrating circuits 41 are in a reset state. The second reset output unit 133 outputs the reset signal RST2 according to the reset timing of the integrating circuits 42 generated by the timing generation unit 31, so that all of the plurality of integrating circuits 42 are in the reset state.

As described above, the current detection device 10 according to the present embodiment includes the timing generation unit 31, and by generating the reset timing, the plurality of integration circuits 41 and the plurality of integration circuits 42 can be appropriately reset (initialized) by a simple configuration.

The current detection device 10 of the present embodiment includes a motor control unit 30 that controls switching of the switching element 21 and the switching element 22. The motor control unit 30 includes a timing generation unit 31.

As described above, since the current detection device 10 according to the present embodiment can generate the reset timing by the software processing of the CPU of the motor control unit 30, the plurality of integrating circuits 41 and the plurality of integrating circuits 42 can be reset (initialized) appropriately by a simpler configuration.

The current detection method according to the present embodiment includes a plurality of sets of switching elements 21 and 22 connected in series, and is a current detection method for generating ac signals of a plurality of phases and detecting a current flowing through an inverter unit 20, and includes: a first integrating step, a second integrating step, a detecting processing step, a first reset output step, and a second reset output step. In the first integration step, the plurality of (e.g., three) integration circuits 41 integrate the outputs of the rogowski coil 11, which detects the currents flowing through the switching elements 21 corresponding to the plurality of phases (e.g., 3 phases), respectively, and output the first detection signal. In the second integration step, the plurality of integration circuits 42 integrate the outputs of the rogowski coil 12, which detect the currents flowing through the switching elements 22 corresponding to each of the plurality of phases, respectively, and output a second detection signal. In the detection processing step, the detection processor 131 detects the current flowing through the inverter section 20 based on the first detection signal and the second detection signal. In the first reset output step, the first reset output section 32 outputs the reset signal RST1 (first reset signal) for resetting the plurality of integrating circuits 41 during the first period TRrst1 in which all the switching elements 21 are in the off state (non-on state). In the second reset output step, the second reset output section 33 outputs the reset signal RST2 (second reset signal) that resets the plurality of integrating circuits 42 during the second period TRRST2 in which all the switching elements 22 are in the off state (non-on state).

In this way, the current detection method according to the present embodiment has the same effects as those of the current detection device 10 described above, and therefore, the arrangement of the current detection device 10 can be simplified.

The present invention is not limited to the above-described embodiments, and can be modified within the scope not departing from the spirit of the present invention.

For example, in the above embodiments, the example in which the current detection device 10 is applied to the current detection for controlling the driving of the motor 3 included in the motor control device 1 has been described, but the present invention is not limited thereto. For example, the current detection device 10 may be applied to current detection using an inverter unit other than the motor control device 1 such as a power supply device.

In the above embodiment, the example in which the motor control unit 30 includes the timing generation unit 31 has been described, but the present invention is not limited to this, and the timing generation unit 31 may be implemented by a logic circuit while the timing generation unit 31 is provided outside the motor control unit 30.

Fig. 10 is a diagram of a modification of the timing generation unit 31 according to the present embodiment. The timing generator 31a shown in fig. 10 shows a modification realized by a logic circuit.

As shown in fig. 10, the timing generation section 31a includes NOR circuits (311-1, 311-2), delay circuits (312-1, 312-2, 313-1, 313-2), AND inverting circuits (314-1, 314-2), AND circuits (315-1, 315-2).

The NOR circuit 311-1 and NOR circuit 311-2 are three-input negation or circuits. The NOR circuit 311-1 outputs NOR output signals of the control signal S1 (waveform W4) of the U phase, the control signal S3 (waveform W5) of the V phase, and the control signal S5 (waveform W6) of the W phase in the switching element 21.

Delay circuit 312-1 and delay circuit 312-2 are delay circuits. The delay circuit 312-1 delays the output of the NOR circuit 311-1 by a predetermined period, AND outputs the delayed output to the delay circuit 313-1 AND the AND circuit 315-1 in the subsequent stage.

The delay circuit 312-2 delays the output of the NOR circuit 311-2 by a predetermined period, AND outputs the delayed output to the delay circuit 313-2 AND the AND circuit 315-2 of the next stage.

The delay circuit 313-1 and the delay circuit 313-2 are delay circuits. The delay circuit 313-1 delays the output of the delay circuit 312-1 by a predetermined period of time and outputs the delayed output to the inverter circuit 314-1. The delay circuit 313-2 delays the output of the delay circuit 312-2 by a predetermined period and outputs the delayed output to the inverter circuit 314-2.

The inverter circuit 314-1 and the inverter circuit 314-2 are logic inverter circuits. The inverting circuit 314-1 logically inverts the output of the delay circuit 313-1 AND outputs to the AND circuit 315-1. The inverting circuit 314-2 logically inverts the output of the delay circuit 313-2 AND outputs to the AND circuit 315-2.

The AND circuit 315-1 AND the AND circuit 315-2 are logical AND circuits. The AND circuit 315-1 outputs an output signal obtained by logically integrating the output of the delay circuit 312-1 AND the output of the inverting circuit 314-1 as a reset timing signal RT 1. The AND circuit 315-2 outputs an output signal obtained by logically integrating the output of the delay circuit 312-2 AND the inverting circuit 314-2 as a reset timing signal RT2.

In FIG. 10, a reset timing signal RT1 of an integration circuit 41 is generated by a logic circuit composed of a NOR circuit 311-1, delay circuits (312-1, 313-1), an inverting circuit 314-1, AND an AND circuit 315-1

The reset timing signal RT2 of the integration circuit 42 is generated by a logic circuit constituted by the NOR circuit 311-2, the delay circuits (312-2, 313-2), the inverting circuit 314-2, AND the AND circuit 315-2.

As described above, in the present embodiment, the timing generation unit 31a includes a logic circuit that generates the reset timing of the integration circuit 41 based on the control signals (S1, S3, S5) of the switching elements 21 corresponding to the plurality of phases, and generates the reset timing of the integration circuit 42 based on the control signals (S2, S4, S6) of the switching elements 22 corresponding to the plurality of phases.

By so doing, the current detection device 10 according to the present embodiment can appropriately reset (initialize) the plurality of integrating circuits 41 and the plurality of integrating circuits 42 by the logic circuit having a simple configuration.

In the above-described embodiment, the example in which the current detection unit 13 (the detection processing unit 131) outputs a signal for converting a current waveform into a voltage and the motor control unit 30 obtains a current value via an ADC (not shown) has been described, but the present invention is not limited thereto. For example, the current detector 13 (the detection processor 131) may also include an ADC. That is, the current detection unit 13 (detection processing unit 131) may have a part of the functions of the motor control unit 30. The motor control unit 30 may have a part or all of the functions of the current detection unit 13 (the detection processing unit 131).

In the above-described embodiment, the example in which the current detection device 10 detects the current in accordance with the three-phase ac signal has been described, but the present invention is not limited to this, and the present invention is applicable to applications in which the number of phases is less than three or four or more.

Each structure of the motor control device 1 and the current detection device 10 has a computer system inside. The processes in the respective configurations of the motor control device 1 and the current detection device 10 may be performed by recording a program for realizing the functions of the respective configurations of the motor control device 1 and the current detection device 10 in a computer-readable recording medium, and by causing a computer system to read and execute the program recorded in the recording medium. Here, "causing the computer system to read in and execute the program recorded in the recording medium" includes installing the program in the computer system. As used herein, a "computer system" includes hardware such as an OS and peripheral devices.

In addition, the "computer system" may include a plurality of computer devices connected via a network including a communication line such as the internet, WAN, LAN, dedicated line, or the like. The term "computer-readable recording medium" refers to a removable medium such as a floppy disk, a magneto-optical disk, a ROM, or a CD-ROM, and a storage device such as a hard disk incorporated in a computer system. As described above, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

[ symbolic description ]

1 motor control device

2 DC power supply

3 motor

4 smoothing capacitor

10 current detection device

11. 11-1, 11-2, 11-3, 12-1, 12-2, 12-3 rogowski coil

13 current detection unit

20 inverter unit

21. 21-1, 21-2, 21-3, 22-1, 22-2, 22-3 switching element

30 motor control part

31. 31a timing generation unit

41. 41-1, 41-2, 41-3, 42-1, 42-2, 42-3 integrating circuits

43 resistor

44 operational amplifier

45 capacitor

46 reset switch

50. 50-1, 50-2, 50-3 adder

131 detection processing part

132 first reset output section

133 second reset output section

311-1, 311-2NOR circuit

312-1, 312-2, 313-1, 313-2 delay circuit

314-1, 314-2 inverting circuits

315-1, 315-2AND circuits.

Claims

1. A current detection device having a plurality of sets of first switching elements and second switching elements connected in series for detecting a current flowing through an inverter section that generates ac signals of a plurality of phases, comprising:

a plurality of first rogowski coils, which are respectively in one-to-one correspondence with the first switching elements, for detecting a current flowing through the first switching elements;

a plurality of second rogowski coils, respectively corresponding to the second switching elements one by one, for detecting a current flowing through the second switching elements;

the first integrating circuits are respectively in one-to-one correspondence with the first rogowski coils and have a reset function and are used for integrating the output of the first rogowski coils and then outputting a first detection signal;

the second integrating circuits are respectively in one-to-one correspondence with the second rogowski coils and have a reset function and are used for integrating the output of the second rogowski coils and outputting a second detection signal;

a detection processing unit configured to detect a current flowing through the inverter unit based on the first detection signal and the second detection signal;

a first reset output unit that outputs a first reset signal for resetting the plurality of first integrated circuits during a first period in which all the first switching elements are in a non-conductive state; and

And a second reset output unit configured to output a second reset signal for resetting the plurality of second integrated circuits during a second period in which all the second switching elements are in a non-conductive state.

2. The current detection device according to claim 1, wherein:

wherein the first reset output section outputs the first reset signal so that all of the plurality of first integrating circuits are in a reset state during a part of the first period,

the second reset output section outputs the second reset signal during a part of the second period so that all of the plurality of second integration circuits are in a reset state.

3. The current detection apparatus according to claim 1 or 2, characterized by comprising:

a timing generation section for generating a reset timing of the first integrating circuit and a reset timing of the second integrating circuit,

the first reset output section outputs the first reset signal so that all of the plurality of first integrating circuits are in a reset state according to the reset timing of the first integrating circuit generated by the timing generating section,

the second reset output section outputs the second reset signal so that all of the plurality of second integration circuits are in a reset state, in accordance with the reset timing of the second integration circuit generated by the timing generation section.

4. A current detecting device according to claim 3, comprising:

a control section for controlling switching of the first switching element and the second switching element,

the control section includes the timing generation section.

5. A current detection apparatus according to claim 3, wherein:

the timing generation section includes a logic circuit that generates a reset timing of the first integration circuit based on a control signal of the first switching element corresponding to the plurality of phases, and generates a reset timing of the second integration circuit based on a control signal of the second switching element corresponding to the plurality of phases.

6. A current detection method having a plurality of sets of first switching elements and second switching elements connected in series for detecting a current flowing through an inverter section that generates ac signals of a plurality of phases, comprising:

a first integration step of integrating outputs of first rogowski coils, each of which detects a current flowing through the first switching element corresponding to each of the plurality of phases, by a plurality of first integration circuits, and outputting a first detection signal;

a second integration step of integrating outputs of the first rogowski coils, each of which detects a current flowing through the second switching element corresponding to each of the plurality of phases, and outputting a second detection signal;

A detection processing step of detecting a current flowing through the inverter unit based on the first detection signal and the second detection signal;

a first reset step of outputting a first reset signal for resetting the plurality of first integrated circuits in a first period in which all the first switching elements are in a non-conductive state; and

and a second reset step of outputting a second reset signal for resetting the plurality of second integrated circuits in a second period in which all the second switching elements are in a non-conductive state.