CN117674773A - RC relaxation oscillator and working method thereof - Google Patents

Abstract

The invention provides an RC relaxation oscillator, comprising: the capacitor charging and discharging module is used for controlling the charging and discharging of the capacitor according to the output signal to generate capacitor voltage; the reference generation module is used for sequentially providing an original high voltage and an original low voltage as reference voltages in a first oscillation period and sequentially providing a new high voltage and an original low voltage as reference voltages in a second and subsequent oscillation periods; wherein the newly set high voltage is related to the maximum value of the capacitor voltage and is smaller than the original high voltage; the comparison module is connected with the output ends of the capacitor charging and discharging module and the reference generating module and is used for comparing the capacitor voltage with the reference voltage and generating an output signal according to the comparison result. The RC relaxation oscillator provided by the invention solves the problem that the output frequency of the traditional RC relaxation oscillator has poor temperature characteristics.

Description

RC relaxation oscillator and working method thereof

Technical Field

The invention relates to the field of integrated circuit design, in particular to an RC relaxation oscillator and a working method thereof.

Background

The oscillator is a circuit which can generate periodic variation only by supplying power with a direct current power supply without external signal stimulation; there are a wide range of important applications within integrated circuits, such as in counting devices to act as counters, in clock generation circuits to provide accurate clock signals for chips, etc.

Depending on the topology of the circuit, the devices involved and the oscillation principle, oscillators are largely classified into crystal oscillators, LC oscillators, ring oscillators and RC relaxation oscillators. Compared with other types of oscillators, the RC relaxation oscillator has the advantages of smaller area, simple structure, easy integration and the like, and is expected to be a hot spot of current and future researches.

The output frequency of the traditional RC relaxation oscillator has a great correlation with temperature, and the main reasons are that a resistor influenced by temperature change and loop delay influenced by temperature exist in the traditional RC relaxation oscillator, wherein the loop delay is mainly caused by offset and delay of a comparator; these non-ideal factors cause a large temperature drift in the output frequency of the oscillator, and a relatively stable and sufficient accuracy cannot be achieved when the temperature changes, which greatly limits the application range of the RC relaxation oscillator.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an RC relaxation oscillator and an operating method thereof, which are used for solving the problem that the output frequency of the existing RC relaxation oscillator has poor temperature characteristics.

To achieve the above and other related objects, the present invention provides an RC relaxation oscillator comprising: the device comprises a capacitor charging and discharging module, a reference generating module and a comparison module;

the capacitor charging and discharging module is used for controlling the charging and discharging of the capacitor according to the output signal to generate capacitor voltage;

the reference generation module is used for providing original high voltage and original low voltage as reference voltages in a first oscillation period and providing new high voltage and original low voltage as reference voltages in a second and subsequent oscillation periods; wherein the new set high voltage is related to the maximum value of the capacitor voltage and is less than the original high voltage;

the comparison module is connected with the output ends of the capacitor charge-discharge module and the reference generation module and is used for comparing the capacitor voltage with the reference voltage and generating the output signal according to the comparison result.

Optionally, the capacitor charging and discharging module includes: the first PMOS transistor, the first NMOS transistor and the first capacitor are connected with the first current source and the second current source; the input end of the first current source is connected with working voltage, and the output end of the first current source is connected with the source end of the first PMOS tube; the drain end of the first PMOS tube is connected with the drain end of the first NMOS tube and the first end of the first capacitor, and the gate end of the first PMOS tube is connected with the gate end of the first NMOS tube and the output signal; the source end of the first NMOS tube is grounded through the second current source; the first end of the first capacitor is used as the output end of the capacitor charging and discharging module, and the second end of the first capacitor is grounded.

Optionally, the reference generating module includes: the device comprises an original voltage unit, an overcharge voltage unit, an operation unit and a switch unit;

the original voltage unit is used for generating the original high voltage and the original low voltage according to resistance voltage division;

the overcharge voltage unit is used for copying a capacitor charging part in the capacitor charging and discharging module and generating an overcharge voltage equal to the maximum value of the capacitor voltage;

the operation unit is connected with the output ends of the original voltage unit and the overcharging voltage unit and is used for performing operation processing on the original high voltage and the overcharging voltage and generating the new high voltage;

the switch unit is connected with the output ends of the original voltage unit and the operation unit and is used for carrying out output control on the original high voltage, the original low voltage and the new set high voltage according to the output signals and the control signals.

Optionally, the original voltage unit includes: the first resistor is connected with the first current source; the input end of the third current source is connected with the working voltage, and the output end of the third current source is connected with the first end of the first resistor; the second end of the first resistor is connected with the first end of the second resistor and is used as a high-voltage output end of the original voltage unit; the second end of the second resistor is grounded through the third resistor and serves as a low-voltage output end of the original voltage unit.

Optionally, the overcharge voltage unit includes: the fourth current source, the second PMOS tube and the second capacitor; the input end of the fourth current source is connected with the working voltage, and the output end of the fourth current source is connected with the source end of the second PMOS tube; the drain end of the second PMOS tube is grounded through the second capacitor and serves as the output end of the overcharge voltage unit, and the gate end of the second PMOS tube is connected with the control signal.

Optionally, the overcharge voltage unit further includes: and the non-inverting input end of the voltage follower is connected with the drain end of the second PMOS tube, the inverting input end of the voltage follower is connected with the output end of the voltage follower, and the output end of the voltage follower generates the overcharging voltage.

Optionally, the operation unit includes: the operational amplifier, the fourth resistor and the fifth resistor; and the non-inverting input end of the operational amplifier is connected with the high-voltage output end of the original voltage unit, the inverting input end of the operational amplifier is connected with the output end of the overcharging voltage unit through the fourth resistor, and is connected with the output end of the overcharging voltage unit through the fifth resistor, and the output end of the operational amplifier is used as the output end of the operational unit.

Optionally, the switching unit includes: a first switch, a second switch, a third switch and a fourth switch; the first end of the first switch is connected with the high-voltage output end of the original voltage unit, and the second end of the first switch is connected with the first end of the second switch and the first end of the third switch; the second end of the second switch is connected with the output end of the operation unit, and the second end of the third switch is connected with the first end of the fourth switch and is used as the output end of the switch unit; and the second end of the fourth switch is connected with the low-voltage output end of the original voltage unit.

Optionally, the reference generating module further includes: a control unit for generating the control signal according to the output signal; wherein the control unit includes: and the data end of the D trigger is connected with the working voltage, the clock end of the D trigger is connected with the output signal, and the output end of the D trigger is used as the output end of the control unit.

Optionally, the RC relaxation oscillator further comprises: the shaping module is connected with the output end of the comparison module and is used for shaping the output signal and outputting the shaped output signal; wherein, the shaping module includes: schmitt trigger and inverter chain; the input end of the Schmitt trigger is connected with the output end of the comparison module, the output end of the Schmitt trigger is connected with the input end of the inverter chain, and the output end of the inverter chain is used as the output end of the shaping module.

The invention also provides a working method of the RC relaxation oscillator, which comprises the following steps:

the RC relaxation oscillator starts and outputs a low level in a first oscillation period, and the first capacitor charges based on the first current source and generates capacitor voltage; comparing the capacitor voltage with the original high voltage, and inverting the comparator output when the capacitor voltage rises to (vh+Δv);

the RC relaxation oscillator outputs a high level, and the first capacitor discharges to the ground based on the second current source and generates a capacitor voltage; comparing the capacitor voltage with the original low voltage, and inverting the comparator output when the capacitor voltage drops to (VL- Δv);

the second oscillation period, the RC relaxation oscillator outputs a low level, and the first capacitor is charged based on the first current source and generates capacitor voltage; comparing the capacitor voltage with a newly set high voltage, and inverting the comparator output when the capacitor voltage rises to (vh_new+Δv);

the RC relaxation oscillator outputs a high level, and the first capacitor discharges to the ground based on the second current source and generates a capacitor voltage; comparing the capacitor voltage with the original low voltage, and inverting the comparator output when the capacitor voltage drops to (VL- Δv);

the third and subsequent oscillation cycles repeat the second oscillation cycle continuously;

wherein VH is the original high voltage, VL is the original low voltage, vh_new is the newly set high voltage, and Δv is the amount of overcharged voltage generated by the capacitor at the overcharging time.

As described above, the RC relaxation oscillator and the working method thereof of the invention are based on the design of the capacitor charge-discharge module, the reference generation module and the comparison module, and the influence of the overcharge time on the oscillator frequency is eliminated by changing the reference voltage, even if the change of temperature can cause the change of the overcharge time, the change of the overcharge time is eliminated after passing through the operation unit and is not reflected in the oscillator frequency, so that the temperature characteristic of the RC relaxation oscillator is improved to a great extent, the temperature drift (namely the temperature sensitivity) of the oscillator frequency is reduced, the stability of the oscillator is improved, the oscillator frequency under the same condition is also improved, the frequency range of the RC relaxation oscillator is enlarged, and the possibility of the RC relaxation oscillator applied in a wider range (such as a high-precision circuit) is improved; after the oscillator is stable, the maximum difference value achieved by charging and discharging of the capacitor is exactly equal to the difference between the original high voltage and the original low voltage, so that the actual value and the theoretical calculated value of the frequency of the oscillator are consistent, and the frequency adjustment is convenient.

Drawings

Fig. 1 shows a schematic circuit diagram of an RC relaxation oscillator with a single comparator.

Fig. 2 shows a theoretical waveform diagram of the RC relaxation oscillator shown in fig. 1.

Fig. 3 shows a practical waveform diagram of the RC relaxation oscillator shown in fig. 1.

Fig. 4 shows a schematic circuit diagram of an RC relaxation oscillator of the present invention.

Fig. 5 shows a practical waveform diagram of the RC relaxation oscillator shown in fig. 4.

Description of element reference numerals

100. Capacitor charging and discharging module

200. Reference generating module

201. Original voltage unit

202. Overcharge voltage unit

203. Arithmetic unit

204. Switch unit

205. Control unit

300. Comparison module

400. Shaping module

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 5. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Fig. 1 shows an RC relaxation oscillator of a single comparator, in which a capacitor C is periodically charged and discharged by a first current source I1 and a second current source I2 to generate a capacitor voltage VC, which is input to a non-inverting terminal of the comparator, while a third current source I3 flows through a second resistor R2 to generate a reference high voltage VH and a reference low voltage VL, which are periodically input to an inverting terminal of the comparator; the comparator compares VC with VH, VC with VL respectively, so that high and low levels are periodically generated at the output end, and an oscillating signal with a duty ratio of 50% is finally generated after the shaping of a Schmitt trigger and an inverter.

The specific working principle is as follows: the third current source I3 flows through the second resistor R2 and generates a reference high voltage VH and a reference low voltage VL at both ends thereof, respectively, and the states of the first switch S1 and the second switch S2 are controlled by the output Vo;

when the oscillator is started, vo is at a low level, the first switch S1 is closed, the second switch S2 is turned off, and the reference high voltage VH is input to the inverting terminal of the comparator through the first switch S1; meanwhile, as Vo is at a low level, the PMOS tube MP1 is turned on, the NMOS tube MN1 is turned off, and the first current source I1 charges the capacitor C, so that the voltage of the non-inverting terminal of the comparator is gradually increased.

The comparator compares the voltages of the two input ends in real time, when the capacitor voltage VC rises to be equal to the reference high voltage VH, the output of the comparator is turned over, the output state of the oscillator is changed, and Vo is changed from low level to high level.

When Vo is changed to a high level, the first switch S1 is turned off, the second switch S2 is turned on, the reference low voltage VL replaces the original reference high voltage VH and is input to the inverting terminal of the comparator, meanwhile, since Vo is a high level, the NMOS tube MN1 is turned on, the PMOS tube MP1 is turned off, and the capacitor C discharges towards the ground with the second current source I2, so that the voltage at the non-inverting terminal of the comparator gradually decreases.

The comparator compares the voltages of the two input ends in real time, when the capacitor voltage VC is reduced to be equal to the reference low voltage VL, the output of the comparator is turned over, the output state of the oscillator is changed, and Vo is changed from high level to low level.

The above process is repeated, and therefore an oscillating signal Vo is generated at the output, assuming i1=i2=ic, and the waveform diagram of the oscillator is shown in fig. 2.

Let t be _{Filling material} ＝t2-t1，t _{Put and put} =t3-t 2, as known from the principle of RC relaxation oscillators:

the same principle can be obtained:

the output frequency of the oscillator:

however, the above conclusion is that the output frequency of the RC relaxation oscillator is obtained based on the analysis under ideal conditions, in the actual situation, when the inputs at the two ends of the comparator are equal, the state of the comparator is not changed, but the state is changed when the input difference at the two ends reaches Vos, and the comparator and the whole circuit are transmitted for a certain delay time, so that the voltage on the capacitor C does not change state immediately when reaching the reference voltage of the comparator, but overcharge occurs for a period of time, and the waveform diagram in the actual situation is shown in fig. 3, wherein td is the overcharge time.

In practical cases, due to the existence of the overcharge time td, the output frequency of the RC relaxation oscillator is smaller than that in ideal cases, and the practical frequency is:

if only the influence of the overcharge time td on the output frequency of the RC relaxation oscillator is considered, the mobility of carriers is changed due to the change of the temperature, so that the transmission delay of the comparator and the whole circuit is changed, and the offset voltage and the temperature of the comparator have strong correlation, so that the change of the temperature can be reflected in the delay and the offset, and finally the overcharge time td is influenced, and the output frequency of the RC relaxation oscillator is greatly shifted in temperature.

Based on the above analysis, the RC relaxation oscillator shown in fig. 1 has the following drawbacks:

because the transmission delay and the offset voltage of the comparator have stronger correlation with temperature, the overcharge time td on the capacitor C can be changed along with the temperature, and finally the temperature drift of the output frequency is larger. The existence of the overcharge time td leads to the fact that the actual frequency of the oscillator is lower than the theoretical frequency, that is, the theoretical value deviates from the actual value, so that the range of the output frequency of the oscillator is narrowed.

In order to solve the problems of the RC relaxation oscillator shown in fig. 1, as shown in fig. 4, the present embodiment provides an RC relaxation oscillator, which includes: a capacitor charge and discharge module 100, a reference generation module 200 and a comparison module 300.

The capacitor charge-discharge module 100 is used for controlling the charge and discharge of a capacitor according to the output signal Vo to generate a capacitor voltage VC.

As an example, the capacitive charge-discharge module 100 includes: the first PMOS transistor MP1, the first NMOS transistor MN1 and the first capacitor C1 are connected with the first current source I1, the second current source I2 and the first capacitor C1; the input end of the first current source I1 is connected with the working voltage, and the output end of the first current source I1 is connected with the source end of the first PMOS tube MP 1; the drain end of the first PMOS tube MP1 is connected with the drain end of the first NMOS tube MN1 and the first end of the first capacitor C1, and the gate end is connected with the gate end of the first NMOS tube MN1 and the output signal Vo; the source end of the first NMOS tube MN1 is grounded through a second current source I2; the first end of the first capacitor C1 is used as an output end of the capacitor charging/discharging module 100 to generate a capacitor voltage VC, and the second end is grounded.

In this example, the current value of the first current source I1 and the current value of the second current source I2 are equal, that is, i1=i2. When the output signal Vo is at a low level, the first PMOS tube MP1 is turned on, the first NMOS tube MN1 is turned off, and at the moment, the first current source I1 charges the first capacitor C1, and the capacitor voltage VC is gradually increased; when the output signal Vo is at a high level, the first PMOS transistor MP1 is turned off, the first NMOS transistor MN1 is turned on, the first capacitor C1 discharges to ground by the second current source I2, and the capacitor voltage VC gradually decreases. In practice, the maximum value vcmax=vh+Δv of the capacitor voltage and the minimum value vcmin=vl- Δv of the capacitor voltage due to the existence of the overcharge time td.

The reference generating module 200 is configured to sequentially provide an original high voltage VH and an original low voltage VL as a reference voltage VREF in a first oscillation period, and sequentially provide a NEW high voltage vh_new and an original low voltage VL as the reference voltage VREF in a second and subsequent oscillation periods; the NEW high voltage vh_new is related to the maximum value VCmax of the capacitor voltage and is smaller than the original high voltage VH.

Specifically, the reference generation module 200 includes: an original voltage unit 201, an overcharge voltage unit 202, an operation unit 203, and a switching unit 204.

The raw voltage unit 201 is configured to generate a raw high voltage VH and a raw low voltage VL according to the resistive voltage division.

As an example, the original voltage unit 201 includes: the third current source I3, the first resistor R1, the second resistor R2 and the third resistor R3; the input end of the third current source I3 is connected with the working voltage, and the output end of the third current source I is connected with the first end of the first resistor R1; the second end of the first resistor R1 is connected to the first end of the second resistor R2 and is used as the high voltage output end of the original voltage unit 201 to generate an original high voltage VH; the second terminal of the second resistor R2 is grounded through the third resistor R3 and serves as a low voltage output terminal of the primitive voltage cell 201 to generate the primitive low voltage VL. Wherein the voltage difference between the original high voltage VH and the original low voltage VL VH-vl=i3×r2.

The overcharge voltage unit 202 is used to replicate the capacitor charging section in the capacitor charge-discharge module 100 and generate an overcharge voltage vc_h equal to the maximum value VCmax of the capacitor voltage, that is, vc_h=vcmax=vh+Δv.

As an example, the overcharge voltage unit 202 includes: the fourth current source I4, the second PMOS tube MP2 and the second capacitor C2; the input end of the fourth current source I4 is connected with the working voltage, and the output end of the fourth current source I is connected with the source end of the second PMOS tube MP 2; the drain terminal of the second PMOS transistor MP2 is grounded through the second capacitor C2 and is used as the output terminal of the overcharge voltage unit 202 to generate the overcharge voltage vc_h, and the gate terminal is connected to the control signal Qo.

In this example, the current value of the fourth current source I4 and the current value of the first current source I1 are equal, i.e., i4=i1; the capacitance value of the second capacitor C2 is equal to the capacitance value of the first capacitor C1, that is, c2=c1; the second PMOS transistor MP2 is the same as the first PMOS transistor MP1, i.e., the parameters of the two are the same. When the control signal Qo is at a low level, the second PMOS tube MP2 is turned on, the fourth current source I4 charges the second capacitor C2, and the capacitor voltage gradually rises and reaches (VH+DeltaV); when the control signal Qo is at a high level, the second PMOS transistor MP2 is turned off, and the capacitor voltage is kept unchanged at (vh+Δv).

Further, the overcharge voltage unit 202 further includes: the non-inverting input end of the voltage follower is connected with the drain end of the second PMOS tube MP2, the inverting input end of the voltage follower is connected with the output end of the voltage follower, and the output end of the voltage follower generates the overcharge voltage VC_H. In practical application, the voltage follower can be composed of a transistor or an operational amplifier, but because the input impedance of the operational amplifier is large and the output impedance of the operational amplifier is small, the voltage follower plays a role in impedance matching, not only can reduce the influence on a signal source, but also can improve the capacity of carrying load, and therefore, the voltage follower of the example is composed of the operational amplifier OP 1.

The operation unit 203 is connected to the output terminals of the original voltage unit 201 and the overcharge voltage unit 202, and is configured to perform an operation process on the original high voltage VH and the overcharge voltage vc_h and generate a NEW high voltage vh_new.

As an example, the operation unit 203 includes: an operational amplifier OP2, a fourth resistor R4 and a fifth resistor R5; the non-inverting input terminal of the operational amplifier OP2 is connected to the high voltage output terminal of the original voltage unit 201 to access the original high voltage VH, the inverting input terminal is connected to the output terminal of the overcharge voltage unit 202 through the fourth resistor R4 to access the overcharge voltage vc_h, and is connected to the output terminal thereof through the fifth resistor R5, and the output terminal is used as the output terminal of the operation unit 203 to generate the NEW set high voltage vh_new.

In this example, the resistance of the fifth resistor R5 is 2 times that of the fourth resistor R4, that is, r5=2×r4. The operational amplifier OP2, the fourth resistor R4 and the fifth resistor R5 form a subtractor, and the principle of "virtual short and virtual break" is utilized to indicate that the voltages at the non-inverting input terminal and the inverting input terminal of the operational amplifier OP2 are equal and have the magnitude of VH, that is, the current flowing through the fourth resistor R4 is equal to the current flowing through the fifth resistor R5, that is, (VH-vc_h)/r4= (vh_new-VH)/R5, since r5=2×r4, then 2 (VH-vc_h) = (vh_new-VH) and since vc_h=vh+Δv, then vh_new=vh-2Δv.

The switching unit 204 is connected to the output terminals of the original voltage unit 201 and the operation unit 203, and is configured to perform output control on the original high voltage VH, the original low voltage VL, and the NEW high voltage vh_new according to the output signal Vo and the control signal Qo.

As an example, the switching unit 204 includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the first end of the first switch S1 is connected with the high-voltage output end of the original voltage unit 201 to be connected with the original high voltage VH, and the second end of the first switch S2 is connected with the first end of the third switch S3; the second end of the second switch S2 is connected to the output end of the operation unit 203 to access the newly set high voltage vh_new, and the second end of the third switch S3 is connected to the first end of the fourth switch S4 and is used as the output end of the switch unit 204 to generate the reference voltage VREF; a second terminal of the fourth switch S4 is connected to the low voltage output terminal of the original voltage unit 201 to switch in the original low voltage VL.

In this example, the first switch S1 is controlled by an inverted signal of the control signal Qo, the second switch S2 is controlled by the control signal Qo, the third switch S3 is controlled by an inverted signal of the output signal Vo, and the fourth switch S4 is controlled by the output signal Vo. The method comprises the following steps: when the control signal Qo is at a low level, the first switch S1 is closed, and the second switch S2 is turned off; when the control signal Qo is at a high level, the first switch S1 is turned off and the second switch S2 is turned on. When the output signal Vo is at a low level, the third switch S3 is turned on, and the fourth switch S4 is turned off; when the output signal Vo is at a high level, the third switch S3 is turned off, and the fourth switch S4 is turned on.

In fact, the control signal Qo is related to the output signal Vo, and in the first oscillation period, the control signal Qo is low when the output signal Vo is low, and the control signal Qo is high when the output signal Vo is high; in the second and subsequent oscillation periods, the control signal Qo remains at a high level regardless of whether the output signal Vo is at a low level or at a high level.

Further, the reference generating module 200 further includes: the control unit 205 is configured to generate a control signal Qo according to the output signal Vo.

As an example, the control unit 205 includes: the D flip-flop DFF has a data terminal connected to the operating voltage, a clock terminal connected to the output signal Vo, and an output terminal serving as an output terminal of the control unit 205 to generate the control signal Qo. The D flip-flop is a rising edge triggered D flip-flop, so that the first rising edge of the output signal Vo is triggered, the output of the first rising edge is changed from low level to high level, and the first rising edge is always kept at high level.

The comparison module 300 is connected to the output terminals of the capacitor charge-discharge module 100 and the reference generation module 200, and is used for comparing the capacitor voltage VC with the reference voltage VREF and generating an output signal Vo according to the comparison result.

As an example, the comparison module 300 is implemented by a comparator CMP, wherein a non-inverting input terminal of the comparator CMP is connected to an output terminal of the capacitor charge-discharge module 100 to access the capacitor voltage VC, and an inverting input terminal of the comparator CMP is connected to an output terminal of the reference generation module 200 to access the reference voltage VREF, and the output terminal generates the output signal Vo.

In this example, due to the overcharge time td, the comparator CMP does not output a flip when the voltages at the two input terminals are equal, but outputs a flip when the voltage difference between the two input terminals reaches Δv; as for the case where the capacitance voltage VC gradually increases, the output of the comparator changes from the low level to the high level when vc=vref+Δv, and similarly, the output of the comparator changes from the high level to the low level when vc=vref- Δv when the capacitance voltage VC gradually decreases.

Further, the RC relaxation oscillator further includes: the shaping module 400 is connected to the output end of the comparing module 300, and is configured to shape the output signal Vo and output the shaped output signal Vo, so as to finally generate an oscillating signal Vo' with a duty ratio of 50%. It should be noted that, when the RC relaxation oscillator further includes the shaping module 400, in this embodiment, the output signal Vo related to controlling the first PMOS transistor MP1, the third switch S3, and the fourth switch S4 may be replaced by the shaped oscillation signal Vo ', and meanwhile, the output signal Vo connected to the clock end of the D flip-flop DFF may also be replaced by the shaped oscillation signal Vo', so as to improve the signal precision.

As an example, the shaping module 400 includes: schmitt trigger SMIT and inverter chain; the input end of the schmitt trigger SMIT is connected to the output end of the comparing module 300 to access the output signal Vo, and the output end is connected to the input end of the inverter chain, and the output end of the inverter chain is used as the output end of the shaping module 400 to generate the oscillation signal Vo'. The inverter chain comprises a first inverter INV1 and a second inverter INV2, wherein the input end of the first inverter INV1 is connected with the output end of the schmitt trigger SMIT, the output end of the first inverter INV1 is connected with the input end of the second inverter INV2, and the output end of the second inverter INV2 is used as the output end of the shaping module 400.

Correspondingly, the embodiment also provides a working method of the RC relaxation oscillator, which comprises the following steps:

the RC relaxation oscillator starts and outputs a low level in the first oscillation period, and the first capacitor C1 is charged based on the first current source I1 and generates a capacitor voltage VC; comparing the capacitor voltage VC with the original high voltage VH, and when the capacitor voltage VC increases to (vh+Δv), the comparator CMP output is inverted;

the RC relaxation oscillator outputs a high level, and the first capacitor C1 is discharged to the ground based on the second current source I2 and generates a capacitor voltage VC; comparing the capacitor voltage VC with the original low voltage VL, and inverting the output of the comparator CMP when the capacitor voltage VC is reduced to (VL-DeltaV);

in the second oscillation period, the RC relaxation oscillator outputs a low level, and the first capacitor C1 is charged based on the first current source I1 and generates a capacitor voltage VC; comparing the capacitor voltage VC with the newly set high voltage VH_NEW, and when the capacitor voltage VC rises to (VH_NEW+DeltaV), the output of the comparator CMP is inverted;

the RC relaxation oscillator outputs a high level, and the first capacitor C1 is discharged to the ground based on the second current source I2 and generates a capacitor voltage VC; comparing the capacitor voltage VC with the original low voltage VL, the comparator CMP output toggles when the capacitor voltage VC drops to (VL-av).

The third and subsequent oscillation cycles repeat the second oscillation cycle continuously;

wherein VH is the original high voltage, VL is the original low voltage, vh_new is the newly set high voltage, and Δv is the amount of overcharged voltage generated by the capacitor at the overcharging time.

In this example, in the first oscillation period, when the RC relaxation oscillator is just started, the output signal Vo is at a low level, and the data terminal of the rising edge triggered D flip-flop DFF is always at a high level, so the output terminal thereof is at a low level, that is, the control signal Qo is at a low level, at this time, the first switch S1 and the third switch S3 are closed, the second switch S2 and the fourth switch S4 are turned off, and the original high voltage VH is input as the reference voltage VREF to the inverting input terminal of the comparator CMP.

Meanwhile, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, the first NMOS transistor MN1 is turned off, the first current source I1 charges the first capacitor C1, and the fourth current source I4 charges the second capacitor C2, and since i1=i4 and c1=c2, the voltages on the two capacitors keep consistent at all times.

Due to the overcharge time td, the capacitor voltage VC does not decrease immediately when it increases to the original high voltage VH, but starts to decrease after the increase of Δv is continued, that is, the maximum voltage values of both capacitors are (vh+Δv), at which time the comparator CMP output is inverted.

When the output signal Vo changes from low level to high level, the rising edge triggered D flip-flop DFF detects the rising edge of its clock terminal and makes its output terminal become the same high level as the data terminal, that is, the control signal Qo changes from low level to high level and remains high level all the time, at this time, the first switch S1 and the third switch S3 are turned off, the second switch S2 and the fourth switch S4 are turned on, and the original low voltage VL is input as the reference voltage VREF to the inverting input terminal of the comparator CMP.

Meanwhile, the first PMOS tube MP1 and the second PMOS tube MP2 are turned off, the first NMOS tube MN1 is turned on, the first capacitor C1 is discharged to the ground through the second current source I2, and the capacitor voltage VC is gradually reduced; the second capacitor C2 has no discharge path, and therefore the voltage thereof is kept constant (vh+Δv), that is, the overcharge voltage vc_h=vh+Δv, and thus the NEW high voltage vh_new=vh-2 Δv is obtained by subtracting the overcharge voltage.

Due to the overcharge time td, the capacitor voltage VC does not rise immediately when it decreases to the original low voltage VL, but starts to rise after the decrease of Δv is continued, at which point the comparator CMP output toggles.

In the second and subsequent oscillation periods, since the control signal Qo is always high, the first switch S1 is always turned off, the second switch S2 is always turned on, the second PMOS transistor MP2 is always turned off, and the overcharge voltage vh_c is always maintained at (vh+Δv).

When the output signal Vo changes from high level to low level, the third switch S3 is turned on, the fourth switch S4 is turned off, and the newly set high voltage vh_new is input as the reference voltage VREF to the inverting input terminal of the comparator CMP.

Meanwhile, the first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, the first current source I1 charges the first capacitor C1, and the capacitor voltage VC gradually increases.

Due to the overcharge time td, the capacitor voltage VC does not decrease immediately when it increases to the NEW set high voltage vh_new, but starts to decrease after the increase of Δv is continued, at which time the comparator CMP output is inverted.

When the output signal Vo changes from low level to high level, the third switch S3 is turned off, the fourth switch S4 is turned on, and the original low voltage VL is input to the inverting input terminal of the comparator CMP as the reference voltage VREF.

Meanwhile, the first PMOS transistor MP1 is turned off, the first NMOS transistor MN1 is turned on, the first capacitor C1 is discharged to the ground through the second current source I2, and the capacitor voltage VC gradually decreases.

Due to the overcharge time td, the capacitor voltage VC does not rise immediately when it decreases to the original low voltage VL, but starts to rise after the decrease of Δv is continued, at which point the comparator CMP output toggles.

As can be seen, the RC relaxation oscillator of the present embodiment generates a stable oscillation signal from the second oscillation period, and since the high voltage vh_new=vh-2Δv is newly set, even though the overcharge still exists in the second and subsequent oscillation periods, the difference between the maximum voltage and the minimum voltage of the overcharge is always equal to the difference between the original high voltage VH and the original low voltage VL (i.e., VH-vl=i3×r2), thereby eliminating the influence of the overcharge time on the clock frequency and reducing the temperature sensitivity of the RC relaxation oscillator.

In other words, the scheme of the present embodiment does not eliminate the overcharge voltage Δv caused by the overcharge time td, but by reducing the difference between the larger value and the smaller value of the reference voltage VREF so that even if there is overcharge in the subsequent oscillation process, the difference between the maximum value and the minimum value of the overcharge is always equal to the difference between the original high voltage VH and the original low voltage VL, thereby eliminating the influence of the overcharge time on the clock frequency, reducing the temperature sensitivity of the RC relaxation oscillator.

In summary, according to the RC relaxation oscillator and the working method thereof of the present invention, based on the designs of the capacitor charge-discharge module, the reference generation module and the comparison module, the influence of the overcharge time on the oscillator frequency is eliminated by changing the reference voltage, even if the change of the temperature causes the change of the overcharge time, the change of the overcharge time is eliminated after passing through the operation unit and is not reflected in the oscillator frequency, so that the temperature characteristic of the RC relaxation oscillator is improved to a great extent, the temperature drift (i.e. temperature sensitivity) of the oscillator frequency is reduced, the stability of the oscillator is improved, and meanwhile, the oscillator frequency under the same condition is improved, the frequency range of the RC relaxation oscillator is enlarged, and the possibility of the RC relaxation oscillator being applied in a wider range (e.g. high-precision circuit) is improved; after the oscillator is stable, the maximum difference value achieved by charging and discharging of the capacitor is exactly equal to the difference between the original high voltage and the original low voltage, so that the actual value and the theoretical calculated value of the frequency of the oscillator are consistent, and the frequency adjustment is convenient. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (11)

1. An RC relaxation oscillator, said RC relaxation oscillator comprising: the device comprises a capacitor charging and discharging module, a reference generating module and a comparison module;

the capacitor charging and discharging module is used for controlling the charging and discharging of the capacitor according to the output signal to generate capacitor voltage;

the reference generation module is used for providing original high voltage and original low voltage as reference voltages in a first oscillation period and providing new high voltage and original low voltage as reference voltages in a second and subsequent oscillation periods; wherein the new set high voltage is related to the maximum value of the capacitor voltage and is less than the original high voltage;

the comparison module is connected with the output ends of the capacitor charge-discharge module and the reference generation module and is used for comparing the capacitor voltage with the reference voltage and generating the output signal according to the comparison result.

2. The RC relaxation oscillator of claim 1, wherein said capacitive charge-discharge module comprises: the first PMOS transistor, the first NMOS transistor and the first capacitor are connected with the first current source and the second current source; the input end of the first current source is connected with working voltage, and the output end of the first current source is connected with the source end of the first PMOS tube; the drain end of the first PMOS tube is connected with the drain end of the first NMOS tube and the first end of the first capacitor, and the gate end of the first PMOS tube is connected with the gate end of the first NMOS tube and the output signal; the source end of the first NMOS tube is grounded through the second current source; the first end of the first capacitor is used as the output end of the capacitor charging and discharging module, and the second end of the first capacitor is grounded.

3. The RC relaxation oscillator of claim 1, wherein said reference generation module comprises: the device comprises an original voltage unit, an overcharge voltage unit, an operation unit and a switch unit;

the original voltage unit is used for generating the original high voltage and the original low voltage according to resistance voltage division;

the overcharge voltage unit is used for copying a capacitor charging part in the capacitor charging and discharging module and generating an overcharge voltage equal to the maximum value of the capacitor voltage;

the operation unit is connected with the output ends of the original voltage unit and the overcharging voltage unit and is used for performing operation processing on the original high voltage and the overcharging voltage and generating the new high voltage;

the switch unit is connected with the output ends of the original voltage unit and the operation unit and is used for carrying out output control on the original high voltage, the original low voltage and the new set high voltage according to the output signals and the control signals.

4. The RC relaxation oscillator of claim 3, wherein said raw voltage unit comprises: the first resistor is connected with the first current source; the input end of the third current source is connected with the working voltage, and the output end of the third current source is connected with the first end of the first resistor; the second end of the first resistor is connected with the first end of the second resistor and is used as a high-voltage output end of the original voltage unit; the second end of the second resistor is grounded through the third resistor and serves as a low-voltage output end of the original voltage unit.

5. The RC relaxation oscillator of claim 3, wherein said overcharge voltage unit comprises: the fourth current source, the second PMOS tube and the second capacitor; the input end of the fourth current source is connected with the working voltage, and the output end of the fourth current source is connected with the source end of the second PMOS tube; the drain end of the second PMOS tube is grounded through the second capacitor and serves as the output end of the overcharge voltage unit, and the gate end of the second PMOS tube is connected with the control signal.

6. The RC relaxation oscillator of claim 5, wherein said overcharge voltage cell further comprises: and the non-inverting input end of the voltage follower is connected with the drain end of the second PMOS tube, the inverting input end of the voltage follower is connected with the output end of the voltage follower, and the output end of the voltage follower generates the overcharging voltage.

7. The RC relaxation oscillator of claim 3, wherein said arithmetic unit comprises: the operational amplifier, the fourth resistor and the fifth resistor; and the non-inverting input end of the operational amplifier is connected with the high-voltage output end of the original voltage unit, the inverting input end of the operational amplifier is connected with the output end of the overcharging voltage unit through the fourth resistor, and is connected with the output end of the overcharging voltage unit through the fifth resistor, and the output end of the operational amplifier is used as the output end of the operational unit.

8. An RC relaxation oscillator according to claim 3, characterized in that said switching unit comprises: a first switch, a second switch, a third switch and a fourth switch; the first end of the first switch is connected with the high-voltage output end of the original voltage unit, and the second end of the first switch is connected with the first end of the second switch and the first end of the third switch; the second end of the second switch is connected with the output end of the operation unit, and the second end of the third switch is connected with the first end of the fourth switch and is used as the output end of the switch unit; and the second end of the fourth switch is connected with the low-voltage output end of the original voltage unit.

9. The RC relaxation oscillator of any of claims 3-8, wherein said reference generation module further comprises: a control unit for generating the control signal according to the output signal; wherein the control unit includes: and the data end of the D trigger is connected with the working voltage, the clock end of the D trigger is connected with the output signal, and the output end of the D trigger is used as the output end of the control unit.

10. The RC relaxation oscillator of claim 1, further comprising: the shaping module is connected with the output end of the comparison module and is used for shaping the output signal and outputting the shaped output signal; wherein, the shaping module includes: schmitt trigger and inverter chain; the input end of the Schmitt trigger is connected with the output end of the comparison module, the output end of the Schmitt trigger is connected with the input end of the inverter chain, and the output end of the inverter chain is used as the output end of the shaping module.

11. A method of operating an RC relaxation oscillator as claimed in any of claims 1 to 10, said method of operation comprising:

the RC relaxation oscillator starts and outputs a low level in a first oscillation period, and the first capacitor charges based on the first current source and generates capacitor voltage; comparing the capacitor voltage with the original high voltage, and inverting the comparator output when the capacitor voltage rises to (vh+Δv);

the RC relaxation oscillator outputs a high level, and the first capacitor discharges to the ground based on the second current source and generates a capacitor voltage; comparing the capacitor voltage with the original low voltage, and inverting the comparator output when the capacitor voltage drops to (VL- Δv);

the second oscillation period, the RC relaxation oscillator outputs a low level, and the first capacitor is charged based on the first current source and generates capacitor voltage; comparing the capacitor voltage with a newly set high voltage, and inverting the comparator output when the capacitor voltage rises to (vh_new+Δv);

the RC relaxation oscillator outputs a high level, and the first capacitor discharges to the ground based on the second current source and generates a capacitor voltage; comparing the capacitor voltage with the original low voltage, and inverting the comparator output when the capacitor voltage drops to (VL- Δv);

the third and subsequent oscillation cycles repeat the second oscillation cycle continuously;

wherein VH is the original high voltage, VL is the original low voltage, vh_new is the newly set high voltage, and Δv is the amount of overcharged voltage generated by the capacitor at the overcharging time.