CN117637613A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN117637613A CN117637613A CN202210972869.7A CN202210972869A CN117637613A CN 117637613 A CN117637613 A CN 117637613A CN 202210972869 A CN202210972869 A CN 202210972869A CN 117637613 A CN117637613 A CN 117637613A
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- 239000011229 interlayer Substances 0.000 claims abstract description 135
- 239000003989 dielectric material Substances 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000010438 heat treatment Methods 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 18
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
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- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
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- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein a grid structure is formed on the substrate, and an interlayer dielectric material layer covering the grid structure is also formed on the substrate; thinning the interlayer dielectric material layer higher than the top of the gate structure for one or more times, removing the interlayer dielectric material layer higher than the top of the gate structure, and reserving the interlayer dielectric material layer covering the side wall of the gate structure as an interlayer dielectric layer, wherein the thinning comprises the following steps: converting the interlayer dielectric material layer with partial thickness into a sacrificial layer; and removing the sacrificial layer. The invention is beneficial to guaranteeing the performance of the semiconductor structure.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
Chemical mechanical polishing (Chemical Mechanical Polishing, CMP) processes utilize mechanical forces in the atmosphere of a clean room to act on the wafer surface to generate fracture corrosion forces on the surface film layer, so that the wafer surface tends to be planarized for subsequent process steps (e.g., photolithography), and the etching efficiency must be increased by the chemical substances in the polishing solution through reaction.
In the existing semiconductor manufacturing process, chemical mechanical polishing of dielectric layers (Interlayer Dielectrics, ILD) and the like is very important for the subsequent semiconductor manufacturing process steps, but after chemical mechanical polishing, a large amount of scratches can be generated on the interlayer dielectric layers, which can greatly affect the product yield, and in the existing chemical mechanical polishing forming process of the interlayer dielectric layers, a thicker original layer is required, so that the complexity of the process is increased, and the processing cost is also increased.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which ensures the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, and an interlayer dielectric material layer covering the grid structure is also formed on the substrate; thinning the interlayer dielectric material layer higher than the top of the gate structure for one or more times, removing the interlayer dielectric material layer higher than the top of the gate structure, and reserving the interlayer dielectric material layer covering the side wall of the gate structure as an interlayer dielectric layer, wherein the thinning comprises the following steps: converting the interlayer dielectric material layer with partial thickness into a sacrificial layer; and removing the sacrificial layer.
Optionally, the step of converting the partial thickness interlayer dielectric material layer into the sacrificial layer includes: carrying out chemical reaction treatment on the interlayer dielectric material layer, converting part of the interlayer dielectric material layer into a sacrificial layer, wherein the sacrificial layer is a volatile material; the step of removing the sacrificial layer includes: and carrying out heating treatment on the sacrificial layer to volatilize the sacrificial layer.
Optionally, in the step of performing a chemical reaction treatment on the interlayer dielectric material layer, the chemical reaction treatment includes: and reacting the plasma generated by the fluorocarbon-based gas with the interlayer dielectric material layer.
Optionally, the fluorocarbon-based gas comprises one or more of carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane.
Optionally, the material of the sacrificial layer comprises ammonium hexafluorosilicate.
Optionally, in the step of performing heat treatment on the sacrificial layer, the process of heat treatment includes: and (5) infrared heat treatment.
Optionally, in the step of performing the heat treatment on the sacrificial layer, the temperature of the heat treatment is 150 ℃ to 300 ℃, and the time of the heat treatment is 2s to 30s.
Optionally, the step of converting the partial thickness interlayer dielectric material layer into the sacrificial layer includes: modifying the interlayer dielectric material layer higher than the top of the gate structure to form a sacrificial layer, wherein the etching resistance of the sacrificial layer is smaller than that of the interlayer dielectric material layer; the step of removing the sacrificial layer includes: the sacrificial layer is removed by an etching process.
Optionally, the etching selectivity ratio of the sacrificial layer to the interlayer dielectric material layer is greater than or equal to 10.
Optionally, the process of modifying treatment comprises a plasma bombardment process.
Optionally, the gas employed in the plasma bombardment process comprises hydrogen or helium.
Optionally, the etching process includes a wet etching process.
Optionally, the etching solution of the wet etching process comprises hydrofluoric acid.
Optionally, in the step of providing a substrate, the gate structure is a dummy gate structure; after the interlayer dielectric material layer is thinned, the forming method further comprises the following steps: removing the pseudo gate structure to form a gate opening surrounded by the interlayer dielectric layer; a device gate structure is formed in the gate opening.
Optionally, in the step of providing the substrate, the material of the interlayer dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Optionally, in the step of providing the substrate, a channel protruding portion is further formed on the substrate, and the gate structure spans the channel protruding portion and covers a portion of a top and a portion of a sidewall of the channel protruding portion.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, thinning treatment is carried out on the interlayer dielectric material layer higher than the top of the gate structure for one or more times, the interlayer dielectric material layer higher than the top of the gate structure is removed, and the interlayer dielectric material layer covering the side wall of the gate structure is reserved as an interlayer dielectric layer, wherein the thinning treatment comprises the following steps: converting an interlayer dielectric material layer with partial thickness into a sacrificial layer, and removing the sacrificial layer; the interlayer dielectric material layer with partial thickness is converted into the sacrificial layer, so that an interface with higher flatness between the sacrificial layer and the residual interlayer dielectric material layer is easy to obtain, the removal amount is easy to control when the sacrificial layer is removed, correspondingly, after the sacrificial layer is removed to obtain the interlayer dielectric layer, the flatness of the top surface of the interlayer dielectric layer is higher, the probability of sinking at the top of the interlayer dielectric layer is reduced, and the probability of damaging a grid structure is reduced, so that the performance of the semiconductor structure is guaranteed.
Drawings
Fig. 1 to 2 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 3 to 6 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 7 to 8 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of the current semiconductor structure is difficult to guarantee. The reason why the performance of the semiconductor structure is difficult to guarantee is analyzed by combining a forming method of the semiconductor structure.
Fig. 1 to 2 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, a gate structure 20 is formed on the substrate 10, and an interlayer dielectric material layer 30 covering the gate structure 20 is further formed on the substrate 10.
Referring to fig. 2, the interlayer dielectric material layer 30 is etched, the interlayer dielectric material layer 30 higher than the top of the gate structure 20 is removed, and the interlayer dielectric material layer 30 covering the sidewalls of the gate structure 20 remains as the interlayer dielectric layer 32.
The interlayer dielectric material layer 30 is directly etched to obtain the interlayer dielectric layer 32, so that the etching stop position is difficult to control, the top of the interlayer dielectric layer 32 is easy to be recessed due to over etching, the gate structure 20 is easy to be damaged due to over etching, and in the process of forming a device gate structure subsequently, device gate structure residues are easy to be generated due to the top of the interlayer dielectric layer 32, so that the performance of a semiconductor structure is influenced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, and an interlayer dielectric material layer covering the grid structure is also formed on the substrate; thinning the interlayer dielectric material layer higher than the top of the gate structure for one or more times, removing the interlayer dielectric material layer higher than the top of the gate structure, and reserving the interlayer dielectric material layer covering the side wall of the gate structure as an interlayer dielectric layer, wherein the thinning comprises the following steps: converting the interlayer dielectric material layer with partial thickness into a sacrificial layer; and removing the sacrificial layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, thinning treatment is carried out on the interlayer dielectric material layer higher than the top of the gate structure for one or more times, the interlayer dielectric material layer higher than the top of the gate structure is removed, and the interlayer dielectric material layer covering the side wall of the gate structure is reserved as an interlayer dielectric layer, wherein the thinning treatment comprises the following steps: converting an interlayer dielectric material layer with partial thickness into a sacrificial layer, and removing the sacrificial layer; the interlayer dielectric material layer with partial thickness is converted into the sacrificial layer, so that an interface with higher flatness between the sacrificial layer and the residual interlayer dielectric material layer is easy to obtain, the removal amount is easy to control when the sacrificial layer is removed, correspondingly, after the sacrificial layer is removed to obtain the interlayer dielectric layer, the flatness of the top surface of the interlayer dielectric layer is higher, the probability of sinking at the top of the interlayer dielectric layer is reduced, and the probability of damaging a grid structure is reduced, so that the performance of the semiconductor structure is guaranteed.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 5 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, a substrate 100 is provided, a gate structure 200 is formed on the substrate 100, and an interlayer dielectric material layer 300 covering the gate structure 200 is further formed on the substrate 100.
The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure includes a planar transistor, a fin field effect transistor (FinFET), or a full-wrap (GAA) transistor, among others.
In this embodiment, the material of the substrate 100 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, taking a semiconductor structure as a fin field effect transistor as an example, a channel protrusion (not shown) is further formed on the substrate 100, and the gate structure 200 spans the channel protrusion and covers a portion of the top and a portion of the sidewall of the channel protrusion.
The channel boss is used to provide a channel for the transistor.
In this embodiment, the material of the channel lobe comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material.
In this embodiment, the gate structure 200 is a dummy gate structure for providing a spatial location for the subsequent formation of the device gate structure.
Specifically, the gate structure 200 is a stacked structure including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.
As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.
The interlayer dielectric material layer 300 is used for forming an interlayer dielectric layer later.
In this embodiment, the material of the interlayer dielectric material layer 300 is an insulating material, so that the interlayer dielectric layer formed later can play a role in isolating adjacent devices, and specifically, the material of the interlayer dielectric material layer 300 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. As an example, in this embodiment, the material of the interlayer dielectric material layer 300 is silicon nitride.
Referring to fig. 4 to 6 in combination, the interlayer dielectric material layer 300 higher than the top of the gate structure 200 is thinned one or more times, the interlayer dielectric material layer 300 higher than the top of the gate structure 200 is removed, and the interlayer dielectric material layer 300 covering the sidewalls of the gate structure 200 is left as the interlayer dielectric layer 320, wherein the thinning process includes: converting a portion of the thickness of the interlayer dielectric material layer 300 into a sacrificial layer 310; the sacrificial layer 310 is removed.
The interlayer dielectric layer 320 is used for isolating adjacent devices and also for providing a process basis for forming a gate opening for removing the dummy gate structure subsequently.
Accordingly, in the present embodiment, the material of the interlayer dielectric layer 320 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. As an example, in this embodiment, the material of the interlayer dielectric layer 320 is silicon nitride.
In this embodiment, when the interlayer dielectric material layer 300 with a partial thickness is converted into the sacrificial layer 310, a relatively high-flatness interface between the sacrificial layer 310 and the remaining interlayer dielectric material layer 300 is easily obtained, and the removal amount is easily controlled when the sacrificial layer 310 is removed, and accordingly, after the sacrificial layer 310 is removed to obtain the interlayer dielectric layer 320, the flatness of the top surface of the interlayer dielectric layer 320 is relatively high, and meanwhile, the probability of recessing the top of the interlayer dielectric layer 320 is reduced, and the probability of damaging the gate structure 200 is reduced, so that the performance of the semiconductor structure is guaranteed.
In this embodiment, the step of converting the interlayer dielectric material layer 300 with a partial thickness into the sacrificial layer 310 includes: the interlayer dielectric material layer 300 is subjected to chemical reaction treatment, so that a part of the interlayer dielectric material layer 300 is converted into a sacrificial layer 310, and the sacrificial layer 310 is made of a volatile material.
After the chemical reaction treatment, a part of the thickness of the interlayer dielectric material layer 300 is converted into the sacrificial layer 310, and the sacrificial layer 310 is made of a volatile material, so that the sacrificial layer 310 is easy to remove.
Note that, in this embodiment, the sacrificial layer 310 is formed by a chemical reaction process, and only the interlayer dielectric material layer 300 with a thinner surface can be converted into the sacrificial layer 310 by a single chemical reaction process, so in this embodiment, the interlayer dielectric material layer 300 higher than the top of the gate structure 200 is thinned several times until the interlayer dielectric material layer 300 higher than the top of the gate structure 200 is completely removed.
In this embodiment, in the step of performing the chemical reaction treatment on the interlayer dielectric material layer 300, the chemical reaction treatment includes: the plasma generated using the fluorocarbon-based gas reacts with the interlayer dielectric material layer 300.
In this embodiment, the material of the interlayer dielectric material layer 300 is silicon nitride, and the plasma generated by fluorocarbon-based gas reacts with the interlayer dielectric material layer 300 to form easily volatile fluorocarbon, which is beneficial to the removal of the sacrificial layer 310.
In this embodiment, the fluorocarbon-based gas includes carbon tetrafluoride (CF 4 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Fluoromethane (CH) 3 F) One or more of the following.
One or more fluorocarbon-based gases selected from carbon tetrafluoride, trifluoromethane, difluoromethane and fluoromethane are adopted, so that the regulation and control of the chemical reaction rate are facilitated.
Correspondingly, the material of the sacrificial layer comprises ammonium hexafluorosilicate ((NH) 4 ) 2 SiF 6 )，(NH 4 ) 2 SiF 6 Is good in volatility and is favorable for the sacrifice layer 310Is removed.
In this embodiment, the step of removing the sacrificial layer 310 includes: the sacrificial layer 310 is subjected to a heat treatment so that the sacrificial layer 310 volatilizes.
The heat treatment of the sacrificial layer 310 is beneficial to accelerating the volatilization of the sacrificial layer 310 and improving the process efficiency.
In this embodiment, in the step of performing the heat treatment on the sacrificial layer 310, the process of the heat treatment includes: and (5) infrared heat treatment.
The cost of the infrared heat treatment is relatively low, the operation steps are simple, the process parameters of the infrared heat treatment are easy to control, and the process controllability is good.
In the step of heat-treating the sacrifice layer 310, the temperature of the heat treatment is not particularly high or low. If the temperature of the heating treatment is too high, other film layers of the semiconductor structure are easily damaged by the environment with the too high temperature, and the performance of the semiconductor structure is affected; if the temperature of the heating process is too low, it is difficult to accelerate the volatilization speed of the sacrificial layer 310, thereby making it difficult to improve the process efficiency. For this reason, in the step of heat-treating the sacrifice layer 310 in this embodiment, the temperature of the heat treatment is 150 to 300 ℃.
In the step of heat-treating the sacrificial layer 310, the time of the heat treatment is preferably not too long or too short. If the heating treatment is too long, the semiconductor structure is in a heating environment for a long time, other film layers of the semiconductor structure are easy to damage, and the performance of the semiconductor structure is affected; if the time of the heat treatment is too short, it is liable to cause difficulty in complete volatilization removal of the sacrificial layer 310, thereby causing generation of a residue of the sacrificial layer 310, which affects subsequent fabrication of the semiconductor structure. For this reason, in the step of performing the heat treatment on the sacrifice layer 310 in this embodiment, the time of the heat treatment is 2s to 30s.
Fig. 4 to 5 show a process of performing the thinning process once, and in this embodiment, the thinning process may be performed a plurality of times by cycling the processes of fig. 4 to 5.
In this embodiment, after the interlayer dielectric material layer 300 is thinned, the forming method further includes: the dummy gate structure 200 is removed and a gate opening (not shown) surrounded by an interlayer dielectric layer 320 is formed.
The gate openings are used to provide spatial locations for subsequently forming device gate structures.
In this embodiment, a device gate structure (not shown) is formed in the gate opening.
The device gate structure is used for controlling the on and off of the channel of the transistor.
In this embodiment, the top flatness of the interlayer dielectric layer 320 is better, which is beneficial to reducing the probability of generating residues of the device gate structure due to the recessing of the top of the interlayer dielectric layer 320 in the process of forming the device gate structure, thereby being beneficial to guaranteeing the performance of the semiconductor structure.
In this embodiment, the device gate structure is a metal gate structure.
Specifically, the device gate structure comprises a gate dielectric layer covering the channel protruding portion and a gate electrode layer located on the gate dielectric layer.
In this embodiment, the gate dielectric layer comprises hafnium oxide (HfO 2 ) Zirconium dioxide (ZrO) 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), zirconium hafnium oxide (HfZrO), aluminum oxide (Al) 2 O 3 ) Silicon oxide (SiO) 2 ) And lanthanum oxide (La) 2 O 3 ) One or more of the following; one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminum (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC) as materials of the gate electrode layer.
In other embodiments, the device gate structure may also be a polysilicon gate structure, depending on the process requirements.
Fig. 7 to 8 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: the sacrificial layer is formed by a modification treatment.
Referring to fig. 7 and 8 in combination, the step of converting a portion of the thickness of the interlayer dielectric material layer 301 into a sacrificial layer 311 includes: the interlayer dielectric material layer 301 higher than the top of the gate structure 201 is modified to form a sacrificial layer 311, and the etching resistance of the sacrificial layer 311 is smaller than that of the interlayer dielectric material layer 301.
In this embodiment, the sacrificial layer 311 is obtained by modifying, and the etching resistance of the sacrificial layer 311 is smaller than that of the interlayer dielectric material layer 301, so that the sacrificial layer 311 is easy to remove, and damage to the interlayer dielectric material layer 301 is reduced in the process of removing the sacrificial layer 311.
It should be noted that, in this embodiment, the sacrificial layer 311 is obtained by adopting a modification process, and the sacrificial layer 311 with a larger thickness can be obtained by controlling the process parameters in the modification process, so that the interlayer dielectric material layer 301 higher than the top of the gate structure 201 can be completely removed by adopting a thinning process to form the interlayer dielectric layer 321, which is beneficial to improving the process efficiency and saving the process cost.
It should be noted that the etching selectivity of the sacrificial layer 311 to the interlayer dielectric material layer 301 is not too small. If the etching selection ratio of the sacrificial layer 311 to the interlayer dielectric material layer 301 is too small, the interlayer dielectric material layer 301 is easily damaged during the process of removing the sacrificial layer 311, so that the top flatness of the formed interlayer dielectric layer 321 is poor, and the subsequent manufacturing of the semiconductor structure is affected. For this reason, in the present embodiment, the etching selectivity ratio of the sacrificial layer 311 to the interlayer dielectric material layer 301 is greater than or equal to 10.
In this embodiment, the modification process includes a plasma bombardment process.
The interlayer dielectric material layer 301 can be modified more efficiently by adopting a plasma bombardment process, and the sacrificial layer 311 with smaller etching resistance is obtained.
In this embodiment, the gas used in the plasma bombardment process comprises hydrogen (H 2 ) Or helium (He).
By H 2 Or He performs plasma bombardment process on the interlayer dielectric material layer 301, and the H or He has smaller atomic radius and can be used in a single processDoping and vacancy effects are generated in the interlayer dielectric material layer 301 with the fixed depth, so that the sacrificial layer 311 with smaller etching resistance is formed.
In this embodiment, the step of removing the sacrificial layer 311 includes: the sacrificial layer 311 is removed by an etching process.
In this embodiment, the etching resistance of the sacrificial layer 311 is smaller than that of the interlayer dielectric material layer 301, so that the sacrificial layer 311 can be removed by etching treatment, the process is simple and easy to operate, and damage to the interlayer dielectric material layer 301 can be reduced in the process of removing the sacrificial layer 311.
In this embodiment, the etching process includes a wet etching process.
The wet etching process has relatively low cost and simple operation steps, can realize a larger etching selection ratio, and is beneficial to reducing the damage to the interlayer dielectric material layer 301 in the process of removing the sacrificial layer 311.
In this embodiment, the etching solution of the wet etching process includes hydrofluoric acid.
The hydrofluoric acid solution is adopted, so that the sacrificial layer 311 can be removed more efficiently, the damage to the interlayer dielectric material layer 301 can be ensured to be smaller, and the interlayer dielectric layer 321 with higher quality can be formed.
The specific description of the forming method in this embodiment may be combined with the corresponding description in the foregoing embodiment, and will not be repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is formed on the substrate, and an interlayer dielectric material layer covering the grid structure is also formed on the substrate;
thinning the interlayer dielectric material layer higher than the top of the gate structure for one or more times, removing the interlayer dielectric material layer higher than the top of the gate structure, and reserving the interlayer dielectric material layer covering the side wall of the gate structure as an interlayer dielectric layer, wherein the thinning comprises the following steps: converting the interlayer dielectric material layer with partial thickness into a sacrificial layer; and removing the sacrificial layer.
2. The method of forming a semiconductor structure of claim 1, wherein converting a portion of the thickness of the interlayer dielectric material layer into a sacrificial layer comprises: carrying out chemical reaction treatment on the interlayer dielectric material layer to convert part of the interlayer dielectric material layer into the sacrificial layer, wherein the sacrificial layer is a volatile material;
the step of removing the sacrificial layer includes: and carrying out heating treatment on the sacrificial layer to volatilize the sacrificial layer.
3. The method of forming a semiconductor structure of claim 2, wherein in the step of performing a chemical reaction process on the interlayer dielectric material layer, the chemical reaction process comprises: and reacting the plasma generated by adopting fluorocarbon-based gas with the interlayer dielectric material layer.
4. The method of forming a semiconductor structure of claim 3, wherein the fluorocarbon-based gas comprises one or more of carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane.
5. The method of forming a semiconductor structure of claim 3, wherein the material of the sacrificial layer comprises ammonium hexafluorosilicate.
6. The method of forming a semiconductor structure according to claim 2, wherein in the step of performing a heat treatment on the sacrificial layer, the process of the heat treatment includes: and (5) infrared heat treatment.
7. The method of forming a semiconductor structure according to claim 2, wherein in the step of performing heat treatment on the sacrificial layer, the temperature of the heat treatment is 150 ℃ to 300 ℃, and the time of the heat treatment is 2s to 30s.
8. The method of forming a semiconductor structure of claim 1, wherein converting a portion of the thickness of the interlayer dielectric material layer into a sacrificial layer comprises: modifying the interlayer dielectric material layer higher than the top of the gate structure to form the sacrificial layer, wherein the etching resistance of the sacrificial layer is smaller than that of the interlayer dielectric material layer;
the step of removing the sacrificial layer includes: and removing the sacrificial layer through etching treatment.
9. The method of claim 8, wherein an etch selectivity of the sacrificial layer to the interlayer dielectric material layer is greater than or equal to 10.
10. The method of forming a semiconductor structure of claim 8, wherein the process of modifying comprises a plasma bombardment process.
11. The method of claim 10, wherein the gas used in the plasma bombardment process comprises hydrogen or helium.
12. The method of forming a semiconductor structure of claim 8, wherein the etching process comprises a wet etching process.
13. The method of forming a semiconductor structure of claim 12, wherein the etching solution of the wet etching process comprises hydrofluoric acid.
14. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the gate structure is a dummy gate structure;
after the interlayer dielectric material layer is thinned, the forming method further comprises the following steps: removing the pseudo gate structure to form a gate opening surrounded by the interlayer dielectric layer;
and forming a device gate structure in the gate opening.
15. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the material of the interlayer dielectric material layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
16. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, a channel bump is further formed on the substrate, and the gate structure spans the channel bump and covers a portion of a top and a portion of a sidewall of the channel bump.
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