CN117637477A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN117637477A CN117637477A CN202210960929.3A CN202210960929A CN117637477A CN 117637477 A CN117637477 A CN 117637477A CN 202210960929 A CN202210960929 A CN 202210960929A CN 117637477 A CN117637477 A CN 117637477A
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- 238000000034 method Methods 0.000 title claims abstract description 130
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 239000010410 layer Substances 0.000 claims abstract description 192
- 230000008569 process Effects 0.000 claims abstract description 101
- 238000005468 ion implantation Methods 0.000 claims abstract description 70
- 239000011241 protective layer Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 22
- 239000006117 anti-reflective coating Substances 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 7
- 238000009499 grossing Methods 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 239000011368 organic material Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 2
- 230000008093 supporting effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 18
- 150000002500 ions Chemical class 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 229910001423 beryllium ion Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a to-be-doped layer, and a mask layer covering part of the to-be-doped layer is formed on the substrate; forming a protective layer on the top and the side wall of the mask layer; and after the protective layer is formed, carrying out ion implantation on the layer to be doped, which is exposed by the mask layer, and forming a doped region in the layer to be doped. The protective layer plays a role in fixedly supporting the mask layer, correspondingly, the probability of deformation of the appearance of the mask layer is greatly reduced, and meanwhile, the probability of deformation of the appearance of the mask layer is greatly reduced, so that the region needing ion implantation in the to-be-doped layer can be fully exposed, the region needing ion implantation is not covered, the process window of ion implantation is increased, and the performance of the semiconductor structure is improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the increase in the integration level of semiconductor devices, the critical dimensions of transistors have been reduced, which means that a greater number of transistors can be arranged on a chip, thereby improving the performance of the devices. However, as the transistor size is drastically reduced, the gate dielectric thickness and the operating voltage cannot be changed accordingly, which increases the difficulty of suppressing the short channel effect, and thus increases the channel leakage current of the transistor.
To further reduce the impact of short channel effects on the semiconductor structure, channel leakage current is reduced. One method is to perform anti-punch-through implantation on the bottom of the fin portion through a Hot ion implantation (Hot IMP) process, so that the possibility of drain-source punch-through is reduced, and the short channel effect is reduced.
However, the performance of semiconductor structures remains to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to further improving the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a to-be-doped layer, and a mask layer covering part of the to-be-doped layer is formed on the substrate; forming a protective layer on the top and the side wall of the mask layer; and after the protective layer is formed, carrying out ion implantation on the layer to be doped, which is exposed by the mask layer, and forming a doped region in the layer to be doped.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method for forming a semiconductor structure, which comprises providing a substrate, wherein the substrate comprises a layer to be doped, a mask layer covering part of the layer to be doped is formed on the substrate, a protective layer is formed on the top and the side wall of the mask layer, the shape of the protective layer is not easy to deform in the subsequent ion implantation process of the layer to be doped exposed by the mask layer, the protective layer plays a role of fixedly supporting the mask layer, correspondingly, the probability of deformation of the shape of the mask layer is greatly reduced, and meanwhile, the probability of deformation of the shape of the mask layer is greatly reduced, so that the region needing ion implantation in the layer to be doped can be completely exposed, and the region needing ion implantation is not covered, thereby increasing the process window of ion implantation and further improving the performance of the semiconductor structure.
Drawings
FIGS. 1-2 are schematic diagrams illustrating steps of a semiconductor structure;
fig. 3 to 9 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.
Fig. 1 to 2 are schematic structural views corresponding to each step of a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes a layer to be doped 10, and a mask layer 11 is formed on the substrate to cover a portion of the layer to be doped 10.
Referring to fig. 2, the to-be-doped layer 10 exposed from the mask layer 11 is ion-implanted to form a doped region 15 in the to-be-doped layer 10.
The process of ion implantation on the to-be-doped layer 10 exposed from the mask layer 11 includes a thermal ion implantation process, and the process temperature of the thermal ion implantation process is higher than room temperature.
According to the research, in the process of carrying out ion implantation on the to-be-doped layer 10 exposed out of the mask layer 11 by adopting a thermal ion implantation process, the process temperature is higher, the mask layer 11 is easy to deform under the condition of higher process temperature, and correspondingly, the mask layer exposes the region which does not need to be subjected to ion implantation in the to-be-doped layer, so that the probability of doping the region which does not need to be subjected to ion implantation in the to-be-doped layer is increased, and the performance of the semiconductor structure is further influenced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a layer to be doped, and a mask layer covering part of the layer to be doped is formed on the substrate; forming a protective layer on the top and the side wall of the mask layer; and after the protective layer is formed, carrying out ion implantation on the layer to be doped exposed from the mask layer, and forming a doped region in the layer to be doped.
The embodiment of the invention provides a method for forming a semiconductor structure, which comprises providing a substrate, wherein the substrate comprises a layer to be doped, a mask layer covering part of the layer to be doped is formed on the substrate, a protective layer is formed on the top and the side wall of the mask layer, the shape of the protective layer is not easy to deform in the subsequent process of carrying out ion implantation on the layer to be doped exposed by the mask layer, the protective layer has a fixed supporting effect on the mask layer, the probability of deformation of the shape of the mask layer is correspondingly greatly reduced, and meanwhile, the probability of deformation of the shape of the mask layer is greatly reduced, so that the region to be subjected to ion implantation in the layer to be doped can be completely exposed without covering the region to be subjected to ion implantation, thereby increasing the process window of ion implantation and further improving the performance of the semiconductor structure.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 9 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3 to 5, a substrate is provided, the substrate includes a layer to be doped 100, and a mask layer 103 is formed on the substrate to cover a portion of the layer to be doped 100.
In this embodiment, the substrate provides a process platform for subsequent processing.
According to various performance requirements of the semiconductor process, the layer to be doped 100 includes a fin or a source/drain doped region.
As an example, the layer to be doped 100 is a fin. In other embodiments, the layer to be doped is a source-drain doped region, and the source-drain doped region is doped subsequently to further increase the doping concentration of the source-drain doped region, so as to meet the requirement of device performance.
The mask layer 103 protects the region of the layer to be doped 100, which does not need to be ion-implanted, and reduces the risk of doping the region of the layer to be doped 100, which does not need to be ion-implanted, in the subsequent step of ion-implanting the layer to be doped 100 exposed by the mask layer 103.
In this embodiment, the material of the mask layer 103 includes an organic material.
It should be noted that, in the subsequent ion implantation process of the layer to be doped 100 exposed from the mask layer 103, doped ions are not easy to pass through the organic material, that is, the organic material has the function of blocking the penetration of doped ions, and accordingly, the mask layer 103 protects the region of the layer to be doped 100 where the ion implantation is not required.
In this embodiment, the material of the mask layer 103 includes one or both of photoresist and bottom anti-reflective coating (BARC) material. As an example, the mask layer 103 has a stacked structure, and the material of the mask layer 103 includes photoresist and a bottom anti-reflective coating material, specifically includes a bottom anti-reflective coating and a photoresist layer on the bottom anti-reflective coating.
In particular, the bottom anti-reflection coating material is beneficial to improving the pattern precision after exposure, so that the region of the to-be-doped layer 100, which does not need ion implantation, can be accurately protected. Meanwhile, after the ion implantation is performed on the to-be-doped layer 100 exposed by the mask layer 103, the mask layer 103 needs to be removed, the photoresist and the bottom anti-reflection coating are both organic materials, and the hardness of the photoresist and the bottom anti-reflection coating is softer, so that the mask layer 103 can be removed cleanly, and the to-be-doped layer 100 (such as a fin part) is fully exposed, thereby facilitating the subsequent semiconductor process.
In this embodiment, the step of forming the mask layer 103 includes: forming a mask material layer (not shown) on a substrate; the masking material layer is patterned and a masking layer 103 is formed over the substrate to cover a portion of the layer to be doped 100.
Specifically, the mask material layer includes a bottom anti-reflective coating layer 102 and a photoresist layer 101 on top of the bottom anti-reflective coating layer 102, and the patterned mask material layer includes a patterned photoresist layer 101 and a patterned bottom anti-reflective coating layer 102.
In this embodiment, the process of patterning the mask material layer includes one or more of a dry etching process and a photolithography process. As an example, since the mask material layer includes the bottom anti-reflective coating 102 and the photoresist layer 101 on top of the bottom anti-reflective coating 102, the process of patterning the photoresist layer 101 includes a photolithography process and the patterning the bottom anti-reflective coating 102 includes a dry etching process.
Referring to fig. 6, the surface of the mask layer 103 is smoothed.
It should be noted that, the surface of the mask layer 103 is subjected to smoothing treatment, so that the surface morphology of the mask layer 103 is smoother and smoother, correspondingly, in the subsequent process of forming the protective layer, the difficulty of depositing the protective layer on the top and the side wall of the mask layer 103 is reduced, the top and the side wall of the mask layer 103 can be covered by the subsequently formed protective layer, and correspondingly, the subsequent process window for ion implantation of the to-be-doped layer 100 exposed by the mask layer 103 is increased.
In this embodiment, the process of smoothing the profile of the mask layer 103 includes a plasma treatment process.
The profile of the mask layer 103 is subjected to smoothing treatment by adopting a plasma treatment process, so that free radicals containing argon atoms or hydrogen atoms are easy to generate, and the free radicals containing argon atoms or hydrogen atoms and organic matters on the surface of the mask layer 103 are subjected to softer physical and chemical reactions, so that the surface of the mask layer 103 is smoother after being treated by the plasma treatment process.
It should be noted that the bias power should not be too large or too small. If the bias power is too large or too small, the surface of the mask layer 103 is not smooth enough easily in the process of smoothing the surface of the mask layer 103, the roughness of the surface of the mask layer 103 is increased, and correspondingly, the difficulty in depositing the protective layer on the top surface and the side wall of the mask layer 103 is increased, so that the fixing and supporting effect of the protective layer on the mask layer 103 is influenced, and the performance of the semiconductor structure is further influenced. For this reason, in the present embodiment, the bias power is 500W to 5000W.
In this embodiment, the dc voltage in the plasma processing process is negative, specifically, when the dc voltage is negative, the free ions containing positive charges are attracted by the upper electrode plate, so as to reduce physical bombardment on the surface of the mask layer 103, thereby being beneficial to further improving the roughness of the surface profile of the mask layer 103 and enabling the surface morphology of the mask layer 103 to be smoother and smoother.
It should be noted that the dc voltage should not be too large or too small. If the dc voltage is too large or too small, the surface roughness of the mask layer 103 is not improved, which increases the difficulty in depositing a protective layer on top and side walls of the mask layer 103. For this purpose, in this embodiment, the DC voltage is from-50V to-300V.
In this embodiment, the reaction gas includes Ar and H in the plasma treatment process 2 One or two of them.
Specifically Ar and H 2 The method is used for generating free radicals containing argon atoms or hydrogen atoms in a plasma treatment process, the polarity of the free radicals is low, and the damage to the surface of the mask layer 103 is small, so that the roughness of the surface of the mask layer 103 can be effectively improved, and the surface profile of the mask layer 103 is smooth.
Referring to fig. 7, a protective layer 107 is formed on top of and sidewalls of the mask layer 103.
It should be noted that, the protection layer 107 is formed on the top and the side wall of the mask layer 103, in the subsequent ion implantation process of the layer to be doped 100 exposed by the mask layer 103, the shape of the protection layer 107 is not easy to deform, so that the protection layer 107 has a fixed supporting function on the mask layer 103, accordingly, the probability of deforming the shape of the mask layer 103 is greatly reduced, meanwhile, the probability of deforming the shape of the mask layer 103 is greatly reduced, so that the region to be ion implanted in the layer to be doped 100 can be completely exposed, and the region to be ion implanted is not required to be covered, thereby improving the process window of ion implantation and further improving the performance of the semiconductor structure.
Specifically, the subsequent ion implantation process for the layer to be doped 100 exposed by the mask layer 103 includes a thermal ion implantation process, so that the protection layer 107 protects the mask layer 103, during the thermal ion implantation process, the morphology of the mask layer 103 is better improved, the probability of material shrinkage is lower, and the occurrence of material deformation of the mask layer 103 under thermal conditions is favorably inhibited, thereby increasing the process window of the thermal ion implantation process (for example, the process temperature of the thermal ion implantation process can be increased while increasing the doping amount of the thermal ion implantation process).
In this embodiment, the process of forming the protective layer 107 includes a sputter deposition process.
It should be noted that, the thickness of the protective layer 107 formed by the sputtering deposition process is relatively thin, so that the process window for performing the ion implantation on the to-be-doped layer 100 exposed by the mask layer 103 is less affected, and meanwhile, in the process of removing the protective layer 107, the process difficulty of removing the protective layer 107 is reduced.
In this embodiment, the material of the protective layer 107 includes one or more of amorphous silicon, silicon oxide, and silicon oxycarbide
Specifically, the amorphous silicon, the silicon oxide and the silicon oxycarbide are all inorganic materials, and in the subsequent ion implantation process of the to-be-doped layer 100 exposed by the mask layer 103, the inorganic materials have the characteristic of high temperature resistance, so that the inorganic materials are not easy to deform, and correspondingly, the protective layer 107 plays a role in fixedly supporting the mask layer 103.
The thickness of the protective layer 107 should not be too large or too small. If the thickness of the protective layer 107 is too large, the difficulty of the subsequent process for removing the protective layer 107 is increased, so that the process efficiency for removing the protective layer 107 is reduced, and the process of the semiconductor structure is influenced; if the thickness of the protective layer 107 is too small, the effect of the protective layer 107 on the fixed support of the mask layer 103 is easily affected, the probability of deformation of the protective layer 107 is increased, and correspondingly, the probability of deformation of the mask layer 103 is greatly improved, so that the region which does not need to be subjected to ion implantation is exposed, the risk of doping the region which does not need to be subjected to ion implantation is increased, and the performance of the semiconductor structure is affected. For this reason, in the present embodiment, the thickness of the protective layer 107 is 0.3 nm to 3 nm.
Referring to fig. 8, after the protective layer 107 is formed, ion implantation is performed on the layer to be doped 100 exposed by the mask layer 103, and a doped region 108 is formed in the layer to be doped 100.
The doped region 108 is used to meet various process requirements according to various performance requirements of the semiconductor process, and in this embodiment, the ion implantation includes lightly doped drain ion implantation (Lightly Doped Drain, LDD).
As can be seen from the foregoing, the embodiment takes the layer to be doped 100 as the fin portion as an example, so that the lightly doped drain ion implantation is performed on the fin portion, which is beneficial to preventing short channel effect, reducing the probability of occurrence of channel leakage current effect between the source and the drain, and simultaneously, is beneficial to reducing the generation of hot carrier effect.
For this reason, in the present embodiment, the doped region 108 is a lightly doped region 108.
In this embodiment, the process of ion implantation on the layer to be doped 100 exposed from the mask layer 103 includes a thermal ion implantation process, and the process temperature of the thermal ion implantation process is higher than room temperature.
It should be noted that, the thermal ion implantation process is used to implant ions into the layer to be doped 100 exposed from the mask layer 103, the process temperature of the thermal ion implantation process is higher than room temperature, and the thermal ion implantation process can repair the damage of the layer to be doped 100 during the implantation process.
For example, in the case where the layer to be doped 100 is a fin, damage to the fin can be repaired, thereby reducing the probability of affecting the mobility of carriers in the fin. The width of the fin portion is generally smaller, the risk of damage to the fin portion in the ion implantation process is increased, the fin portion is used for providing a channel for device operation, the influence of the quality of the fin portion on the device performance is large, and therefore the thermal ion implantation process is conducted on the fin portion, and the effect of improving the device performance is good.
It should be further noted that, increasing the dopant amount of the ion implantation easily increases the damage probability of the layer to be doped 100, and correspondingly, by adopting the thermal ion implantation process, the process requirement of higher dopant amount can be satisfied while the damage probability of the layer to be doped 100 is reduced. For example, in this embodiment, the ion implantation is a lightly doped drain ion implantation, and by adopting a thermal ion implantation process, it is beneficial to reduce the probability of generating hot carrier effect, channel leakage current effect and short channel effect by increasing the doping amount.
In this embodiment, the process temperature of the thermal ion implantation process is higher than the room temperature, which refers to the room temperature of the processing shop, and the room temperature is 20 ℃ to 30 ℃.
In the process of the thermal ion implantation, the implantation energy range should not be too large or too small. If the implantation energy range is too large, the depth of the doped region 108 formed in the layer to be doped 100 is too large, so that the formed region of the doped region 108 cannot meet the process requirement, the effect of preventing the short channel effect, which is played by the doped region 108, is reduced, and the performance of the semiconductor structure is affected; if the implantation energy is too small, the concentration of the dopant ions in the doped region 108 is easily reduced, so that hot carrier effect is easily generated due to the reduced concentration of the dopant ions, and the probability of occurrence of channel leakage current effect between the source and the drain is increased, thereby influencing the performance of the semiconductor structure. For this reason, in the present embodiment, the implantation energy ranges from 10kev to 100kev during the thermal ion implantation process.
It should be noted that, during the thermal ion implantation process, the process temperature range should not be too large or too small. If the process temperature is too high, the effect of the protection layer 107 on the fixed support of the mask layer 103 is easily affected, so that the probability of deformation of the shape of the mask layer 103 is increased; if the process temperature is too low, the dosage of the doped ions in the process of the thermal ion implantation process is limited, and the process requirements cannot be met, for example, the dosage of the doped ions is reduced, so that hot carrier effect is easy to generate, the probability of occurrence of channel leakage current effect between the source and the drain is increased, and the performance of the semiconductor structure is affected. For this reason, in the present embodiment, the process temperature ranges from 20 ℃ to 200 ℃ during the thermal ion implantation process.
Referring to fig. 9, after ion implantation is performed on the to-be-doped layer 100 exposed by the mask layer 103, the method for forming a semiconductor structure further includes: the protective layer 107 and the mask layer 103 are removed.
Specifically, the protection layer 107 and the mask layer 103 are removed to provide a process basis for a subsequent semiconductor manufacturing process.
In this embodiment, the process of removing the protective layer 107 and the mask layer 103 includes one or both of an ashing process and a wet etching process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a to-be-doped layer, and a mask layer covering part of the to-be-doped layer is formed on the substrate;
forming a protective layer on the top and the side wall of the mask layer;
and after the protective layer is formed, carrying out ion implantation on the layer to be doped, which is exposed by the mask layer, and forming a doped region in the layer to be doped.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the mask layer comprises an organic material.
3. The method of forming a semiconductor structure of claim 2, wherein the material of the mask layer comprises one or both of a photoresist and a bottom antireflective coating material.
4. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the protective layer: and carrying out smoothing treatment on the surface of the mask layer.
5. The method of forming a semiconductor structure of claim 4, wherein the process of smoothing the profile of the mask layer comprises a plasma treatment process.
6. The method of forming a semiconductor structure of claim 5, wherein the parameters of the plasma processing process comprise: bias power 500W to 5000W; the direct current voltage is-50V to-300V; the reaction gas includes Ar and H 2 One or two of them.
7. The method of forming a semiconductor structure of claim 1, wherein the process of forming the protective layer comprises a sputter deposition process.
8. The method of forming a semiconductor structure of claim 1, wherein the material of the protective layer comprises one or more of amorphous silicon, silicon oxide, and silicon oxycarbide.
9. The method of forming a semiconductor structure of claim 1, wherein the protective layer has a thickness of 0.3 nm to 3 nm.
10. The method of claim 1, wherein the layer to be doped comprises a fin or a source drain doped region.
11. The method of claim 10, wherein the layer to be doped is a fin and the ion implantation comprises lightly doped drain ion implantation.
12. The method of forming a semiconductor structure of claim 1, wherein forming the mask layer comprises: forming a mask material layer on the substrate; and patterning the mask material layer, and forming a mask layer covering part of the layer to be doped on the substrate.
13. The method of forming a semiconductor structure of claim 12, wherein patterning the masking material layer comprises one or more of a dry etching process and a photolithography process.
14. The method of claim 1, 2, 3, 10 or 11, wherein the ion implantation process for the layer to be doped exposed by the mask layer comprises a thermal ion implantation process, wherein the process temperature of the thermal ion implantation process is higher than room temperature.
15. The method of forming a semiconductor structure of claim 14, wherein the process parameters of the thermal ion implantation process comprise: the implantation energy ranges from 10kev to 100kev; the process temperature ranges from 20 ℃ to 200 ℃.
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