CN1175837A

CN1175837A - High- and low-speed code rate conversion circuit

Info

Publication number: CN1175837A
Application number: CN 96109563
Authority: CN
Inventors: 陈文放; 张新民; 何调元; 徐卫; 李宏超; 潘云生
Original assignee: TECH SAFETY INST SECRETS COMMITTEE PLA
Current assignee: TECH SAFETY INST SECRETS COMMITTEE PLA
Priority date: 1996-08-30
Filing date: 1996-08-30
Publication date: 1998-03-11
Anticipated expiration: 2016-08-30
Also published as: CN1061805C

Abstract

A VLS IC for high-speed or low-speed code rate conversion in digital communication system is composed of time interval pulses generating module, 2Mbps to 64 Kbps conversion module, synchronous transform module, direction change selection module and I/O module. All circuits are integrated in one FPGA VLS IC, which can divide primary group E1 into 32 zero-order groups E0 or merge 32 zero-order groups E0 into one primary group E1.

Description

Low speed code rate conversion circuit at a high speed,

The invention belongs to the design field of very lagre scale integrated circuit (VLSIC) in the digital communication, specially refer to shunt and the circuit design of closing the road in the PCM pulse code modulation communication.

In digital communications network, in order to make full use of the transmission of circuit, and, will in communication network, carry out rate conversion for the grouping in communicating by letter and the needs of maintaining secrecy, or with the primary group E in the signal ₁, 2.048 mbit/(being called for short 2Mbps) are divided into 32 zero degree group E ₀(64kbps); Or with 32 tunnel zero degree group E ₀Be combined into one road primary group E ₁Circuit.

In present existing technology, this similar shunt, close the road circuit and mainly have following several defective: one, by in polymorphic type, a plurality of chips, small scale integrated circuit formed, its volume is big, power consumption is high, poor reliability and price are expensive; Two, system is incomplete, particularly at primary group E ₁Be divided into E ₀The time, output is no more than 10 the tunnel, is not whole outputs, brings many inconvenience to application; Three, also do not see 32 road E up to now ₀Synthesize one road E ₁Circuit and equipment thereof come into operation; Four, in circuit design, with close the road and along separate routes two kinds of speed conversions be chosen in the circuit of realizing on a slice IC chip by control and also do not see.In view of the foregoing, just wish to design more advanced, complete, multiple functional circuit, satisfy the transmission requirement in the digital communications network.

Purpose of the present invention is exactly on a slice VLSI (very large scale integrated circuit) chip, utilizes the mode of FPGA (FieldProqrammable Gate Array is a field programmable gate array), finishes primary group E ₁Divide to 32 tunnel zero degree group E ₀, or with 32 road reversal E ₀Be combined into one road E ₁Thereby, carry out effective signal transmission.

The present invention relies on following technical proposals to realize, the integrated circuit of a kind of high speed of numeral, low speed rate conversion, it is characterized in that circuit inside connects a conversion module by 2Mbps 64Kbps (2), synchronous conversion module (3) and direction transformation by time-gap pulsing generation module (1) and selects module (4), be connected to input/output module (5), constitute the FPGA internal circuit configuration.

According to the 2MHZ clock and the 8KHZ frame synchronizing signal of input, form zero phase (0 °) and π 64KHZ mutually by time-gap pulsing generation module (1), produce 32 time slot sign pulse Ti simultaneously, i=0,1 ..., 31, be used for indicating and selection E ₁In 32 time slot TSi, i=0,1 ..., 31; 2Mbps → 64Kbps conversion module (2) is selected each road from importing the E1 of PCM32 road at a high speed, becomes 32 road E ₀Signal is perhaps by reversal 32 road E ₀Signal synthesizes one road E ₁Signal output; Conversion module (3) is that output signal is carried out Synchronous Processing synchronously, and with zero phase, π is half and half 32 road E mutually ₀Output is concentrated in the unification that becomes homophase; Change direction and select module mainly the input and output two-way signaling to be selected, determine this circuit or realize that 2Mbps is divided into 32 road 64Kbps, or realize that 32 road 64Kbps are combined into the conversion of one road 2Mbps; Input/output module (5) is to determine that the input/output signal of this circuit is Transistor-Transistor Logic level or CMOS level, and solves the compatibling problem of the two.

Further specify embodiment below in conjunction with accompanying drawing:

Description of drawings:

Fig. 1 be the present invention along separate routes/close the theory diagram on road;

Fig. 2 is the circuit distribution map of time slot sign pulse generation module;

Fig. 3 is TS4n, TS4n+1, and n=0,1 ..., 8, the branch of the 2Mbps 64Kbps of totally 16 time slots/close road circuit, (direction transformation circuit be also included within).

Fig. 4 is TS4n+2, TS4n+3, and n=0,1 ..., 8 branch of the 2Mbps 64Kbps of totally 16 time slots/close road circuit, (direction transformation circuit be also included within).

Fig. 5 is a sequential chart;

Fig. 6 is complete embodiment circuit diagram.

In Fig. 1, clearly show allomeric function of the present invention and structural framing, S is the function selecting end, and S=0 represents circuit of the present invention for closing the road, and S=1 represents that circuit of the present invention is shunt.When S=1 divides under the line state, input signal is digital pcm 32 road E1 signals of 2Mbps, 2MZ clock, 8KHZ frame synchronizing signal, output zero phase 64KHZ clock and 32 tunnel synchronous 64Kbps data-signals.When S=0 closes under the line state, be input as 2MHZ clock, 8KHZ synchronously and 32 road 64Kbps data-signals, zero phase 64KHZ clock is an output signal, is produced by circuit of the present invention, 2Mbps is an output signal.

In Fig. 2, shown the time slot sign pulse-generating circuit, it comprises two four counter, the 3-8 decoder of four positive arteries and veins outputs, this circuit common property is given birth to 32 time-gap pulsings, produces the clock of 64KHZ simultaneously, the frame synchronization of its input 2MHZ clock and 8KHZ, C16BARD) four digit counters that trigger for trailing edge, WF-138 is the improvement of 74LS138, it is output as positive pulse.

In Fig. 3, represent a kind of branch/close the road circuit, it is one of core circuit of the present invention, and it is comprising one 8 bit shift register, connect four triple gates, a bi-directional pin, and two with the door, a NOR gate, when S=1, it realizes the shunt speed conversion of 2Mbps 64Kbps, when S=0, that realizes 64Kbps → 2Mbps closes road speed conversion, TS4n, TS4n+1, n=0,1 ... 8, have 16 time slots and all reuse identical circuit, do not repeat among the figure to draw, RS8 is eight grades of shift registers.This figure operation principle is: when S=1, at the TS4n or the TS4n+1 time slot of every frame, the clock of shift register is the non-of 2MHZ clock; Non-TS4n or TS4n+1 time slot, the clock of shift register is the non-of 64KHZ clock, the clock that is shift register is the mix clock that 2MHZ and 64KHZ form, utilize mix clock, can be with the data of TS4n or TS4n+1, write in 8 bit shift register at a high speed, after TS4n or the TS4n+1 time slot, with the 64KHZ clock data in 8 bit shift register are read successively from the Q7 end again.

When S=0, its course of work is similar with S=1, but conversion is opposite, non-TS4n or TS4n+1 time slot, mix clock writes low speed data in 8 bit shift register, TS4n or TS4n+1 time slot, with the non-of 2MHZ clock the data in 8 grades of shifting memories are read at a high speed from the Q8 end, note, when having only TS4n or TS4n+1, with door IC35 triple gate IC10 is opened, at this moment, M point place signal is the data of TS4n or TS4+1, At All Other Times, triple gate IC10 closes, and M point signal is the data of other time slot.

The described circuit of Fig. 4, it also is one of core circuit of the present invention, this figure compares with Fig. 3, substantially similar, it comprises the three identical parts with figure, promptly one eight bit shift register, four triple gates, bi-directional pin, two with door and a NOR gate, in addition, increase by two triple gates, a trigger.On function, their difference is that the 64KHZ clock of mix clock is the π phase, just because of this, no matter is along separate routes or closes the road, has all increased phase-adjusting circuit, i.e. d type flip flop FDC.In addition, when closing the road, low speed 64Kbps speed data is adjusted by the FDC phase place earlier, and low speed writes 8 grades of shift registers again, when T4+2 or TS4n+3, utilizes the 2MHZ clock, and the data high-speed in the shift register is read.

Fig. 5 represents the sequential chart of circuit of the present invention, the signal of 2Mbps and the relation of clock, the data-signal of 64Kbps are to be output as the π phase from this circuit, and the 64Kbps signal of importing when closing the road is zero phase, be the reversal signal, 64KHZ zero phase clock is provided by circuit of the present invention.

Fig. 6 represents a kind of embodiment of circuit of the present invention, IPAD is the pin of input signal among the figure, OPAD is the pin of output signal, BPAD is the pin of I/O two-way signaling, TBUF and OBUFZ are triple gate, are noted that especially time slot sign pulse generation module is with all time-gap pulsing Ti,=0,1 ... 31 all generate, and two examples have only been drawn in speed conversion, direction transformation and conversion synchronously, do not repeat to spread out to draw, if TSi is 32 road 64Kbps data-signals, i=0,1 ... 31, TS4n is example with TS0, and TS4n+1 is identical with TS4n not to be drawn.TS4n+2 is example with TS4, and TS4n+3 does not draw so that TS4+2 is identical, i.e. the situation of n=0.When n=1, as long as with T4n, T4n+1, T4n+2, T4n+3 replace T0 respectively, T1, T2, T3, TS4n+1, TS4n+2, TS4n+3 replace TS0 respectively, TS1, TS2, TS3 gets final product.

Outstanding feature of the present invention is, with all each several part circuit, all is made in above a slice VLSI chip FPGA-XC3064APC84, realized in the digital pcm communication, with primary group E₁Be divided into 32 zero degree group E₀Or 32 tunnel zero degree group E₀Be combined into one road primary group E₁Circuit, finish at a high speed, the low speed code check Mapping function, ten times of the circuit volume decimals of being realized by a slice FPGA, decades of times in light weight, merit Consumption only has several milliwatts, low price decades of times, and reliability height, and it is safe to use. Performance period is short, Launch is fast.

Claims

1, a kind of high speed of numeral, low speed code rate conversion circuit, constitute by ultra-large circuit integrated chip, it is characterized in that, circuit inside connects the conversion module (2) of a 2Mbps 64Kbps, synchronous conversion module (3) and direction transformation by time-gap pulsing generation module (1) and selects module (4), be connected to input/output module (5), constitute the FPGA internal circuit configuration.

2, according to the described high speed of claim 1, low speed code rate conversion circuit, it is characterized in that, inner time slot sign pulse-generating circuit, it comprises 2 four counter, the 3-8 decoder of four positive pulse outputs.

According to the described high speed of claim 1, low speed code rate conversion circuit, it is characterized in that 3, its inner a kind of branch/close the road circuit comprises one 8 bit shift register, it connects four triple gates, bi-directional pin and two and door, a NOR gate.

4, according to the described high speed of claim 1, low speed code rate conversion circuit, it is characterized in that, inner another kind branch/close road circuit, except comprise one 8 bit shift register, four triple gates, bi-directional pin, two with door and NOR gate, also increase by two triple gates, a d type flip flop.