CN1105791A - Secondary conversion type code flow regulating method and device - Google Patents
Secondary conversion type code flow regulating method and device Download PDFInfo
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Abstract
The present invention belongs to the field of electric communication technology. Said invention puts forward that the conversion of input information code flow to code flow after code speed justification is divided into first conversion of input information code flow to parallel information code word flow and secondary conversion of parallel information code word flow to code flow after code speed justification. The code flow restoration process of its receiving end also is implemented by two-step conversion, and is inverse process of its transmitting end. Said method greatly reduces the operation speed of device, reduces the circuit scale and is favourable for implementing special-purpose chip of synchronous digital series by using CMOS special-purpose integrated circuit. Said invention specially is applicable to justification circuit of snchronous digital series.
Description
The invention belongs to the telecommunication field, particularly the multiplexing technique of digital communication.
At present, digital communication just develops towards big capacity direction, and the synchronous digital hierarchy (SDH) that CCITT (CCITT) proposes is accepted by the whole world.In SDH, two class code speed adjustment technologies have been adopted: positive justification and positive/zero/negative justification.But the difference of following the quasi-synchronous serial justification is the adjustment frame of SDH to be constituted by code word, and every code word is made of 8 bits.The code word that has is by fixed stuff R-Bits, adjusts non information bits such as control bit and service bit and constitutes, and is called the additional overhead code word.The code word that has is to be made of the fix information bit, is called the fix information code word.The code word that has contains the positive justification bit, is called the positive justification code word.The code word that has contains the negative justification bit, is called the negative justification code word.The two is referred to as the adjustment code word again.That adjusts that code word has also contains fix information bit and other bits.As the adjustment code word among the C-4 is the positive justification code word, contains 1 fixed stuff R-Bits of 1 positive justification bit and 6 fix information bits.C-12 contains 1 positive justification code word and 1 negative justification code word, the positive justification code word contains 1 positive justification bit and 7 fix information bits, and the negative justification code word contains 1 negative justification bit and 7 overhead bits when no negative justification requirement, and the negative justification code word does not contain information bit.The fix information code word is referred to as the information code word with the adjustment code word that contains information bit.The code word that does not contain information bit is called non-information code word, comprises the additional overhead code word and does not contain the negative justification code word of information bit.
The justification process is divided into code stream adjustment process and clock adjustment process.The code stream adjustment process is divided into the code stream recovery process of the code stream conversion process and the receiving terminal of transmitting terminal again, and the two is actually the inverse transformation process.Conventional code flow regulating method is to adopt serial logic, presses bit work.The code stream transform method of its transmitting terminal is: the information code current of serial input is read by bit, inserts overhead bits again, and the code stream after the formation justification claims modulated code stream to finish code stream, conversion later on.Its realization block diagram is seen shown in Fig. 1 (a).Input letter sign indicating number (11) writes elastic store under input information clock (12) drives.Justification clock (13) by the pulse of deduction noninformation bit, forms and reads clock (14) in reading clock generation circuit.From elastic store, read letter sign indicating number (15) with reading clock (14), close the road with other overhead bits (16) again, produce modulated code stream (17), finish the code stream conversion.As seen, the code stream conversion is to adopt elastic store one step completed.The code stream restoration methods of its receiving terminal is shown in Fig. 1 (b): the information bit in the modulated code stream (21) is write the elastic store of receiving end by serial under the driving of writing clock, and then pursue bit with the even information clock (24) that recovers and read, recover uniform serial information code stream (25), finish code stream and recover.Write the noninformation bit pulse in the receive clock (22) of clock generation circuit deduction input, produce and write clock (23).As seen, the code stream recovery also is to adopt elastic store one step completed.Because it is work in series that conventional code stream is adjusted circuit, its operating rate equals the speed of modulated code stream; Again because it is can only generally to realize with trigger by organized by bit work thereby used elastic store.
The C-4 interface of synchronous digital hierarchy, stream rate are 140M/s to 155Mb/s, and common CMOS application-specific integrated circuit (ASIC) is difficult to work to this speed; Owing to adopted a large amount of overhead bits in the synchronous digital hierarchy, cause the scale of elastic store very big again, the cost of realization is very high.
Australian Patent AU-A-64538/90, proposing employing is written in parallel in proper order, the elastic storage method that selection is read realizes that code stream conversion and code stream recover, reduced the operating rate of device, the effective information bit is less than code word size in the code word owing to adjust, cause the information bit of the code word of reading to be made up of the different information bits that writes in the code word like this, make elastic store to organize by bit, its scale does not reduce.That is to say that this method has reduced the device operating rate, but do not solve the too big problem of elastic store scale.Fig. 2 shows the read-write process in the elastic store when making in this way.Ablation process is undertaken by code word.Code word Di writes the bit 0 of elastic store to bit 7, and code word Di+1 writes the bit 8 of elastic store to bit 15, and code word Di+2 writes the bit 16 to 23 of elastic store.When reading, Z adjusts code word, and two at its end is non-information code position.Wi, Wi+1 and Wi+2 are the fix information code word.As seen from Figure 2, when reading the fix information code word, read next code word, but read when adjusting code word Z, can only read next code word every 6 every a code word.Like this, elastic store can only can not be operated by the code word that writes by bit work.
The objective of the invention is to overcome existing code quick adjusting method operating rate height, the requirement circuit scale is big, weak points such as device cost height, a kind of new code stream quadratic transformation method is proposed, the code stream restoration methods that comprises the code stream transform method and the receiving terminal of transmitting terminal, and the transmitting terminal device and the receiving end device that adopt this method.Realize to reduce operating rate, reduce circuit scale, be easy to adopt common CMOS application-specific integrated circuit (ASIC) to constitute in the synchronous digital hierarchy plurality of advantages such as code quick adjusting device.
The quadratic transformation method is adopted in the code stream conversion of the transmitting terminal that the present invention proposes, and it is characterized in that may further comprise the steps:
(1). receive the input information code stream with the input information clock;
(2). get the W position from the input information code stream, W is that code word is long, is divided into W road and line output at every turn, constitutes a parallel fix information code word;
(3) when output has the adjustment code word of K information bit, from the input information code stream, take out the K position, be divided into the output of K road and use by the position ordering of information bit in adjusting code word, constitute a parallel adjustment code word;
(4) the fix information code word that step (2) and (3) are produced and adjustment code word that information bit is arranged write elastic store in proper order by the code word beat of input information clock;
(5) the information code byte of pressing justification frame is clapped sense information code word from elastic store, and bat place of non-information code byte is not read, to produce non-information code word;
(6) adjust phase relation between the read-write operation of elastic store, with guarantee justification frame the adjustment code word beat of information bit is arranged the time lucky reading step (4) the adjustment code word that information bit is arranged that writes;
(7) code stream read of step (5), produce the service bit stream that circuit produces and close the road by adjusting adjustment control code that request signal control produces and service bit, form the code stream after the justification, finish the code stream conversion of transmitting terminal.
The code stream that the present invention proposes the receiving terminal of justification recovers to adopt the secondary inverse transform method, it is characterized in that may further comprise the steps:
(1) receives input letter sign indicating number with input clock;
(2) will import the letter sign indicating number and be divided into W road and line output, constitute parallel code word by code word;
(3) the parallel code word that will contain information bit writes elastic store by the code word beat of input clock;
(4) by the beat of the information clock that recovers, read an information code word every J pulse from elastic store, J is the figure place of effective information position in the information code word of reading;
(5) remove noninformation bit in the adjustment code word of step (4) output by the indication of the adjustment control code that receives;
(6) by the beat of the information clock that recovers, the parallel code word that step (5) is exported is merged into definite way output, thereby the code stream of finishing receiving terminal recovers.
Step (1) has constituted the conversion first time of transmitting terminal in the code stream transform method of transmitting terminal of the present invention to step (3).It is transformed into parallel information streams of code words with the input information code stream.Parallel information streams of code words is to be made of parallel fix information code word and the parallel adjustment code word that contains information bit.Step (4) has constituted the conversion second time of transmitting terminal to step (7).It changes parallel information code word rheology into satisfactory modulated code stream.When first time conversion, the adjustment code word that contains information bit is inserted required non information bit, produce the fix information code word and contain the adjustment code word of information bit; When second time conversion, insert the additional overhead code word again and do not contain the adjustment code word of information bit.Like this, during conversion for the second time to the read-write of elastic store all by code word work, thereby its not only available common parallel elastic store realizes, and can realize with the elastic store that RAM constitutes.Because code word speed is low, the scale of the RAM of same memory capacity is little more a lot of than trigger, thereby the quadratic transformation method reduced operating rate, has reduced circuit scale.The main points of this invention are to organize the adjustment code word that contains information bit before writing elastic store, and comprise that the code stream transform method of the prior art of AU-A-4538/90 patent of invention all is to organize to adjust code word after reading from elastic store again.
Code stream after the justification in the code stream transform method of transmitting terminal of the present invention in the input information code stream of step (1) and the step (7) can be the serial code stream of single channel, also can be the parallel code stream of multichannel.The parallel code stream of use can reduce the requirement to the device operating rate.The said code stream transform method of the present invention not only is suitable for positive justification, align/zero/negative justification process also is suitable for.In order to be illustrated more clearly in the said method of the present invention, below we tell about its code stream conversion process with concrete instance.
C-4 interface with SDH is an example, and the input information code stream with the single channel serial is that starting point begins to tell about here.Certainly, as if being that example is told about with multidiameter delay input information code stream, situation also difference is little.Fig. 3 (a) illustrates the code stream figure of serial input information code stream, and numeral wherein just is used to represent the ordinal relation of each information bit, and the bit that numeral is little is gone ahead of the rest the numbering of an information bit of each numeral.Information streams of code words through obtain walking abreast after the code stream conversion first time reduces the speed of service.Parallel way is 8 in this example.Certainly be not limited to branch 8 tunnel, but, divide 8 the tunnel to be best selection from the C-4 interface of SDH.Fig. 3 (b) illustrates the code stream figure of parallel information code word.Bit 1,9,17,25 ... constitute the 1 road code stream, bit 2,10 ... constitute the 2 road code stream, by that analogy, bit 8,16,24 ... constitute the 8 road code stream.An information code word frame is made of 242 information code words, comprises 241 fix information code words and 1 positive justification code word.8 bits of fix information code word are the fix information position all, and the code word cycle is 8 times of input information sign indicating number bit period.The positive justification code word is made of 6 fix information positions, an adjustment position and fixed stuff R-Bits.Do not have when adjustment and adjust the position carry information, then positive justification code word contains 7 information bits, and code word cycle this moment is 7 times of input information sign indicating number bit period.Have when adjustment to adjust not carry information of position, then positive justification code word contains 6 information bits, and code word cycle this moment is 6 times of input information sign indicating number bit period.The position of information bit in adjusting code word be order as shown in the figure.Code stream conversion for the second time is transformed to the parallel modulated code stream shown in Fig. 3 (c), i.e. code stream after the justification with the parallel information streams of code words shown in Fig. 3 (b).POH, W, X and Y represent POH code word, W code word, X code word and Y code word among the figure, all are made of 8 bits.Their general designation additional overhead code words.POH contains 8 service bits, and the W code word contains 8 fix information bits, and the X code word contains one and adjusts control code, 5 fixed stuff R-Bits and 2 service bits.The Y code word contains 8 fixed stuff R-Bits.The Z code word is for adjusting code word.96I represents that there contains 96 information bits, or 12 fix information code words.More as can be known, before and after the code stream conversion, the ordinal relation between each information code word does not change, and has just inserted some additional overhead code words between them for the second time by Fig. 3 (b) and Fig. 3 (c).Because code stream conversion for the second time is based on the code word operation, thereby not only operating rate is low, realizes also simple.During the design specialized circuit, modulated code stream is designed to 8 tunnel parallel code streams suits, but if be designed to single channel serial code stream form, as long as, it is merged into one the tunnel gets final product the closing in the dataway operation of the step (7) of code stream transform method of the present invention.The modulated code flow structure of single channel serial is seen shown in Fig. 3 (d).For convenience of explanation, draw some code word more meticulousr among the figure.Among Fig. 3 (c) and Fig. 3 (d) each code word cycle all identical, by modulated stream rate decision.The structure of the modulated code stream of C-4 interface is derived from CCITT suggestion Fig. 5 .3 G.709.Adjustment control code among Fig. 3 (c) and Fig. 3 (d) and service bit be step of the present invention (7) realize but their position and other filling bits then realize in step (4) to (6).
The C-3 of SDH and C-12 interface all adopt positive/zero/negative justification, adopt code stream conversion process of the present invention similar substantially, and being not difficult derives according to last example.The information streams of code words also is advisable to get 8 tunnel parallel code streams.It should be noted that positive/zero/negative adjustment process contains the positive justification process, negative withering had suffered journey and non-adjustment process.Adjust code word and also be divided into positive justification code word and negative justification code word.When positive justification took place, the parallel information streams of code words did not contain the negative justification code word, only contains fix information code word and positive justification code word, and first bit of positive justification code word is a filling bit, and other are the fix information bit.When not adjusting, the parallel information streams of code words does not contain the negative justification code word yet, only contains fix information code word and positive justification code word, and 8 bits of the positive justification code word of this moment are information bit all.When negative justification took place, the parallel information streams of code words contained positive justification code word and negative justification code word, and 8 bits of the positive justification code word of this moment are information bit all, and preceding 7 bits of negative justification code word are filling bit, and last bit is an information bit.
Adjust request signal and produced by the clock adjustment member, it has exceeded scope of the present invention.In positive justification, adjusting request signal also is the positive justification request signal.Positive justification has taken place in its effective expression, and its invalid representation is not adjusted.In the justification of the C-4 of SDH interface, if it is effective to adjust request signal, K=6 then, otherwise K=7.In positive/zero/negative justification, adjust request signal and divide positive justification request signal and negative justification request signal.The positive justification request signal is effectively indicated generation positive justification, and the negative justification request signal is effectively indicated the generation negative justification, and the two all invalid indication is not adjusted.
The method of adjustment of the phase relation between the read-write operation of elastic store can have multiple.Such as, can adopt the address correspondent method, allow the address of memory cell of each information code word of information code word frame and elastic store keep the corresponding relation of determining.Promptly to elastic store writing information code word the time, each information code word of information code word frame all has the definite address of oneself.Certainly, this corresponding relation can be one to one, also can be a plurality of to one.Read by this corresponding relation when reading.The avoid way and the conventional method of colliding as for the read-write of elastic store are as good as.Again such as, can adopt label method, promptly when writing elastic store, a certain code word of information code word frame is made a specific identifier, a for example additional flag bit can be adjusted the read-write phase place when reading elastic store in view of the above.
The receiving terminal code stream recovery process of justification be the inverse transformation process of code stream conversion of transmitting terminal because that the code stream conversion process of transmitting terminal has been narrated is quite detailed, can understand code stream recovery process with reference to the code stream conversion process of transmitting terminal.
The step (1) to (4) of the code stream restoration methods of receiving terminal of the present invention has constituted the inverse transformation first time that code stream recovers.It removes the additional overhead code word in the justification frame, realizes the inverse transformation of modulated code stream to the parallel information streams of code words.Step (5) to (6) has constituted the inverse transformation second time that code stream recovers.It removes the non information bit in the adjustment code word of parallel information streams of code words, realizes the inverse transformation of parallel information streams of code words to the information code current that recovers.Like this, for the first time during inverse transformation to the read-write of elastic store all by code word work, thereby its not only available common parallel elastic store realizes, and can realize with the elastic store that RAM constitutes.This has not only reduced operating rate, and has reduced circuit scale.Main points of the present invention are to remove the non information bit of adjusting in the code word after reading elastic store again, and comprise that the code stream restoration methods of the prior art of AU-A-64538/90 patent of invention all is the just once task of finishing the non information bit in the adjustment code word of removing non-information code word and information bit being arranged when writing elastic store.
Equally, said input believes that said definite way can be a single channel in sign indicating number and the step (6) in the step (1) of the said code stream restoration methods of the present invention, also can be multichannel.And the said code stream restoration methods of the present invention not only is suitable for positive justification, align/zero/negative justification also is suitable for.The code stream recovery process of the C-4 interface of SDH, C-3 interface and C12 interface only is the inverse process of their code stream conversion processes separately, repeats no more here.The recovery of the information clock of mentioning in the step of said code stream restoration methods (4) and (6) is to be finished by the clock adjustment member, does not tell about here.
The understanding of the long W of code word also can be different in the code stream adjustment, and for example, in SDH, W is generally understood as 8.Like this, deal with also more convenient.But cut apart code word by other figure places, as by 4, neither.
The transmitting terminal device that the code stream that adopts the method for the invention to constitute is adjusted is by timing circuit, controlled code conversion circuit, variable frequency divider, and write address produces circuit, elastic store, read address production electric circuit, adjust control code and produce circuit and close road circuit formation, as shown in Figure 4.Timing circuit produces various time signals under justification clock (43) drives: (44), (45), (47) and (421), use for other each several part circuit.(41) be the information code current of input, (42) are the information clock of input, and for adjusting request signal, (420) select signal for adjusting (48), and (46) are fractional frequency signal, and (49) are for writing synchronizing signal.Variable frequency divider and controlled code conversion circuit are finished code stream conversion for the first time.Variable frequency divider is used to produce the time signal of information code word frame, variable frequency divider is to (42) frequency division, pulse of every information code word output gets (46), and pulse of every frame output gets (49), whenever the pulse of adjustment code word output that contains information bit gets (420).Because information code word frame includes non information bit, but not information bit quantity depends on adjustment request signal (48) again, thereby the work of variable frequency divider will be subjected to (48) control.Controlled code conversion circuit is accepted input information code stream (41) under input information clock (42) drives, be converted to parallel information code word output (410) under fractional frequency signal (46) effect, and (420) are used for the information bit of adjusting code word is sorted.When positive justification, (48) and (420) all single signal of planting, i.e. signal is selected in positive justification request signal and positive justification; But when positive/zero/negative justification, (48) represent two kinds of signals; Positive justification request signal and negative justification request signal, (420) are also represented two kinds of signals: positive justification selects signal and negative justification to select signal.Write address produces circuit and utilizes fractional frequency signal (46) to produce the write address (411) and the write control signal (412) of elastic store.The every frame output of variable frequency divider write-once synchronizing signal (49) has definite write address (for example the address 0) to guarantee every frame first code word in (410).That reads that address production electric circuit utilizes frame pulse (45) that timing circuit produces and code word pulse signal (47) the generation elastic store of having deducted non-information code word pulse reads address (415) and read control signal (416), and frame pulse (45) is used for the work phase place of proof reading address production electric circuit.Information code word (410) writes the memory cell of the elastic store of address signal (411) defined under write control signal (412) effect, read under (415) and (416) effect again, gets (414).The adjustment control impuls (421) that adjusting control code generation circuit utilization adjustment request signal (48) and timing circuit provides produces adjusts control code (417).The parallel streams of code words (414) of reading from elastic store, adjust control code (417) and service bit (418) and close code stream (419) after the generation justification of road, finish the code stream conversion of transmitting terminal.For fear of the read/write address collision, timing circuit produces coordinates signal (44), is used to adjust the work phase place of variable frequency divider, reads to guarantee to write to be ahead of.
When (41) were the single channel code stream, controlled code conversion was a serial to parallel conversion process; When (41) were the multidiameter delay code stream, controlled code conversion was individual and and conversion process.Fig. 5 provides the conversion formation of single channel information code current to the parallel information streams of code words.Be example with the serial to parallel conversion process below, tell about the code stream conversion process first time that comprises controlled code conversion in detail.
A kind of realization circuit of the controlled code conversion circuit of the said transmitting terminal of the present invention as shown in Figure 5, it is made of SI PO shift register and MUX.Fig. 5 signal connection relation between it and variable frequency divider that also draws simultaneously.Other input signals of variable frequency divider and the visible Fig. 4 of output signal.The information code current (51) of serial input moves into SI PO shift register by turn under input information clock (52) drives.In the ordinary course of things, variable frequency divider works in the W frequency division, and W is the code word width, and the also line output (57) of MUX equals its parallel input (56).Like this, the every W bit of a variable frequency divider output fractional frequency signal (54) starts SI PO shift register and does once and line output (56), thereby just the information code current of serial is become parallel fix information code word.The every frame of translation circuit will be organized the adjustment code word output that contains information bit for the first time.The adjustment code word output variable frequency divider that contains information bit for tissue will utilize own adjustment code word pulse that produces and external adjustment request signal (53) to determine to contain the generation moment of the adjustment code word of information bit, and reduce the frequency division number of times at this moment, output frequency division signal (54) starts serial to parallel conversion in advance.At this moment the partial bit of (56) does not contain information, and variable frequency divider is also exported and adjust to be selected signal (55) control MUX, and the information bit in (56) is strobed on the tram in (57).Also have or not the request of adjustment relevant owing to adjust the figure place of effective information position in the code word, thereby variable frequency divider also to be adjusted the control of request signal (53) with this frame.Adjusting request signal in positive justification is the positive justification request signal, and adjusting and selecting signal is that signal is selected in positive justification.In positive/zero/negative justification, adjust request signal (53) and comprise positive justification request signal and negative justification request signal; Adjust and select signal to comprise positive justification selection signal and negative justification selection signal, control different selection logics respectively.If the negative justification request signal is invalid, the negative justification code word does not contain the effective information bit, and then variable frequency divider is by next code word work.
Application-specific integrated circuit (ASIC) technology all has two-port RAM to select as macrocell power supply road designer as gate array and standard cell at present.The elastic store of the said transmitting terminal device of the present invention is the parallel elastic store of dual-port just, thereby its available general d type flip flop constitutes also available two-port RAM formation.The circuit scale of two-port RAM is more a lot of than the small scale of the parallel elastic store that constitutes with d type flip flop.Thereby the method that adopts the present invention to propose can greatly reduce circuit scale.The elastic store structure of receiving end device of the present invention is identical with the structure of transmitting terminal device elastic store, thereby also is fit to realize with two-port RAM.
The receiving end device that the code stream that adopts the present invention institute to constitute to method is adjusted is by timing synchronization sytem, and code conversion circuit, write address produce circuit, elastic store, read address production electric circuit, variable frequency divider and controlled code conversion circuit formation, as shown in Figure 6.Its course of work is as follows: timing synchronization sytem produces various timing signals under input clock (62) and input letter sign indicating number (61) effect: (63), (64), (613) and (616), use for other partial circuits.Input clock (62) will be imported the letter sign indicating number and move into code conversion circuit.Timing signal (63) is a code word pulse signal of having deducted non-information code word pulse.It starts code conversion circuit, and the fix information code word that will import in the letter sign indicating number (61) is transformed into parallel code word (65) with the adjustment code word that contains information bit.Write address produces write address (66) and the write control signal (67) that circuit utilization (63) produces elastic store, and (65) are write elastic store.Timing signal (64) is a frame pulse signal, is used to control the corresponding relation of write address (66) and parallel code word (65), with the certainty of guarantee information code word writing position.Read address production electric circuit the divided pulse (611) of variable frequency divider output and read synchronizing signal (612) act under the generation elastic store read address (69) and read control signal (610), the information code word is read (68) from elastic store.Read synchronizing signal (612) and be used to read synchronously the generation of address, select signal (617) synchronous with adjusting to guarantee the adjustment code word in (68).(613) be the adjustment index signal that detects from the adjustment control code, (614) are the even information clocks that outside phase-locked loop recovers out.Variable frequency divider (613) control under to (614) frequency division, produce the fractional frequency signal (611) of a pulse of information code word output of each information code word frame, a pulse of every information code word frame output read synchronizing signal (612), signal (617) is selected in the adjustment of a pulse of adjustment code word output of every information code word frame.(611), the time signal of (612) and (617) configuration information code word frame.(68) be the parallel information streams of code words.Opposite with the process of transmitting terminal, controlled code conversion circuit utilization (611) and (617) are transformed to the information code current (615) of determining way with the parallel information code word, and the code stream of finishing receiving terminal recovers.Timing signal (616) is to coordinate signal, is used to avoid the collision of read/write address.When positive justification, (613) and (617) all single signal of planting, i.e. signal is selected in positive justification request signal and positive justification.When positive/zero/negative justification, (613) and (617) are respectively two kinds of signals.(613) be respectively positive justification index signal and negative justification index signal.(617) being respectively positive justification selects signal and negative justification to select signal.That tells about when it acts on transmitting terminal is the same.
When (615) were the single channel code stream, controlled code conversion was a parallel serial conversion process; When (615) were the multidiameter delay code stream, controlled code conversion was individual and and conversion process.Tell about the conversion formation of parallel information streams of code words below in conjunction with the work of variable frequency divider to the single channel information code current.Transmitting terminal of the present invention the second time inverse transform circuit a kind of realization circuit as shown in Figure 7, it is gone here and there out shift register by variable frequency divider MUX and incorporating into and constitutes.MUX wherein and incorporating into is gone here and there out shift register and has been constituted the controlled code conversion circuit of the said receiving terminal of the present invention.At ordinary times, the fix information code word is carried out parallel serial conversion.The input of MUX (76) equals output (77).The information clock (73) that variable frequency divider recovers receiving end is made W frequency division (W gets 8 in SDH), output frequency division signal (74).Fractional frequency signal (74) also claims commutation pulse, and it is inserted (77) incorporate into and goes here and there out shift register, again by (73) serial shift out serial information sign indicating number (75).When from elastic store, reading the adjustment code word that contains information bit, variable frequency divider utilizes the pulse of adjustment code word and the external adjustment index signal (71) that oneself produce to predict this constantly, and in time reduce the frequency division number of times, output frequency division signal (74) is also controlled variable frequency divider and is produced adjustment selection signal (72) in advance.(72) the control MUX will the effective information position in (76) be chosen former positions of (77), inserts to incorporate into through (74) again and goes here and there out shift register, is then shifted out by (73) serial, recovers information code current (75).Align for the adjustment code word in guaranteeing signal (72) and importing (76), variable frequency divider is also exported and is read synchronizing signal (78), is used for synchronous elastic store to read the generation of address.(79) be the coordination signal of timing synchronization sytem output, be used to change the work phase place of variable frequency divider, to avoid elastic store read-write collision.In positive justification, (71) and (72) all have only a kind of, i.e. signal is selected in positive justification request signal and positive justification.But in positive/zero/negative justification, (71) comprise two kinds of positive justification request signal and negative justification request signals.(72) comprising positive justification selects signal and negative justification to select two kinds of signals, it is to work when the positive justification code word occurring in (76) that signal is selected in positive justification request signal and positive justification, and it is to work when the negative justification code word occurring in (76) that signal is selected in negative justification request signal and negative justification.
For adjusting the justification circuit that frame constitutes with code word, the method that adopts the present invention to propose can reduce the operating rate of circuit and dwindle circuit scale greatly, is beneficial to adopt the CMOS application-specific integrated circuit (ASIC) to realize.The present invention is specially adapted to the realization of the C-n interface of synchronous digital hierarchy, realizes that for China synchronous optical fiber transmission network is significant.
Brief Description Of Drawings
Fig. 1 (a) is a common code stream conversion block diagram
Fig. 1 (b) recovers block diagram for common code stream
Fig. 2 is written in parallel to the elastic storage process of selecting reading method
Fig. 3 (a) is a serial input information code stream schematic diagram
Fig. 3 (b) is the C-4 interface concurrent information streams of code words frame structure schematic diagram of SDH
Fig. 3 (c) is the modulated code stream frame structure of the C-4 interface concurrent schematic diagram of SDH
Fig. 3 (d) is the modulated code stream frame structure of the C-4 interface serial schematic diagram of SDH
Fig. 4 is the calcspar of a kind of transmitting terminal device of the present invention
Fig. 5 is the calcspar of translation circuit first time of the present invention
Fig. 6 is the calcspar of a kind of receiving end device of the present invention
Fig. 7 is the calcspar of inverse transform circuit second time of the present invention
Fig. 8 (a) is the justification frame structure schematic diagram of the C-12 interface of SDH
Fig. 8 (b) is the information code word frame structure schematic diagram of C-12 interface when negative justification is arranged of SDH
Fig. 8 (c) is the information code word frame structure schematic diagram of C-12 interface when not adjusting of SDH
Fig. 8 (d) is the information code word frame structure schematic diagram of C-12 interface when positive justification is arranged of SDH
The present invention designs three kinds of embodiment of the code stream adjusting device that adopts code stream quadratic transformation method, is described in detail as follows respectively:
1, the code stream adjusting device of synchronous digital hierarchy C-4 serial line interface:
The C-4 interface of SDH adopts positive justification, and its code stream adjusting device divides transmitting terminal device and receiving end device.The transmitting terminal device adopts Fig. 4 and calcspar shown in Figure 5, but can save the MUX among Fig. 5 and adjust the selection signal.Input information code stream (41) is the serial code stream of 1392 64kbps, and the pulse repetition frequency of input information clock (42) is 139,264KHZ.Variable frequency divider carries out frequency division to the input information clock, produces fractional frequency signal (46) and writes synchronizing signal (49) under adjustment request signal (48) control.Its process is like this: each information code word frame of fractional frequency signal is made of 242 pulses.Fractional frequency signal pulse of per 8 the input information timeticks output of variable frequency divider.After the 229th fractional frequency signal pulse of output,, then cross 7 input information timeticks and export the 230th fractional frequency signal pulse if it is invalid to adjust request signal; If it is effective to adjust request signal, then crosses 6 input information timeticks and export the 230th fractional frequency signal pulse.Still fractional frequency signal pulse of per later on 8 input information timeticks output until the 242nd fractional frequency signal pulse of output, goes round and begins again then.Writing synchronizing signal is pulse of each information code word frame, is positioned at the 1st fractional frequency signal pulse place.Controlled code conversion circuit is a simple serial to parallel conversion circuit, is made of SI PO shift register.Under the input information clock drove, the input information code stream was moved into SI PO shift register by turn by serial, started serial to parallel conversion with fractional frequency signal (46), just obtained the information streams of code words that walks abreast, shown in Fig. 3 (b).Write address produces circuit individual write address counter, and fractional frequency signal (46) is counted, and count value is exactly the write address (411) of elastic store.The pulsewidth that writes synchronizing signal (49) is not more than a code word size, and its effect is that write address counter is returned other.Write control signal (412) can be produced by fractional frequency signal (46), and its effective time width should be narrower than the time width of write address.Elastic store constitutes with two-port RAM.Timing circuit is made of logical circuit, utilizes justification clock (43) to produce various timing signals.Timing signal (45) is the frame pulse of justification frame, and pulse of every frame is positioned at first code word of justification frame, and pulsewidth is not more than a code word size.The timing signal (47) that timing circuit produces is a code word pulse signal of having deducted the pairing code word pulse of non-information code word.Reading address production electric circuit has a read address counter, timing signal (47) is counted, count value be exactly elastic store read address (415).Timing signal (45) carries out set to read address counter, is set to the previous address of address 0.Read control signal (416) can be produced by timing signal (47), and its effective time width should be narrower than the width of reading the address.Timing circuit is output coordinating signal (44) also, also can use frame pulse (45) as coordinating signal.If frame pulse (45) with to write synchronizing signal (49) too approaching, is just adjusted the work phase place of variable frequency divider, make to write synchronizing signal in advance.Adjust control code and produce circuit and close all circuit common of road circuit, repeat no more.
Receiving terminal adopts device as shown in Figure 6.The formation of timing synchronization sytem utilizes input clock (62) and input letter sign indicating number (61) to produce the needed various timing signals of receiving terminal with common the same.Code conversion circuit is made of SI PO shift register, and input clock will be imported the letter sign indicating number and move into SI PO shift register by turn.The code word pulse signal (63) of deducting non-information code word pulse that timing synchronization sytem provides starts serial to parallel conversion and presses code parallel output, gets (65).The write address counter that write address produces in the circuit is counted (63), and count value is the write address (66) of elastic store.The signal (64) of timing synchronization sytem output is a frame pulse, is positioned at first code word of justification frame, and it is long that pulsewidth is narrower than a code word.It is set to write address counter the last address of address 0.Write control signal (67) is produced by (63), and its effective time width should be narrower than the time width of write address.Elastic store is made of two-port RAM.The course of work of variable frequency divider is the same substantially with the course of work of the variable frequency divider of transmitting terminal, and distinctive points has two places: (1), be that the 229th fractional frequency signal pulse exported in advance, rather than the 230th of transmitting terminal; (2), with adjusting the adjustment request signal that index signal (613) replaces transmitting terminal.Also the write address generation circuit with transmitting terminal is the same to read address production electric circuit.Controlled code conversion circuit is one to be incorporated into and goes here and there out shift register, saves to adjust and selects signal (617).Fractional frequency signal (611) starts parallel serial conversion, (68) is inserted to incorporate into go here and there out shift register.The even information clock (614) that recovers will believe by turn that again sign indicating number shifts out, and just obtains the uniform serial information code stream (615) that recovers.
2, the code stream adjusting device of synchronous digital hierarchy C-4 parallel interface (4 tunnel):
The C-4 interface operating rate height of SDH, if adopt parallel interface, it is more simple that circuit is linked.Be example with 4 tunnel parallel interfaces here.
The transmitting terminal device adopts as Fig. 4 calcspar.(41) be four tunnel parallel input information code streams, speed is 1/4th of fourth order group speed.(42) be the input information clock, pulse repetition frequency is 1/4th of a fourth order group clock frequency.Variable frequency divider removes 2 to (42) and produces fractional frequency signals (46), and per 4 frames change and remove 2 for removing 1 once.It is effective that every in addition generation is adjusted request signal (48) four times, additionally changes to remove 2 for removing 1 once again.Adjust and select signal (420) to constitute: S1 and S2 by 2 signals.S1 is made of the 230th fractional frequency signal pulse, and S2 gets and adjusts request signal (48).Controlled code conversion circuit adopts common elastic store to constitute, and utilizes (42) to write 4 input information sign indicating numbers (41) at every turn, utilizes (46) to read 8 information codes (410) at every turn.When the 230th fractional frequency signal pulse arrives,, move 6 bits after then and read a parallel code word if it is effective to adjust request signal; If it is invalid to adjust request signal, moves 7 bits after then and read a parallel code word.Other are all just the same with the transmitting terminal device of embodiment 1, repeat no more.
Receiving end device adopts calcspar shown in Figure 6.The work of variable frequency divider is the same with the variable frequency divider of transmitting terminal, and unique difference is to replace adjusting request signal with the adjustment index signal that receives.Controlled code conversion circuit is to constitute with elastic store, utilizes fractional frequency signal (611) to write 8 at every turn.When the 230th fractional frequency signal pulse arrives,, move 6 bits after then and write a code word again if it is effective to adjust index signal; If it is invalid to adjust index signal, moves 7 bits after then and write a code word again.(614) Ci Shi repetition rate is 1/4th of a fourth order group speed.It supplies with variable frequency divider, also is used to read 4 bits from elastic store simultaneously at every turn, forms four tunnel parallel information code currents.The work of other parts is identical with the counterpart of embodiment 1, repeats no more.
3, the code stream adjusting device of synchronous digital hierarchy C-12 serial line interface:
The C-12 interface of SDH adopts positive/zero/negative code speed adjustment technology.The code stream adjusting device divides transmitting terminal device and receiving end device.The transmitting terminal device adopts calcspar shown in Figure 4.Receiving end device adopts calcspar shown in Figure 6.The structure of C-12 interface justification frame is made of 140 code words shown in Fig. 8 (a), contains 127 fix information code words, 1 positive justification code word, 1 negative justification code word, other are the additional overhead code word, R represents fixed stuff R-Bits among the figure, 0 is the service bit, and C1 is the negative justification control code, and C2 is the positive justification control code, I is the fix information bit, S1 is the negative justification bit, and S2 is the positive justification bit, and V5 also is a kind of service bit.When negative justification, the structure of information code word frame is shown in Fig. 8 (b), and the 97th code word is the negative justification code word, and S1 is an information bit, and full frame is totally 129 code words.When not adjusting, the structure of information code word frame is made of 128 code words shown in Fig. 8 (c), does not contain non information bit.When positive justification, information code word frame structure is shown in Fig. 8 (d), and full frame is totally 128 code words, and the 97th code word is the positive justification code word, and S2 is a noninformation bit.
Transmitting terminal is compared with embodiment 1 with the course of work of receiving terminal, and is most of identical.Below only different detailed descriptions of part do.
(41) be the input information code stream, speed is 2048kbps.The pulse frequency of input information clock (42) is 2048KHZ.Adjusting request signal (48) is made of positive justification request signal and negative justification request signal.Variable frequency divider is 8 frequency divisions at ordinary times, fractional frequency signal pulse of per 8 input information timeticks output.If this frame has the request adjusted, then last till the 128th fractional frequency signal pulse output after, variable frequency divider goes round and begins again.If this frame has the positive justification request, then bit output of the 97th fractional frequency signal pulse advancing then still by 8 frequency division work, goes round and begins again after the 128th fractional frequency signal pulse output again.If this frame has the negative justification request, then seven bit outputs of the 97th fractional frequency signal pulse advancing then still by 8 frequency division work, go round and begin again after the 129th fractional frequency signal pulse output again.The controlled code conversion circuit of making a start also be select signal also to omit with the SI PO shift register adjustment need not.
At receiving terminal, (614) are the even clocks that outside phase-locked ring recovers, and pulse frequency is 2048KHZ.The work of variable frequency divider is the same with the variable frequency divider of transmitting terminal, adjusts selection signal (617) but will produce two: positive justification selects signal and negative justification to select signal.They are pulse all, is positioned at the 97th code word place, and pulsewidth is that a code word is long.The controlled code conversion circuit of receiving terminal adopts circuit shown in Figure 7, by MUX with incorporate into and go here and there out shift register and constitute.MUX has three kinds to select logic, is subjected to positive justification to select signal and negative justification to select signal controlling.The negative justification code word of negative justification (the 97th code word) is being arranged constantly, negative justification selects the signal controlling MUX that the most last position is chosen in last position of code word.The positive justification code word of positive justification (the 97th code word) is being arranged constantly, signal controlling MUX back seven the first seven positions of choosing code word with code word are selected in positive justification.In other moment, the input of MUX equals output.Fractional frequency signal (611) starts parallel serial conversion, the output of MUX is inserted to incorporate into go here and there out shift register, shifts out the even information code current (615) that is restored by turn by the even information clock that recovers.
Claims (8)
1, a kind of quadratic transformation method of code stream conversion of transmitting terminal of justification is characterized in that may further comprise the steps:
(1) receives the input information code stream with the input information clock;
(2) get the W position from said input information code stream, W is that code word is long, is divided into W road and line output at every turn, constitutes a parallel fix information code word;
(3) when output has the adjustment code word of k information bit, from said input information code stream, take out the k position, be divided into the output of k road and, constitute a parallel adjustment code word by the position ordering of information bit in said adjustment code word;
(4) the said fix information code word that step (2) and (3) are produced and adjustment code word that information bit is arranged write elastic store in proper order by the code word beat of said input information clock;
(5) the information code byte of pressing justification frame is clapped sense information code word from said elastic store, and bat place of non-information code byte is not read, to produce non-information code word;
(6) adjust phase relation between the read-write operation of said elastic store, with guarantee justification frame the adjustment code word beat of information bit is arranged the time lucky reading step (4) the said adjustment code word that information bit is arranged that writes;
(7) code stream read of step (5), produce the service bit stream that circuit produces and close the road by adjusting adjustment control code that request signal control produces and service bit, form the code stream after the justification, finish the code stream conversion of transmitting terminal.
2, the secondary inverse transformation method of a kind of receiving terminal code stream of justification recovery is characterized in that may further comprise the steps:
(1) receives input letter sign indicating number with input clock;
(2) said input letter sign indicating number is divided into W road and line output by code word, constitutes parallel code word;
(3) the parallel code word that will contain information bit writes elastic store by the code word beat of said input clock;
(4) by the beat of the information clock that recovers, read an information code word every J pulse from said elastic store, J is the figure place of effective information position in the information code word of reading;
(5) remove noninformation bit in the said adjustment code word of step (4) output by the indication of the adjustment control code that receives;
(6) by the beat of the information clock that recovers, the parallel code word that step (5) is exported is merged into definite way output, thereby the code stream of finishing receiving terminal recovers.
3, adopt the transmitting terminal device of code flow regulating method according to claim 1, it is characterized in that producing down the timing circuit of various time signals by the effect of justification clock, receive information clock and information code current, and at the fractional frequency signal of variable frequency divider output with adjust the controlled code conversion circuit of selecting the parallel code word of output under the signal effect, under the coordination signal effect of external adjustment request signal and timing circuit output, the information clock is carried out frequency division and produce fractional frequency signal, adjust the variable frequency divider of selecting signal and writing synchronizing signal, write the parallel code word of coming under write address and the write control signal effect by said controlled code conversion circuit and reading the address and the read control signal effect under read the elastic store of parallel code word, utilize described fractional frequency signal and write synchronizing signal and produce the write address of elastic store and the write address generation circuit of write control signal, utilize the frame pulse of said timing circuit generation and the address production electric circuit of reading of reading address and read control signal that information code word pulse signal produces elastic store, under the adjustment control impuls effect of external adjustment request signal and timing circuit generation, produce the adjustment control code of adjusting control code and produce circuit, and, adjust the road circuit that closes that service bit that control code and external circuit produce merges output and constitute the parallel code word of said elastic store output.
4, transmitting terminal device as claimed in claim 3 is characterized in that said controlled code conversion circuit is by under the input information clock drives the information code current serial of serial input being moved into and produce the SI PO shift register of parallel code word output under fractional frequency signal control and being adjusted and select signal controlling to select the MUX of conversion output to constitute to the parallel code word output of SI PO shift register.
5, transmitting terminal device as claimed in claim 3 is characterized in that described elastic store constitutes with dual-port random access memory.
6, employing is as the receiving end device of code flow regulating method as described in the claim 2, it is characterized in that it is by accepting the timing synchronous circuit that input clock and input letter sign indicating number produce various timing signals, under input clock drives, accept input letter sign indicating number and under the effect of the information code word pulse signal that said timing synchronous circuit produces, produce the code conversion circuit of parallel code word output, the write address of generation elastic store write address and write control signal produces circuit under frame pulse signal that is produced by timing synchronization sytem and the effect of information code word pulse signal, in the divided pulse of variable frequency divider output with read the address production electric circuit of reading of reading address and read control signal of generation elastic store under the synchronizing signal effect, accept the parallel code word that code conversion circuit sends here under write address and the write control signal effect and reading the address and the read control signal effect under the elastic store of the parallel code word of output, the information clock that recovers is carried out frequency division and produce fractional frequency signal under the control of adjustment index signal, read synchronizing signal and adjust the variable frequency divider of selecting signal, and under fractional frequency signal and the effect of adjustment selection signal, utilize the information clock that recovers the parallel code word of elastic store output to be transformed into the controlled code conversion circuit formation of the information code current of definite way.
7, receiving end device as claimed in claim 6, it is characterized in that said controlled code conversion circuit by adjust to select under the signal controlling parallel code word to input elect the MUX of output and under commutation pulse triggers, the parallel output code flow of MUX moved into inner and under the triggering of the information clock that receiving end is recovered serial constitute going here and there out shift register incorporating into of shifting out of inside letter sign indicating number.
8, receiving end device as claimed in claim 6 is characterized in that said elastic store is made of dual-port random access memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 94100652 CN1105791A (en) | 1994-01-21 | 1994-01-21 | Secondary conversion type code flow regulating method and device |
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| CN 94100652 CN1105791A (en) | 1994-01-21 | 1994-01-21 | Secondary conversion type code flow regulating method and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1061805C (en) * | 1996-08-30 | 2001-02-07 | 中国人民解放军保密委员会技术安全研究所 | High-speed and low-speed code rate conversion circuit |
| CN1064497C (en) * | 1996-09-20 | 2001-04-11 | 清华大学 | Twice-smoothing jitter reducing method and circuit |
-
1994
- 1994-01-21 CN CN 94100652 patent/CN1105791A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1061805C (en) * | 1996-08-30 | 2001-02-07 | 中国人民解放军保密委员会技术安全研究所 | High-speed and low-speed code rate conversion circuit |
| CN1064497C (en) * | 1996-09-20 | 2001-04-11 | 清华大学 | Twice-smoothing jitter reducing method and circuit |
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