CN1061805C

CN1061805C - High- and low-speed code rate conversion circuit

Info

Publication number: CN1061805C
Application number: CN96109563A
Authority: CN
Inventors: 陈文放; 张新民; 何调元; 徐卫; 李宏超; 潘云生
Original assignee: TECH SAFETY INST SECRETS COMMITTEE PLA
Current assignee: TECH SAFETY INST SECRETS COMMITTEE PLA
Priority date: 1996-08-30
Filing date: 1996-08-30
Publication date: 2001-02-07
Anticipated expiration: 2016-08-30
Also published as: CN1175837A

Abstract

The present invention relates to a high-speed and low-speed code rate conversion super large-scale integrated circuit in a digital communication system, which comprises a time slot pulse generating module, a 2Mbps to 64Kbps converting module, a synchronous converting module, a direction conversion selecting module and an input/output module. All the circuits are integrated on one super large-scale integrated circuit by FPGA, and thus, the circuit capable of dividing a primary group E1 into 32 zero degree groups E0 or integrating 32 zero degree groups E0 into the primary group E1 in digital PCM communication is realized.

Description

Low speed code rate conversion circuit at a high speed,

The invention belongs to the design field of very lagre scale integrated circuit (VLSIC) in the digital communication, specially refer to shunt and the circuit design of closing the road in the PCM pulse code modulation communication.

In digital communication wind network, in order to make full use of the transmission of circuit, and, will in communication wind network, carry out rate conversion for the grouping in communicating by letter and the needs of maintaining secrecy, or with signal primary group E ₁, 2.048 mbit/(being called for short 2Mbps) are divided into 32 zero degree group E ₀(64Kbps); Or with 32 tunnel zero degree group E ₀Be combined into a kind of primary group E ₁Circuit.

In present existing technology, this similar shunt, close the road circuit and mainly have following several defective: one, by in polymorphic type, the many outer chips, small scale integrated circuit formed, its volume is big, power consumption is high, poor reliability and price be costliness; Two, system is incomplete, particularly at primary group E ₁Be divided into E ₀The time, output is no more than 10 the tunnel, is not whole outputs, brings many inconvenience to application; Three also do not see 32 road E up to now ₀Synthesize one road E ₁Circuit and equipment thereof come into operation; Four, in circuit design, with close the road and along separate routes two kinds of speed conversions be chosen in the circuit of realizing on a slice IC chip by control and also do not see.In view of the foregoing, just wish to design more advanced, complete, multiple functional circuit, satisfy the transmission requirement in the digital communications network.

Purpose of the present invention is exactly on a slice very lagre scale integrated circuit (VLSIC) core, utilizes the mode of FPGA (FreldProqrammable Gale Array is a field programmable gate array), finishes primary group E ₁Divide to 32 tunnel zero degree group E ₀, or with 32 road reversal E ₀Be combined into a kind of E ₁Thereby it is big defeated to carry out effective signal.

The present invention relies on following technical proposals to realize, a kind of high speed of numeral, low speed code rate conversion circuit, mainly include branch/close circuit, it is characterized in that, on a slice VLSI (very large scale integrated circuit) chip FPGA, realize the rate conversion in the digital pcm communication, it constitutes, by time-gap pulsing generation module circuit and to be connected to one be the conversion module circuit of 2Mbps → 64Kbps by speed, be connected respectively to synchronous conversion module circuit by this module, and direction transformation selects modular circuit signal after treatment to be connected to the input/output module circuit.

According to the 2MHZ clock and the 8KHZ frame synchronizing signal of input, time-gap pulsing generation module 1 forms zero phase (0 °) and π 64KHZ mutually, produces 32 time slot sign pulse Ti simultaneously, i=0,1 ..., 31, be used for indicating and selection E ₁In 32 time slot TSi, i=0,1 ..., 31; 2Mbps → conversion module 2 is selected each road from importing the E road, PCM32 road at a high speed, becomes 32 road E0 signals, perhaps by reversal 32 road E ₀Signal synthesizes a kind of E ₁Signal output, conversion module 3 is that output signal is carried out Synchronous Processing synchronously, with zero phase, π is half and half 32 road E mutually ₀Output is concentrated in the unification that becomes homophase; Change direction and select module mainly the input and output two-way signaling to be selected, determine this circuit or realize that 2Mbps is divided into 32 road 64Kbps, or realize that 32 road 64Kbps are combined into the conversion of a kind of 2Mbps; The input/output signal of determining this circuit of input/output module 5 is Transistor-Transistor Logic level or CMOS level, and solves the compatibling problem of the two.

Outstanding feature of the present invention is, with all each several part circuit, all is made in above a slice VLSI (very large scale integrated circuit) chip FPGA-XC3064APC84, realized in the digital pcm communication, with primary group E ₁Be divided into 32 zero degree group E ₀Or 32 tunnel zero degree group E ₀Be combined into a kind of primary group E ₁Circuit, finish at a high speed, low speed rate conversion function, ten times of the circuit volume decimals of being realized by a slice FPGA, tens place in light weight, power consumption has only several milliwatts, tens of times of low prices, and reliability height, it is safe to use.Performance period is short, and launch is fast.

Further specify embodiment below in conjunction with accompanying drawing:

Description of drawings:

Fig. 1 be the present invention along separate routes/close the theory diagram on road;

Fig. 2 is the circuit distribution map of time slot sign pulse generation module;

Fig. 3 is TS4n+2, TS4n+3, n=0,1 ..., 8 branch of the 2Mbps → 86Kbps of totally 16 time slots/close road circuit, (direction transformation circuit be also included within);

Fig. 4 is TS4n+2, TS4n+3, n=01 ..., 8 branch of the 2Mbps → 64Kbps of totally 16 time slots/close road circuit, (direction transformation circuit be also included within).

Fig. 5 is a sequential chart;

Fig. 6 is complete embodiment circuit diagram.

In Fig. 1, clearly show allomeric function of the present invention and structural framing, S is the function selecting end, and S=0 represents circuit of the present invention for closing the road, and S=1 represents that circuit of the present invention is shunt.When S=1 divides under the line state, input signal is digital pcm 32 road E1 signals of 2Mbps, 2MHZ clock, 8KHZ frame synchronizing signal, output zero phase 64KHZ clock and 32 tunnel synchronous 64Kbps data-signals.When S=0 closes under the line state, be input as 2MHZ clock, 8KHZ synchronously and 32 road 64Hbps data-signals, zero phase 64KHZ clock is an output signal, is produced by circuit of the present invention, 2Mbps is an output signal.

In Fig. 2, shown the time slot sign pulse-generating circuit, it comprises two four digit counters, the 3-8 decoder of four positive arteries and veins outputs, this circuit common property is given birth to 32 time-gap pulsings, produces the clock of 64KHZ simultaneously, the frame synchronization of its input 2MHZ clock and 8KHZ, C16BARD is four digit counters that trailing edge triggers, and the decoder WF-138 of positive pulse output is the improvement of 74LS138, and it is output as positive pulse.

In Fig. 3, represent a kind of branch/close road circuit, it is one of core circuit of the present invention, it is comprising one 8 bit shift register, connect four triple gates, a bi-directional pin, and two with the door, individual NOR gate, when S=1, it realizes the shunt velocity transformation of 2Mbps → 64Kbps, and when S=0, that realizes 64Kbps → 2Mbps closes the road speed conversion, TS4n+1, m=0,1 ... 8, have 16 time slots and all reuse identical circuit, do not repeat among the figure to draw, RS8 is eight grades of shift registers.This figure operation principle is: when S=1, at the TS4n or the TS4n=1 time slot of every frame, the clock of shift register is the non-of 2MHZ clock; Non-TS4n or TS4n+1 time slot, the clock of shift register is the non-of 64KHZ clock, the clock that is shift register is the mix clock that 2MHZ and 64KHZ form, utilize mix clock, can be with the data of TS4n or TS4n+1, write in 8 bit shift register at a high speed, after TS4n or the TS4n+1 time slot, with the 64KHZ clock data in 8 bit shift register are read successively from the Q7 end again.

When S=0, its course of work is similar with S=1, but conversion is opposite, non-TS4n or TS4n+1 time slot, mix clock writes low speed data in 8 bit shift register, TS4n or TS4n+1 time slot, with the non-of 2MHZ clock the data in 8 grades of shifting memories are read at a high speed from the Q8 end, note, when having only TS4n or TS4n+1, with door IC35 triple gate IC10 is opened, at this moment, M point place signal is the data of TS4n or TS4n+1, At All Other Times, triple gate IC10 closes, and M point signal is the data of other time slot.

The described circuit of Fig. 4, it also is one of core circuit of the present invention, this figure compares with Fig. 3, substantially similar, it comprises the three identical parts with figure, promptly eight title bit register, four three-states allow, bi-directional pin, two and door and a NOR gate, in addition, increase by two triple gate IC21, IC24, a trigger D.On function, their difference is that the 64KHZ clock of mix clock is the π phase, just because of this, no matter is along separate routes or closes the road, has all increased phase-adjusting circuit, i.e. d type flip flop FDC.In addition, when closing the road, low speed 64Kbps speed data is adjusted by the FDC phase place earlier, and low speed writes 8 grades of shift registers again, when TS4n+2 or TS4n+3, utilizes the 2MHZ clock, and the data high-speed in the shift register is read.

Fig. 5 represents the sequential chart of circuit of the present invention, the signal of 2Mbps and the relation of clock, the data-signal of 64Kbps are to be output as the π phase from this circuit, and the 64Kbps signal of importing when closing the road is zero phase, be the reversal signal, 64KHZ zero phase clock is provided by circuit of the present invention.

Fig. 6 represents a kind of embodiment of circuit of the present invention, IPAD is the pin of input signal among the figure, OPAD is the pin of output signal, BPAD is the pin of I/O two-way signaling, TBUF and OBUFZ are triple gate, be noted that especially time slot sign pulse generation module is with all time-gap pulsing Ti, i=0,1 ... 31 all generate, two examples have only been drawn in speed conversion, direction transformation and conversion synchronously, do not repeat to spread out to draw, and establishing TSi is 32 road 64Kbps data-signals, i=0,1 ... 31, TS4n is example with TS0, and TS04n+1 is identical with TS4n not to be drawn.TS4n+2 is example with TS4, and TS4n+3 does not draw so that TS2+2 is identical, i.e. the situation of n=0.When n=1, only with T4n, T4n+1, T4n+2, T4n+3 replace T0 respectively, T1, T2, T3, TS4n+1, TS4n+2, TS4n+3 replace TS0 respectively, TS1, TS2, TS3 gets final product.

Claims

1, a kind of digital high-speed, low speed code rate conversion circuit, mainly include branch/close circuit, it is characterized in that, on a slice VLSI (very large scale integrated circuit) chip FPGA, realize the rate conversion in the digital pcm communication, it constitutes, being connected to a speed by time-gap pulsing generation module circuit (1) is that 2Mbps transforms to the conversion module circuit (2) that speed is 64Kbps, be connected to synchronous conversion module circuit (3) and direction transformation processing module circuit (4) respectively simultaneously by this module, signal after treatment returns input/output module circuit (5).

According to the described high speed of claim 1, low speed code rate conversion circuit, it is characterized in that 2, said time-gap pulsing produces circuit (1) and comprises two four digit counter 16BARD, and they are connected to the 3-8 decoder WF-138 of four positive pulse outputs.

3, according to the described high speed of claim 1, low speed code rate conversion circuit, it is characterized in that, said speed conversion modular circuit, it comprises one 8 bit shift register RS8, it is connecting four triple gate IC8, IC9, IC10, IC11 and a bi-directional pin, simultaneously this circuit also comprise two with the door and a coupled NOR gate.

4, according to the described high speed of claim 1, low speed code rate conversion circuit, it is characterized in that, said speed conversion modular circuit, after 8 bit shift register connect four triple gates, bi-directional pin and two and door, NOR gate, also to increase a d type flip flop FDC and two coupled triple gate IC21 again, IC24.