CN117577151A

CN117577151A - Memory cell, memristor array, memory calculation integrated circuit and operation method

Info

Publication number: CN117577151A
Application number: CN202311657064.4A
Authority: CN
Inventors: 吴华强; 魏秋萌; 姚鹏; 伍冬; 高滨; 唐建石; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-12-05
Filing date: 2023-12-05
Publication date: 2024-02-20

Abstract

The embodiment of the disclosure provides a memory cell, a memristor array, a memory integrated circuit and an operation method. The storage unit comprises n weight units and a transverse gate tube. Each of the n weight units comprises a first memristor element and a first switching element, a first electrode of the first memristor element is electrically connected with a first electrode of the first switching element, a second electrode of the first memristor element serves as a second end of the corresponding weight unit and is used for receiving a first bit line signal, second electrodes of the first switching elements of the n weight units serve as first ends of the corresponding weight units respectively and are electrically connected with each other and are electrically connected with first ends of the transverse gate tubes, control electrodes of the first switching elements are respectively used for receiving different first word line signals, second ends of the transverse gate tubes are used for receiving source line signals, and control ends of the transverse gate tubes are used for receiving second word line signals.

Description

Memory cell, memristor array, memory calculation integrated circuit and operation method

Technical Field

Embodiments of the present disclosure relate to a memory cell, a memristor array, a memory integrated circuit, and a method of operation.

Background

With the rapid development of artificial intelligence and neural network technologies, the importance of hardware acceleration technology is increasingly significant. The integrated memory and calculation is a calculation architecture for the acceleration of the neural network hardware, and the memory cell array simultaneously fuses calculation functions, so that the data carrying and memory access cost is obviously reduced. Taking a memristor memory cell array as an example, the nonvolatile conductive state of the device is used for storing network weight, and after voltage pulse for coding input information is applied, matrix vector multiplication results are represented by output analog current values. The current type integrated circuit based on nonvolatile components can be used for realizing matrix calculation with high parallelism and high throughput rate, and greatly improving system calculation power. The storage unit array is an infrastructure forming a memory and calculation integrated system, and different array structures are required to be matched with different calculation precision, system calculation force, energy efficiency and cost requirements.

Disclosure of Invention

At least one embodiment of the present disclosure provides a memory cell including:

n weight units, where n is a positive integer, each of the n weight units including a first memristor element including a first electrode and a second electrode, and a first switching element including a control electrode, a first electrode, and a second electrode;

The transverse gate tube comprises a control end, a first end and a second end,

the first electrodes of the first memristor elements are electrically connected with the first poles of the first switch elements, the second electrodes of the first memristor elements serve as second ends of corresponding weight units and are used for receiving first bit line signals, the second poles of the first switch elements of the n weight units serve as first ends of the corresponding weight units respectively and are electrically connected with each other and with the first ends of the transverse gate tubes, the control poles of the first switch elements are respectively used for receiving different first word line signals, the second ends of the transverse gate tubes are used for receiving source line signals, and the control ends of the transverse gate tubes are used for receiving second word line signals.

For example, in a memory cell provided in at least one embodiment of the present disclosure, each of the n weight units further includes a second memristor element and a second switching element, a first electrode of the second memristor element is electrically connected to a first pole of the second switching element, a second electrode of the second memristor element serves as a third terminal of the corresponding weight unit and is used for receiving a second bit line signal, a control terminal of the second switching element is electrically connected to a control terminal of the first switching element, and a second pole of the second switching element is electrically connected to a second pole of the first switching element.

At least one embodiment of the present disclosure provides a memristor array including:

a plurality of memory cells provided in at least one embodiment of the present disclosure, where the plurality of memory cells are arranged in m memory cell rows and p memory cell columns along a first direction and a second direction, and m and p are positive integers;

p groups of first word lines extending along the second direction and connected with the p memory cell columns in a one-to-one correspondence manner, wherein each group of the p groups of first word lines comprises n first word lines, and each of the n first word lines is electrically connected with a first pole of a first switching element of a corresponding one of the memory cell columns;

m second word lines extending along the first direction and connected with the m memory cell rows in a one-to-one correspondence manner, wherein each of the m second word lines is electrically connected with a control end of a lateral gate tube of a corresponding one of the memory cell rows;

p source lines extending along the second direction and connected with the p memory cell columns in a one-to-one correspondence manner, wherein each of the p source lines is electrically connected with the second end of the transverse gate tube of the corresponding one of the memory cell columns;

and m first bit lines extending along the first direction and connected with the m memory cell rows in a one-to-one correspondence manner, wherein each of the m first bit lines is electrically connected with the second electrode of the first memristor element of the corresponding one of the memory cell rows.

For example, in a memristor array provided by at least one embodiment of the present disclosure, each of the n weight cells further includes a second memristor element and a second switching element, the memristor array further includes:

and m second bit lines extending along the first direction and connected with the m memory cell rows in a one-to-one correspondence, wherein each of the m second bit lines is electrically connected with a second electrode of a second memristor element of the corresponding one of the memory cell rows.

For example, in the memristor array provided in at least one embodiment of the present disclosure, the driving circuit further includes:

a bit line driving circuit electrically connected to the first bit line to provide the first bit line signal;

and a word line driving circuit electrically connected with the second word line to provide the second word line signal.

For example, in a memristor array provided in at least one embodiment of the present disclosure, the bit line driving circuit includes an amplifying circuit unit, a first output circuit, a second output circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, and a bit line driving output terminal; the amplifying circuit unit comprises a first input end, a second input end, a first output end and a second output end; the first output circuit is respectively and electrically connected with a first node, a first voltage end and the bit line driving output end and is configured to conduct or break the connection between the bit line driving output end and the first voltage end under the control of the potential of the first node; the second output circuit is respectively and electrically connected with a second node, a second voltage end and the bit line driving output end and is configured to conduct or break the connection between the bit line driving output end and the second voltage end under the control of the potential of the second node; the first control circuit is electrically connected with the first voltage terminal and the first node respectively and is configured to conduct or break connection between the first node and the first voltage terminal; the second control circuit is respectively and electrically connected with the second voltage terminal and the second node and is configured to conduct or break the connection between the second node and the second voltage terminal; the third control circuit is electrically connected with the first output end of the amplifying circuit unit and the first node respectively and is configured to switch on or off the connection between the first node and the first output end of the amplifying circuit unit; the fourth control circuit is electrically connected with the second output end of the amplifying circuit unit and the second node respectively and is configured to turn on or off connection between the second node and the second output end of the amplifying circuit unit.

For example, in a memristor array provided by at least one embodiment of the present disclosure, the word line driving circuit includes a fifth control circuit, a sixth control circuit, and a word line driving output; the fifth control circuit is electrically connected with the first voltage terminal and the word line driving output terminal respectively and is configured to switch on or off the connection between the first voltage terminal and the word line driving output terminal; the sixth control circuit is electrically connected to the second voltage terminal and the word line driving output terminal, respectively, and is configured to turn on or off connection between the second voltage terminal and the word line driving output terminal.

At least one embodiment of the present disclosure provides a memory integrated circuit including a memristor array as provided by at least one embodiment of the present disclosure.

At least one embodiment of the present disclosure provides a method of operating a memristor array as provided by at least one embodiment of the present disclosure, the method of operating comprising: applying a second selected voltage to a second word line corresponding to a row where a target operation unit is located, and applying a first selected voltage to a first word line corresponding to a column where the target operation unit is located, thereby selecting the target operation unit; and applying an operation voltage to the first bit line and the source line corresponding to the target operation unit.

For example, in the operation method provided in at least one embodiment of the present disclosure, the applying an operation voltage to the first bit line and the source line corresponding to the target operation unit includes: and applying an operation voltage for setting to the first bit line and the source line corresponding to the target operation unit.

For example, in the operation method provided in at least one embodiment of the present disclosure, the applying an operation voltage to the first bit line and the source line corresponding to the target operation unit includes: and applying an operation voltage for resetting to the first bit line and the source line corresponding to the target operation unit.

For example, in the operation method provided in at least one embodiment of the present disclosure, the target operation unit includes a non-zero input unit, and the applying the operation voltage to the first bit line and the source line corresponding to the target operation unit includes: applying an input signal to a first bit line corresponding to the target operation unit; and applying a source line voltage to the column where the target operation unit is located.

At least one embodiment of the present disclosure provides an electronic device including: a selection module configured to apply a second selection voltage to a second word line corresponding to a row where a target operation unit is located, and apply a first selection voltage to a first word line corresponding to a column where the target operation unit is located, thereby selecting the target operation unit; and an operation module configured to apply an operation voltage to the first bit line and the source line corresponding to the target operation unit.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the operation module is further configured to apply an operation voltage for setting to the first bit line and the source line corresponding to the target operation unit.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the operation module is further configured to apply an operation voltage for reset to the first bit line and the source line corresponding to the target operation unit.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the operation module is further configured to apply an input signal to a first bit line corresponding to the target operation unit; and applying a source line voltage to the column where the target operation unit is located.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A is a schematic diagram of a conventional memristor array for current-mode storage;

FIG. 1B is a schematic diagram of another conventional memristor array for current-mode storage;

FIG. 1C is a diagram illustrating a situation where calculation errors are caused;

FIG. 1D is a diagram illustrating another situation in which calculation errors are caused;

FIG. 2A is a schematic diagram of a memory cell based on a 1T1R structure according to at least one embodiment of the present disclosure;

FIG. 2B is a schematic diagram of a memory cell based on a 2T2R structure according to at least one embodiment of the present disclosure;

FIG. 3A is a schematic diagram of a memristor array provided in accordance with at least one embodiment of the present disclosure;

FIG. 3B is a schematic diagram of a memristor array provided in at least one embodiment of the present disclosure;

FIG. 4A is a schematic diagram of a driving circuit according to at least one embodiment of the present disclosure;

FIG. 4B is a schematic diagram of a driving circuit according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a memory integrated circuit according to at least one embodiment of the present disclosure;

FIG. 6A is a schematic diagram of a set operation method according to at least one embodiment of the present disclosure;

FIG. 6B is a schematic diagram of a reset operation method according to at least one embodiment of the present disclosure;

FIG. 6C is a schematic diagram of a method of computing operation provided in accordance with at least one embodiment of the present disclosure; and

fig. 7 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The memristor array comprises a plurality of rows and columns of memory cells, each memory cell comprises a weight cell and is realized in the form of a memristor cell, the memristor cell can be in a 1T1R structure or a 2T2R structure, the memristor cell in the 1T1R structure comprises a switching element and a memristor element, a first end of the memristor element is electrically connected with a first end (such as a drain electrode of a transistor) of the switching element, and the memristor cell in the 2T2R structure comprises two switching elements and two memristor elements. The present disclosure is not limited as to the type, structure, etc. of memristor elements. Memristor elements employed in embodiments of the present disclosure may be, for example, resistive change memories, phase change memories, conductive bridge memories, or other memristor elements of the same characteristics. The switching elements employed in the embodiments of the present disclosure may be, for example, thin film transistors, field effect transistors, or other switching elements of the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that the source and drain may be indistinguishable in structure.

Memristor elements are a type of nonvolatile device whose conductance state can be adjusted by application of an external stimulus. Memristor elements, which are two-terminal devices, have the characteristics of adjustable resistance and non-volatility, and are therefore widely used in memory and accounting. Memristor elements may operate directly on the analog domain, e.g., memristor elements may perform multiplications based on ohm's law and additions based on kirchhoff's current law. For example, according to kirchhoff's law, the memristor array described above may perform multiply-accumulate computations in parallel by setting the states (e.g., resistance) of the memristor elements and applying corresponding word line and bit line signals at the word and bit lines, with both storage and computation occurring in each element of the array.

The write operation to the memristor cell may be implemented by performing set and reset operations on the memristor cell. For example, a set operation may be a bit line plus a positive voltage pulse, the source line being grounded, the memristor cell resistance value may be made low; the reset operation may be to apply a positive voltage pulse to the source line, and the bit line is grounded, so that the resistance of the memristor unit may be increased. A set operation or a reset operation may be used as a write operation.

The read operation for the memristor cell may be: applying a reading voltage to the memristor unit, obtaining a current value output by the memristor unit under the action of the reading voltage, and determining the current resistance value/conductivity value of the memristor unit according to the current value and the reading voltage. For example, a read voltage may be applied to the source line so that the resistance/conductance value of the memristor cell may be determined using ohm's law from the current value output by the bit line.

After the memristor cell is produced, an initialization operation is required. For example, the initialization operation may be to apply a higher voltage to the memristor cell, i.e., a positive voltage pulse is applied to the bit line while the source line is grounded, and the magnitude and time of the positive voltage pulse is higher than those of the set operation. This operation causes the resistance of the memristor cell to change, thereby giving it an initial resistance. Since the resistance values of the memristor cells are random, the resistance value of each memristor cell will be different even under the same initialization conditions.

The inventors of the present disclosure noted that in the highly parallel mode, the conventional array cannot turn off the unselected weight units, resulting in complex external circuit load and additional leakage, thereby affecting the calculation accuracy and energy efficiency.

For example, FIG. 1A is a schematic diagram of a common memristor array for current-mode memory integration. In this array, multiple columns of weight cells (memristor cells) are required to implement a multiplexed analog-to-digital converter (ADC), so that vertical word lines WL (WL [0] - [3 ]) are required to control the gating of the columns, and the word lines of the unselected columns are turned off to reduce the additional leakage power consumption. In this array structure, since the gating of the word lines will cause the turning on of all the weight units on a column corresponding to one source line SL, the conductance of the array load seen at the ADC side is very large, which causes a large current noise, and the voltage deviation corresponding to zero input will cause leakage, which affects the calculation accuracy.

For example, FIG. 1B is a schematic diagram of another common memristor array for current-mode memory cell in which word lines WL and bit lines BL are parallel, so that a row for a zero (0) input (i.e., an input value of 0) can be turned off completely by pulling the word line BL signal low, thereby reducing the impact of leakage on the computation accuracy in the case of zero input. However, this structure cannot be applied to the case of multi-column multiplexing ADC, and columns not participating in calculation may generate additional power consumption, reducing the energy efficiency of calculation.

One calculation error in the calculation is a current error caused by the deviation of the clamp voltage of the source line SL, and fig. 1C is a schematic diagram showing a case where such calculation error is caused. FIG. 1C shows array current at m input parallelism, where G _i Representing the equivalent conductance of the ith row weight element, V _READ[i] The read voltage representing the ith row weight cell when the voltage on the source line SL isAccurate clamping of analog-to-digital converter ADC to clamping voltage V _CLAMP When the current flowing into the ADC is ideal current I _ideal ：

I _ideal ＝Σ _i G _i ·V _READ[i]

When the clamp voltage has a deviation voltage DeltaV, an additional current deviation I is caused _∈ ：

I _∈ ＝ΔV·Σ _i G _i

Wherein the deviation current I _∈ Equal to the product of the clamp offset voltage Δv and the corresponding array conductance sum. The clamping bias voltage comprises static bias caused by mismatch and dynamic bias caused by noise and other factors. The higher the parallelism of the array calculation, the larger the conductance sum, and the larger the current error caused by the clamping deviation voltage.

Another calculation error is a current error caused by zero input voltage deviation of the bit line BL, and fig. 1D is a schematic diagram showing a case where such calculation error is caused. In an ideal state, the bit line BL voltage and the clamp voltage V corresponding to zero input _CLAMP The same applies. As shown in fig. 1D, the bit line BL voltage has a deviation Δv _i This can lead to leakage current in the zero input line, which can cause serious calculation errors.

At least one embodiment of the present disclosure provides a storage unit, where the storage unit includes n weight units and a horizontal gate tube, and n is a positive integer. Each of the n weight cells includes a first memristor element including a first electrode and a second electrode, and a first switching element including a control electrode, a first electrode, and a second electrode. The transverse gate tube comprises a control end, a first end and a second end. The first electrodes of the first memristor elements are electrically connected with the first poles of the first switch elements, the second electrodes of the first memristor elements are used as the second ends of the corresponding weight units and are used for receiving first bit line signals, the second poles of the first switch elements of the n weight units are respectively used as the first ends of the corresponding weight units and are electrically connected with each other and are electrically connected with the first ends of the transverse gate tubes, the control poles of the first switch elements are respectively used for receiving different first word line signals, the second ends of the transverse gate tubes are used for receiving source line signals, and the control ends of the transverse gate tubes are used for receiving second word line signals.

According to the memory cell provided by the at least one embodiment of the present disclosure, through introducing the transverse gate tube and the second word line signal control, the input sparseness can be effectively utilized, and the unselected weight units can be thoroughly turned off, so as to improve the calculation accuracy; the at least one embodiment of the present disclosure may further be used for efficiently multiplexing peripheral circuits, avoiding the leakage problem of the conventional memristor array structure.

The storage unit provided according to the present disclosure is described below in a non-limiting manner by a plurality of embodiments and examples thereof, and as described below, different features of these specific examples or embodiments may be combined with each other without contradiction, thereby obtaining new examples or embodiments, which also fall within the scope of protection of the present disclosure.

Fig. 2A is a schematic diagram of a memory cell based on a 1T1R structure according to at least one embodiment of the present disclosure.

For example, as shown in fig. 2A, a storage unit 30 based on a 1T1R structure provided in an embodiment of the present disclosure includes n weight units 10 and a lateral gate 20, where n is a positive integer. Each weight cell 10 comprises a first memristor element 101 and a first switching element 102, i.e. the weight cell is of a 1T1R structure, the first memristor element 101 comprises a first electrode 1011 and a second electrode 1012, and the first switching element 102 comprises a first pole 1021, a second pole 1022 and a control pole 1023. The lateral gate 20 includes a first end 201, a second end 202, and a control end 203.

For example, as shown in fig. 2A, a first electrode 1011 of the first memristor element 101 is electrically connected to a first pole 1021 of the first switching element 102, a second electrode 1012 of the first memristor element 101 serves as a second end of the corresponding weight cell 102 and is used to receive a first Bit Line (BL) signal, and second poles 1022 of the first switching elements 102 of the n weight cells serve as first ends of the corresponding weight cells 102 and are electrically connected to each other and to the first end 201 of the lateral gate tube 20, respectively. In FIG. 2A, WV [0], WV [1] … … WV [ n-1] respectively represent first and second n first word lines … …, the control electrodes 1023 of the first switching elements are respectively used for receiving different first word line (WV) signals, the second end 202 of the lateral gate 20 is used for receiving the source line SL signal, and the control end 203 of the lateral gate 20 is used for receiving the second word line (WH) signal.

The first word line signal enables control of the multiplexing of n weight cells in the memory cell 30. For the weight unit to be selected to participate in calculation, the first word line signal corresponding to the weight unit can be enabled, and the current of the weight unit is connected to the first end 201 of the lateral gate tube 20 to realize participation in calculation; for the unselected weight units, the first word line signal corresponding to the weight unit can be pulled down to realize the turn-off.

Fig. 2B is a schematic diagram of a memory cell based on a 2T2R structure according to at least one embodiment of the present disclosure.

For example, as shown in fig. 2B, the storage unit 40 based on the 2T2R structure provided in the embodiments of the present disclosure includes n weight units 10 and a lateral gate 20, where n is a positive integer. Each weight cell 10 includes a first memristor element 101, a first switching element 102, a second memristor element 103, and a second switching element 104, i.e., the weight cell is a 2T2R structure.

For example, as shown in fig. 2B, the first electrode 1031 of the second memristor element 103 is electrically connected to the first pole 1041 of the second switching element 104, the second electrode 1032 of the second memristor element 103 serves as the third terminal of the corresponding weighting unit 10 and is used for receiving the second bit line BLD signal, the control terminal 1043 of the second switching element 104 is electrically connected to the control terminal 1023 of the first switching element 102, and the second pole 1042 of the second switching element 104 is electrically connected to the second pole 1022 of the first switching element 102. The remaining components are connected in a manner similar to that of fig. 2A, and are not described in detail herein.

FIG. 3A is a schematic diagram of a memristor array provided by at least one embodiment of the present disclosure, including a plurality of memory cells 30 in FIG. 2A based on a 1T1R structure.

For example, referring to FIGS. 2A and 3A, the memristor array includes p groups of first word lines WV (WV [ n-1:0] -WV [ pn-1 ] (p-1) n), m second word lines WH (WH [0] -WH [ m-1 ]), p source lines SL (SL [0] -SL [ p-1 ]), and m first bit lines BL (BL [0] -BL [ m-1 ]), and a plurality of memory cells 30 as shown in FIG. 2A arranged in m memory cell rows and p memory cell columns along a first direction D1 and a second direction D2. Each set of first word lines WV includes n first word lines, e.g., WV [ n-1:0]. m, n, p, etc. are positive integers, and will not be described in detail.

For example, p sets of first word lines WV extend in the second direction D2 and are connected in one-to-one correspondence with p columns of memory cells 30, each of the p sets of first word lines WV including n first word lines, each of the n first word lines WV being electrically connected to a first pole of a first switching element of a corresponding column of memory cells 30. Taking the first word line WV [ n-1:0] as an example, the first word line WV [ n-1:0] implements control of multiplexing of n weight cells in the memory cell 30. For a weight unit needing to be selected to participate in calculation, enabling a first word line signal corresponding to the weight unit, and connecting the weight unit to a first end of a transverse gate tube in a current manner so as to realize participation in calculation; for the unselected weight units, the first word line signal corresponding to the weight unit can be pulled down to realize the turn-off.

For example, m second word lines WH extend along the first direction D1 and are connected to the m rows of memory cells 30 in a one-to-one correspondence, and each of the m second word lines WH is electrically connected to a control terminal of a lateral gate of the corresponding row of memory cells 30. The second word line WH controls the conduction of the lateral gate, and determines whether the weight cell current selected by the first word line WV is connected to the source line SL.

For example, p source lines SL extend along the second direction D2 and are connected to the p columns of memory cells 30 in a one-to-one correspondence, and each of the p source lines SL is electrically connected to the second end of the lateral gate of the corresponding column of memory cells 30. N weight cells in one memory cell 30 multiplex a set of source line SL outputs.

For example, m first bit lines BL extend in the first direction D1 and are connected in one-to-one correspondence with m rows of memory cells 30, each of the m first bit lines BL being electrically connected to a second electrode of a first memristor element of the corresponding row of memory cells 30. N weight cells in one memory cell 30 multiplex a set of first bit line BL inputs.

Under the condition of zero (0) input, the second word line signal of the corresponding row is pulled down, the gate tube is turned off, and the corresponding weight unit is disconnected from the source line at the moment, so that electric leakage caused by zero input voltage deviation of the first bit line is effectively eliminated, the total electric conduction load on the source line is reduced, and the calculation accuracy is improved.

FIG. 3B is a schematic diagram of a memristor array provided by at least one embodiment of the present disclosure, including the memory cell 40 of FIG. 2B based on the 2T2R structure.

For example, referring to FIGS. 2B and 3B, the memristor array further includes m second bit lines BLD (BLD [0] BLD [ m-1 ]). For example, m second bit lines BLD extend along the first direction D1 and are connected in one-to-one correspondence with the m rows of memory cells 40, each of the m second bit lines BLD being electrically connected to a second electrode of a second memristor element of the corresponding row of memory cells 40. The remaining components of the memristor array and their connection are similar to those in fig. 3A, and are not described here again.

The memristor array provided in at least one embodiment of the present disclosure further includes various driving circuits including a bit line driving circuit and a word line driving circuit, for example, an input circuit, an output circuit, and the like as needed, for example, the input circuit may include a digital-to-analog converter (DAC) and the like, and the output circuit may include an analog-to-digital converter (ADC) and the like.

For example, a bit line driving circuit is electrically connected to the first bit line BL to supply a first bit line signal.

For example, the bit line driving circuit includes an amplifying circuit unit OTA, a first output circuit PM0, a second output circuit NM0, a first control circuit SW1, a second control circuit SW2, a third control circuit SW3, a fourth control circuit SW4, and a bit line driving output terminal OB. For example, the bit line driver circuit employs a Class-AB output stage design.

For example, the amplifying circuit unit OTA includes a first input terminal VIP, a second input terminal VIN, and a first output terminal, a second output terminal.

For example, the first output circuit PM0 is electrically connected to the first node N1, the first voltage terminal V1, and the bit line driving output terminal OB, respectively, and is configured to turn on or off the connection between the bit line driving output terminal OB and the first voltage terminal V1 under the control of the potential of the first node N1; the second output circuit NM0 is electrically connected to the second node N2, the second voltage terminal V0, and the bit line driving output terminal OB, respectively, and is configured to turn on or off the connection between the bit line driving output terminal OB and the second voltage terminal V0 under the control of the potential of the second node N2.

For example, the first control circuit SW1 is electrically connected to the first voltage terminal V1 and the first node N1, respectively, and is configured to turn on or off the connection between the first node N1 and the first voltage terminal V1; the second control circuit SW2 is electrically connected to the second voltage terminal V0 and the second node N2, and is configured to turn on or off the connection between the second node N2 and the second voltage terminal V0; the third control circuit SW3 is electrically connected to the first output terminal of the amplifying circuit unit OTA and the first node N1, respectively, and is configured to turn on or off the connection between the first node N1 and the first output terminal of the amplifying circuit unit OTA; the fourth control circuit SW4 is electrically connected to the second output terminal of the amplifying circuit unit OTA and the second node N2, respectively, and is configured to turn on or off the connection between the second node N2 and the second output terminal of the amplifying circuit unit OTA.

It should be noted that in the case of the 2T 2R-based structure, the memristor array further includes a second bit line, where the driving voltages required by the first bit line and the second bit line are different, so two bit line driving circuits are required for each row of the memristor array, and are electrically connected to the first bit line and the second bit line to provide the first bit line signal and the second bit line signal, respectively.

For example, the word line driving circuit is electrically connected to the second word line to supply the second word line signal.

For example, the word line driving circuit includes a fifth control circuit SW5, a sixth control circuit SW6, and a word line driving output OW. The fifth control circuit SW5 is electrically connected to the first voltage terminal V1 and the word line driving output terminal OW, respectively, and is configured to turn on or off the connection between the first voltage terminal V1 and the word line driving output terminal OW; the sixth control circuit SW6 is electrically connected to the second voltage terminal V0 and the word line driving output terminal OW, respectively, and is configured to turn on or off the connection between the second voltage terminal V0 and the word line driving output terminal OW.

As shown in fig. 4A, in the case of zero input, the voltage applied to the first input terminal VIP of the amplifying circuit unit OTA is equal to the clamp voltage on the source line SL, and at this time, the first control circuit SW1 and the second control circuit SW2 are turned on, and the third control circuit SW3 and the fourth control circuit SW4 are turned off, so that the control terminal of the first output circuit PM0 is connected to the first voltage terminal V1, and the control terminal of the second output circuit NM0 is connected to the second voltage terminal V2. For example, the first voltage terminal V1 is a power source, and the second voltage terminal V2 is Ground (GND).

As shown in fig. 4B, in the case of non-zero input, the voltage applied to the first input terminal VIP of the amplifying circuit unit OTA is equal to the sum of the input voltage and the clamp voltage, at this time, the first control circuit SW1 and the second control circuit SW2 are turned off, and the third control circuit SW3 and the fourth control circuit SW4 are turned on, so that the control terminals of the first output circuit PM0 and the second output circuit NM0 are respectively connected to the two output terminals of the amplifying circuit unit OTA, and the bit line driving output terminal OB outputs the calculated voltage required for the first bit line BL. At the same time, the fifth control circuit SW5 is turned on, the sixth control circuit SW6 is turned off, and the word line driving output end OW outputs a voltage required for driving the second word line WH, and pulls the corresponding second word line WH high.

For example, the first input VIP and the second input VIN of the amplifying circuit unit OTA are connected in a feedback structure, i.e. in the form of a unity gain buffer. Therefore, no voltage needs to be applied to VIN, and the VIN voltage is consistent with the VIP voltage through feedback dummy short, so that the two output ends of the amplifying circuit unit OTA output consistent voltages.

Based on the driving circuit, not only the zero input corresponding weight unit can be completely turned off, but also the bit line driving circuit of the zero input corresponding row can be completely turned off, so that the calculation power consumption of the network under the condition of higher input sparseness is greatly reduced.

Fig. 5 is a schematic diagram of a memory integrated circuit according to at least one embodiment of the present disclosure.

As shown in FIG. 5, the integrated circuit includes the memristor array provided in at least one embodiment described above, the memristor array includes p groups of first word lines WV (WV [ n-1:0] WV [ pn-1 ] (p-1) n ]), m second word lines WH (WH [0] WH [ m-1 ]), p source lines SL (SL [0] SL [ p-1 ]), and m first bit lines BL (BL [0] BL [ m-1 ]), and a plurality of memory cells 30 arranged in m memory cell rows and p memory cell columns along the first direction D1 and the second direction D2. The memristor array further includes a drive circuit 50 including a bit line drive circuit 51 and a word line drive circuit 52.

As shown in fig. 5, the integrated circuit further includes an input circuit 61, an output circuit 62, a first word line program drive circuit 71, a second word line program drive circuit 72, a first bit line program drive circuit 73, and a source line program drive circuit 74. The input circuit 61 comprises a plurality of digital-to-analog converters DACs and the output circuit 62 comprises a plurality of analog-to-digital converters ADCs.

For example, m digital-to-analog converters DAC (DAC [0] - [ m-1 ]) are electrically connected to the bit line driving circuits 51 of the corresponding row in one-to-one correspondence, and the digital-to-analog converters DAC are used for converting the input digital signals into analog signals so as to input the analog signals to the first input terminals of the amplifying circuit units of the corresponding bit line driving circuits when performing parallel computation.

For example, the first word line program driving circuit 71 is electrically connected to the first word lines WV (WV [ n-1:0] to WV [ pn-1 (p-1) n ]) to provide a first word line program signal, and the second word line program driving circuit 72 is electrically connected to the second word lines WH (WH [0] to WH [ m-1 ]) to provide a second word line program signal, and the first word line program signal and the second word line program signal can be used to select a cell to be operated.

For example, the first bit line program driving circuit 73 is electrically connected to the first bit lines BL (BL [0] to BL [ m-1 ]) to provide a first bit line program signal, and the source line program driving circuit 74 is electrically connected to the source lines SL (SL [0] to SL [ p-1 ]) to provide a source line program signal, which may be used to provide a set voltage to a cell requiring a set operation, and the source line program signal may be used to provide a reset voltage to a cell requiring a reset operation.

For example, p analog-to-digital converters ADC (ADC [0] - [ p-1 ]) are electrically connected to the source lines SL (SL [0] - [ p-1 ]) in one-to-one correspondence, and the analog-to-digital converters ADC are used for converting the analog signals into digital signals and providing clamping voltages for the source lines for calculation. The n weight units of each storage unit in the memristor array are multiplexed into the same ADC circuit, and one of the n weight units is controlled by the first word line WV to participate in calculation. The circuit architecture can improve the calculation accuracy and the energy efficiency of the integrated circuit.

For example, the integrated circuit may further include a front-end control circuit (not shown) for providing control voltages of the first control circuit to the sixth control circuit in the bit line driving circuit 51 based on zero/non-zero data of the input digital signal. For example, the front-end control circuit may include analog/digital circuits, etc.

It should be noted that, in the case of the 2T 2R-based structure, the memristor array further includes a second bit line, and at this time, the integrated circuit further includes a second bit line programming driving circuit, and the second bit line programming driving circuit is electrically connected to the second bit line to provide a second bit line programming signal, where the second bit line programming signal may be used to provide a set voltage to a cell that needs to perform a set operation. Otherwise, in the case of the 2T 2R-based structure, the remaining components of the integrated circuit and their connection are similar to those in fig. 5, and are not described here again.

At least one embodiment of the present disclosure also provides a method of operation for a memristor array as described above, including step S1 and step S2.

Step S1: and applying a second selected voltage to the second word line corresponding to the row where the target operation unit is located, and applying a first selected voltage to the first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit.

For example, a first selection voltage may be applied through the first word line program driving circuit 71 as shown in fig. 5, and a second selection voltage may be applied through the second word line program driving circuit 72 as shown in fig. 5.

Step S2: an operating voltage is applied to the first bit line and the source line corresponding to the target operating unit.

For example, a memristor array includes an operational mode and a computation mode. When the memristor array is in the operation mode, the memristor unit is in an initialized state, and values of elements in the matrix which need to be multiplied can be written into the memristor array, for example, weight values are mapped into conductance values of the memristor. For example, writing is realized by a set operation and a reset operation.

For example, when the set operation is performed, step S2 is further: an operation voltage for setting is applied to the first bit line and the source line corresponding to the target operation unit.

Fig. 6A is a schematic diagram of a set operation method according to at least one embodiment of the present disclosure. As shown in fig. 6A, the specific operation method is as follows:

applying a second selected voltage to a second word line WH [1] corresponding to a row where a target operation unit to be set is located, and applying a first selected voltage to a first word line WV [ n-1] corresponding to a column where the target operation unit to be set is located, thereby selecting the target operation unit to be set;

First bit line BL [1] corresponding to target operation unit]Applying a set voltage V _SET The source line SL [0 ] corresponding to the target operation unit is pulled down]And pulls down the voltages on the remaining signal lines, thereby implementing a set operation on the target operation unit. For example, the set voltage V _SET The source line voltage may be applied through the first bit line program driving circuit 73 as shown in fig. 5, and the source line voltage may be applied through the source line program driving circuit 74 as shown in fig. 5.

For example, when the reset operation is performed, step S2 is further: an operation voltage for reset is applied to the first bit line and the source line corresponding to the target operation unit.

Fig. 6B is a schematic diagram of a reset operation method according to at least one embodiment of the present disclosure. As shown in fig. 6B, the specific operation method is as follows:

applying a second selected voltage to a second word line WH [1] corresponding to a row where a target operation unit to be reset is located, and applying a first selected voltage to a first word line WV [ n-1] corresponding to a column where the target operation unit to be reset is located, thereby selecting the target operation unit to be reset;

source line SL [0 ] corresponding to target operation unit]Applying a reset voltage V _RESET Pull down the first bit corresponding to the target operation unitLine BL [1]]And pulls down the voltages on the remaining signal lines, thereby realizing a reset operation for the target operation unit. For example, the first bit line voltage may be applied by the first bit line program drive circuit 73 as shown in FIG. 5, resetting the voltage V _RESET Can be applied by a source line programming drive circuit 74 as shown in fig. 5.

For example, when the memristor array is in a calculation mode, the memristors in the memristor array are in a conductive state available for calculation, the voltage input on the first bit line does not change the conductance value of the memristor, and for example, the calculation can be completed by performing a multiply-add operation through the memristor array.

For example, when performing parallel computing operations, the target operation unit includes a non-zero input unit, step S2 is further: an input signal is applied to a first bit line corresponding to a target operation unit, and a source line voltage is applied to a column in which the target operation unit is located.

FIG. 6C is a schematic diagram of a parallel computing operation method according to at least one embodiment of the present disclosure. As shown in fig. 6C, the specific operation method is:

and applying a second selected voltage to the second word lines WH [0] to WH [ m-1] corresponding to the rows where all the target operation units participating in calculation are located, and applying a first selected voltage to the first word lines WV [0] to WV [ n-1] corresponding to the columns where all the target operation units participating in calculation are located, so that the target operation units participating in calculation are selected. Specifically, assuming that the whole array has only the second behavior zero input and the rest behaviors are non-zero input, for a non-zero input unit, the voltages on the corresponding second word lines WH [0], WH [2] to WH [ m-1] are pulled up, and for a zero input unit, the voltages on the corresponding second word lines WH [1] are pulled down;

An input signal is applied to the first bit lines BL [0] to BL [ m-1] corresponding to the target operation unit, and a clamping voltage is applied to the source line SL [0] of the column where the target operation unit is located, so that parallel computing operation is realized. For example, the input digital signal may be converted into an analog signal by the digital-to-analog converter DAC, and then the calculated voltage, that is, the input signal applied to the first bit line, may be output by the bit line driving circuit 51. For example, the clamp voltage applied on the source line may be provided by an analog-to-digital converter ADC.

At least one embodiment of the present disclosure further provides an electronic device, and fig. 7 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. The electronic device may be, for example, a server device or a terminal device, and may be used, for example, in a server, a computer, a controller, or the like.

For example, as shown in fig. 7, an electronic device 700 includes a selection module 701 and an operation module 702.

For example, the selection module 701 is configured to apply a second selection voltage to a second word line corresponding to a row where a target operation unit is located, and apply a first selection voltage to a first word line corresponding to a column where the target operation unit is located, thereby selecting the target operation unit. For example, the selection module 701 may include a first word line program driving circuit 71 and a second word line program driving circuit 72 as shown in fig. 5.

For example, the operation module 702 is configured to apply an operation voltage to the first bit line and the source line corresponding to the target operation unit.

For example, the operation module 702 is further configured to apply an operation voltage for setting to the first bit line and the source line corresponding to the target operation unit. For example, the operation module 702 is further configured to apply an operation voltage for reset to the first bit line and the source line corresponding to the target operation unit. For example, the operation module 702 may include the first bit line program driving circuit 73 and the source line program driving circuit 74 shown in fig. 5.

For example, the operation module 702 is further configured to apply an input signal to a first bit line corresponding to a target operation unit and to apply a source line voltage to a column in which the target operation unit is located. For example, the operation module 702 may further include the input circuit 61, the output circuit 62, and the bit line driving circuit 51 shown in fig. 5.

For the relevant content of the selection module 701 and the operation module 702, reference may be made to the relevant descriptions of step S1 and step S2 in the above embodiments of the operation method, which are not repeated herein.

One or more embodiments of the present disclosure provide a memory cell, memristor array, memory integrated circuit, operating method, and electronic device with one or more of the following beneficial effects:

(1) The memory cell provided by at least one embodiment of the present disclosure may be effectively applied to a memristor array, and by introducing a lateral gate tube and a lateral second word line signal control, a row corresponding to zero input may be completely turned off, so as to reduce source line conductance and load, reduce zero input leakage current, and improve calculation accuracy.

(2) The memristor array provided by at least one embodiment of the present disclosure includes a bit line driving circuit and a lateral second word line driving circuit, which can effectively reduce power consumption of a peripheral circuit under zero input, thereby improving computing energy efficiency of a system under a high sparseness network.

(3) The integrated circuit for memory operation provided by at least one embodiment of the present disclosure, which is implemented based on the memristor array of the memory cell of the above embodiment, can be used to solve the problem of reduced calculation accuracy caused by excessive array conductance load in a high parallel integrated circuit for memory operation.

(4) The integrated circuit for memory operation provided by at least one embodiment of the present disclosure is implemented based on the memristor array of the memory cell in the foregoing embodiment, and may be matched with a drive circuit capable of being turned off, so as to effectively improve the calculation energy efficiency of the integrated circuit for memory operation when calculating the high input sparseness network.

While the disclosure has been described in detail with respect to the general description and the specific embodiments thereof, it will be apparent to those skilled in the art that certain modifications and improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications or improvements may be made without departing from the spirit of the disclosure and are intended to be within the scope of the disclosure as claimed.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A memory cell, comprising:

the transverse gate tube comprises a control end, a first end and a second end,

2. The memory cell of claim 1 wherein each of the n weight cells further comprises a second memristor element and a second switching element,

the first electrode of the second memristor element is electrically connected with the first pole of the second switching element, the second electrode of the second memristor element is used as the third end of the corresponding weight unit and is used for receiving the second bit line signal, the control end of the second switching element is electrically connected with the control end of the first switching element, and the second pole of the second switching element is electrically connected with the second pole of the first switching element.

3. A memristor array, comprising:

the plurality of memory cells of claim 1, wherein the plurality of memory cells are arranged in m memory cell rows and p memory cell columns along a first direction and a second direction, m and p being positive integers;

4. The memristor array of claim 3, wherein each of the n weight cells further comprises a second memristor element and a second switching element,

the memristor array further includes:

5. The memristor array of claim 3, further comprising a drive circuit, wherein the drive circuit comprises:

6. The memristor array of claim 5, wherein,

the bit line driving circuit comprises an amplifying circuit unit, a first output circuit, a second output circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and a bit line driving output end;

the amplifying circuit unit comprises a first input end, a second input end, a first output end and a second output end;

the first output circuit is respectively and electrically connected with a first node, a first voltage end and the bit line driving output end and is configured to conduct or break the connection between the bit line driving output end and the first voltage end under the control of the potential of the first node;

the second output circuit is respectively and electrically connected with a second node, a second voltage end and the bit line driving output end and is configured to conduct or break the connection between the bit line driving output end and the second voltage end under the control of the potential of the second node;

The first control circuit is electrically connected with the first voltage terminal and the first node respectively and is configured to conduct or break connection between the first node and the first voltage terminal;

the second control circuit is respectively and electrically connected with the second voltage terminal and the second node and is configured to conduct or break the connection between the second node and the second voltage terminal;

the third control circuit is electrically connected with the first output end of the amplifying circuit unit and the first node respectively and is configured to switch on or off the connection between the first node and the first output end of the amplifying circuit unit;

the fourth control circuit is electrically connected with the second output end of the amplifying circuit unit and the second node respectively and is configured to turn on or off connection between the second node and the second output end of the amplifying circuit unit.

7. The memristor array of claim 5 or 6, wherein,

the word line driving circuit comprises a fifth control circuit, a sixth control circuit and a word line driving output end;

the fifth control circuit is electrically connected with the first voltage terminal and the word line driving output terminal respectively and is configured to switch on or off the connection between the first voltage terminal and the word line driving output terminal;

The sixth control circuit is electrically connected to the second voltage terminal and the word line driving output terminal, respectively, and is configured to turn on or off connection between the second voltage terminal and the word line driving output terminal.

8. A memory integrated circuit comprising the memristor array of any one of claims 3-7.

9. A method of operation of the memristor array of any one of claims 3-7, comprising:

applying a second selected voltage to a second word line corresponding to a row where a target operation unit is located, and applying a first selected voltage to a first word line corresponding to a column where the target operation unit is located, thereby selecting the target operation unit;

and applying an operation voltage to the first bit line and the source line corresponding to the target operation unit.

10. The operating method of claim 9, wherein the applying the operating voltage to the first bit line and the source line corresponding to the target operating unit comprises:

and applying an operation voltage for setting to the first bit line and the source line corresponding to the target operation unit.

11. The operating method of claim 9, wherein the applying the operating voltage to the first bit line and the source line corresponding to the target operating unit comprises:

And applying an operation voltage for resetting to the first bit line and the source line corresponding to the target operation unit.

12. The method of operation of claim 9, wherein the target operation unit comprises a non-zero input unit,

the applying the operation voltage to the first bit line and the source line corresponding to the target operation unit includes:

applying an input signal to a first bit line corresponding to the target operation unit;

and applying a source line voltage to the column where the target operation unit is located.