CN117559925B

CN117559925B - Multimode high-efficiency power amplifier

Info

Publication number: CN117559925B
Application number: CN202410046488.5A
Authority: CN
Inventors: 胡柳林; 唐小宏; 刘勇
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2024-01-12
Filing date: 2024-01-12
Publication date: 2024-03-29
Anticipated expiration: 2044-01-12
Also published as: CN117559925A

Abstract

The invention discloses a multimode high-efficiency power amplifier, which belongs to the technical field of integrated circuit design and comprises an input matching shunt network, a first common source amplifying network, a self-adaptive linear bias network, a second common source amplifying network and an output matching shunt network; the invention adopts the common source amplifying network and a novel four-way synthesis structure to realize high-power output, suppresses the impedance traction phenomenon between branches of the amplifier of the traditional power synthesis structure, simplifies the output matching network, ensures that the amplifier can realize multi-mode operation of multiple power class output, simultaneously can realize impedance matching and low insertion loss output, and has the advantages of multi-mode operation, high efficiency, high power output capability, high power gain, good input and output matching characteristics and the like.

Description

Multimode high-efficiency power amplifier

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a multimode high-efficiency power amplifier.

Background

With the rapid development of satellite communication markets with requirements for high-speed satellite communication, broadband digital transmission and the like, the radio frequency front-end transceiver also iterates towards the directions of high integration, low power consumption, miniaturization and low price.

The power amplifier is used as an important module of the transmitter, influences the quality of the whole communication signal, is also the part with the largest energy consumption in the transceiver, is realized by adopting an integrated circuit process design, has certain restriction on the functional performance, and is mainly characterized in the following aspects:

(1) Compatibility of different output power modes is limited: the trend of communication terminal equipment gradually deviates to miniaturization and multifunctionality, two or more power modes can be provided by a power amplifier, the branches synthesized by the traditional power amplifier are limited by a synthesized structure, serious impedance traction phenomenon exists, and multiple power modes cannot be realized, so that more complex circuit design is required when the application requirement exists, and the cost is multiplied.

(2) High efficiency high power capability is limited: the traditional power amplifier synthesis structure cannot be fully compatible with synthesis function and matching function, so that the output structure of the amplifier is complex, the insertion loss is large, the miniaturization and low cost of the amplifier are not facilitated, and the high efficiency and high power capability are limited.

At present, the high-efficiency high-power amplifier has a plurality of structures, and when the amplifier is required to meet various parameters, the multi-mode operation is considered, and the performance of other power modes is always sacrificed at the cost of preserving the performance of one power mode, for example, the power or efficiency index is deteriorated, so that the practical application requirement cannot be met.

It can be seen that the design difficulties of the multimode high-efficiency high-power amplifier based on the integrated circuit technology are as follows: (1) the difficulty in realizing the multi-mode working function is high; and (2) the difficulty of achieving multi-mode high efficiency and high power is high.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a multimode high-efficiency power amplifier, which solves the problems of higher difficulty in realizing multimode working functions of the existing amplifier and higher difficulty in achieving multimode high-efficiency high-power.

In order to achieve the aim of the invention, the invention adopts the following technical scheme: a multimode high-efficiency power amplifier comprises an input matching shunt network, a first common source amplifying network, a self-adaptive linear bias network, a second common source amplifying network and an output matching circuit network;

the input end of the input matching shunt network is used as the input end of the multimode high-efficiency power amplifier, and the first output end and the second output end of the input matching shunt network are respectively connected with the first input end of the first common-source amplifying network and the first input end of the second common-source amplifying network;

the first output end and the second output end of the self-adaptive linear bias network are respectively connected with the first input end of the first common-source amplifying network and the first input end of the second common-source amplifying network;

The third output end and the fourth output end of the self-adaptive linear bias network are respectively connected with the second input end of the first common-source amplifying network and the second input end of the second common-source amplifying network;

the fifth output end and the sixth output end of the self-adaptive linear bias network are respectively connected with the third input end of the first common-source amplifying network and the third input end of the second common-source amplifying network;

the first output end and the second output end of the first common source amplifying network are respectively connected with the first input end and the second input end of the output matching circuit network, and the first output end and the second output end of the second common source amplifying network are respectively connected with the third input end and the fourth output end of the output matching circuit network;

and the output end of the output matching circuit network is used as the output end of the multimode high-efficiency power amplifier.

Further, the first common source amplifying network comprises a driving stage amplifying unit P1, a driving stage amplifying unit P3, a driving stage amplifying unit P5 and a first inter-stage matching shunt network; the second common source amplifying network comprises a driving stage amplifying unit P2, a driving stage amplifying unit P4, a driving stage amplifying unit P6 and a second interstage matching shunt network;

The input end of the driving stage amplifying unit P1 is used as a first input end of the first common source amplifying network, the driving stage amplifying unit P1 is connected with the input end of a first inter-stage matching shunt network, the output end of the first inter-stage matching shunt network is connected with the input ends of the driving stage amplifying unit P3 and the driving stage amplifying unit P5, and the input ends of the driving stage amplifying unit P3 and the driving stage amplifying unit P5 are respectively used as a second input end and a third input end of the first common source amplifying network; the output ends of the driving stage amplifying unit P3 and the driving stage amplifying unit P5 are respectively used as a second output end and a first output end of the first common source amplifying network;

the input end of the driving stage amplifying unit P2 is used as the first input end of the second common source amplifying network, the driving stage amplifying unit P2 is connected with the input end of the second inter-stage matching shunt network, the output end of the second inter-stage matching shunt network is connected with the input ends of the driving stage amplifying unit P4 and the driving stage amplifying unit P6, and the input ends of the driving stage amplifying unit P4 and the driving stage amplifying unit P6 are respectively used as the second input end and the third input end of the second common source amplifying network; the output ends of the driving stage amplifying unit P4 and the driving stage amplifying unit P6 are respectively used as a first output end and a second output end of the second common source amplifying network.

Further, the input matching shunt network comprises a capacitor C1, a capacitor C2 and a capacitor C3; microstrip line TL1, microstrip line TL2, microstrip line TL3, microstrip line TL4, microstrip line TL5, microstrip line TL6, microstrip line TL7, microstrip line TL8, microstrip line TL9; a resistor R1 and a resistor R2; a transformer T1;

one end of the capacitor C1 is used as an input end of an input matching shunt network, the other end of the capacitor C1 is connected with one end of the microstrip line TL1, the other end of the microstrip line TL1 is connected with one end of the microstrip line TL2 and one end of the suspended microstrip line TL3, the other end of the microstrip line TL2 is connected with one end of the input side of the transformer T1, and the other end of the input side of the transformer T1 is grounded;

one end of the output side of the transformer T1 is connected with one end of a microstrip line TL9, the other end of the microstrip line TL9 is respectively connected with one ends of a microstrip line TL7 and a suspended microstrip line TL8, the other end of the microstrip line TL7 is respectively connected with one end of a capacitor C2 and one end of a resistor R1, and the other end of the capacitor C2 and the other end of the resistor R1 are mutually connected and serve as a first output end of the input matching circuit network;

the other end of the output side of the transformer T1 is connected with one end of a microstrip line TL4, the other end of the microstrip line TL4 is connected with one end of a microstrip line TL6 and one end of a suspended microstrip line TL5 respectively, the other end of the microstrip line TL6 is connected with one end of a capacitor C3 and one end of a resistor R2 respectively, and the other end of the capacitor C3 and the other end of the resistor R2 are connected with each other and serve as a second output end of the input matching circuit network.

The beneficial effects of the above-mentioned further scheme are:

the input matching shunt network adopted by the invention can realize the signal self-excitation suppression function so as to improve the stability of the circuit besides impedance matching and broadband equal power distribution of a radio frequency input signal, wherein the capacitor C1, the microstrip line TL2 and the microstrip line TL3 realize first impedance transformation, the T1 transformer and the microstrip lines TL 4-TL 9 realize equal power distribution and second impedance transformation, and the bandwidth performance is improved by the two impedance transformations; the first RC suppression circuit (resistor R1, capacitor C2) and the second RC suppression circuit (resistor R2, capacitor C3) realize suppression of potential unstable signals of the transistor.

Further, the adaptive linear bias network includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a transistor M23, a transistor M24; resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20; capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, and capacitor C21;

The emitter of the transistor M9 is connected with a grounding resistor R4, the base of the transistor M9 is connected with the collector of the transistor M9 and the emitter of the transistor M7 respectively, the collector of the transistor M7 is connected with one end of a resistor R3, the base of the transistor M7, a grounding capacitor C16 and the base of the transistor M8 respectively, the other end of the resistor R3 and the collector of the transistor M8 are connected with a power supply VCC, and the emitter of the transistor M8 is connected with a grounding resistor R5 and serves as a first output end of the self-adaptive linear bias network;

the emitter of the transistor M12 is connected with a grounding resistor R7, the base of the transistor M12 is respectively connected with the collector of the transistor M12 and the emitter of the transistor M10, the collector of the transistor M10 is respectively connected with one end of a resistor R6, the base of the transistor M10, a grounding capacitor C17 and the base of the transistor M11, the other end of the resistor R6 and the collector of the transistor M11 are both connected with a power supply VCC, and the emitter of the transistor M11 is connected with a grounding resistor R8 and serves as a third output end of the self-adaptive linear bias network;

the emitter of the transistor M15 is connected with a grounding resistor R10, the base of the transistor M15 is respectively connected with the collector of the transistor M15 and the emitter of the transistor M13, the collector of the transistor M13 is respectively connected with one end of a resistor R9, the base of the transistor M13, a grounding capacitor C18 and the base of the transistor M14, the other end of the resistor R9 and the collector of the transistor M14 are both connected with a power supply VCC, and the emitter of the transistor M14 is connected with a grounding resistor R11 and serves as a fifth output end of the self-adaptive linear bias network;

The emitter of the transistor M18 is connected with a grounding resistor R13, the base of the transistor M18 is respectively connected with the collector of the transistor M18 and the emitter of the transistor M16, the collector of the transistor M16 is respectively connected with one end of a resistor R12, the base of the transistor M16, a grounding capacitor C19 and the base of the transistor M17, the other end of the resistor R12 and the collector of the transistor M17 are both connected with a power supply VCC, and the emitter of the transistor M17 is connected with a grounding resistor R14 and serves as a second output end of the self-adaptive linear bias network;

the emitter of the transistor M21 is connected with a grounding resistor R16, the base of the transistor M21 is respectively connected with the collector of the transistor M21 and the emitter of the transistor M19, the collector of the transistor M19 is respectively connected with one end of a resistor R15, the base of the transistor M19, a grounding capacitor C20 and the base of the transistor M20, the other end of the resistor R15 and the collector of the transistor M20 are both connected with a power supply VCC, and the emitter of the transistor M20 is connected with a grounding resistor R17 and serves as a fourth output end of the self-adaptive linear bias network;

the emitter of the transistor M24 is connected with the grounding resistor R19, the base of the transistor M24 is connected with the collector of the transistor M24 and the emitter of the transistor M22 respectively, the collector of the transistor M22 is connected with one end of the resistor R18, the base of the transistor M22, the grounding capacitor C21 and the base of the transistor M23 respectively, the other end of the resistor R18 and the collector of the transistor M23 are connected with the power supply VCC, and the emitter of the transistor M23 is connected with the grounding resistor R20 and serves as a sixth output end of the adaptive linear bias network.

The beneficial effects of the above-mentioned further scheme are:

the invention adopts the self-adaptive linear bias network, the network is made up of two groups of three bias circuit units, six units, each group bias circuit provides bias for each amplifier of the first and second common source amplifying network, each bias unit can select the mutually independent power-on mode, thus can control the on or off of each amplifier independently, realize the multimode work of different power class output through opening or closing each amplifier synthesized by final stage; meanwhile, the linear capacitors (C16-C21) added by the bias units can play a role in adjusting the bias points of the amplifying network in real time along with the change of input power, so that the linearity of the amplifier is improved; the transistors M9, M12, M15, M18, M21 and M24 are used as the temperature compensation of the bias circuit, and the power supply bias can be adjusted in real time according to the temperature change, so that the performance degradation of the amplifier caused by temperature fluctuation is reduced. The bias network of the conventional amplifier mostly adopts a simple peripheral voltage division network, and the working mode is single.

Further, the first common source amplifying network comprises a transistor M1, a transistor M2 and a transistor M3; capacitor C4, capacitor C6, capacitor C8, and capacitor C9; microstrip line TL13, microstrip line TL14, microstrip line TL15, microstrip line TL28; a transformer T2;

The base electrode of the transistor M1 is used as a first input end of the first common source amplifying network, the emitter electrode of the transistor M1 is grounded, the collector electrode of the transistor M1 is respectively connected with a power supply VCC and one end of a capacitor C4, the other end of the capacitor C4 is respectively connected with one end of a capacitor C6 and one end of a microstrip line TL13, the other end of the capacitor C6 is connected with a grounding microstrip line TL28, the other end of the microstrip line TL13 is respectively connected with one ends of a suspended microstrip line TL15 and a microstrip line TL14, the other end of the microstrip line TL14 is connected with one end of an input side of a transformer T2, and the other end of the input side of the transformer T2 is grounded;

one end of the output side of the transformer T2 is connected with one end of a capacitor C9, the other end of the output side of the transformer T2 is connected with a capacitor C8, the other end of the capacitor C9 is connected with a base electrode of a transistor M3 and serves as a second input end of the first common source amplifying network, and the other end of the capacitor C8 is connected with a base electrode of the transistor M2 and serves as a third input end of the first common source amplifying network;

the emitter of the transistor M2 is grounded, the collector of the transistor M2 is used as a first output end of the first common source amplifying network, the emitter of the transistor M3 is grounded, and the collector of the transistor M3 is used as a second output end of the first common source amplifying network.

Further, the second common source amplifying network comprises a transistor M4, a transistor M5 and a transistor M6; a capacitor C5, a capacitor C10, a capacitor C11; a transformer T3; microstrip line TL10, microstrip line TL11, microstrip line TL12, microstrip line TL29;

the base electrode of the transistor M4 is used as a first input end of the second common source amplifying network, the emitter electrode of the transistor M4 is grounded, the collector electrode of the transistor M4 is respectively connected with a power supply VCC and one end of a capacitor C5, the other end of the capacitor C5 is respectively connected with one end of a capacitor C7 and one end of a microstrip line TL10, the other end of the capacitor C7 is connected with a grounding microstrip line TL29, the other end of the microstrip line TL10 is respectively connected with one ends of a suspended microstrip line TL12 and a microstrip line TL11, the other end of the microstrip line TL11 is connected with one end of an input side of a transformer T3, and the other end of the input side of the transformer T3 is grounded;

one end of the output side of the transformer T3 is connected with one end of a capacitor C10, the other end of the output side of the transformer T3 is connected with a capacitor C11, the other end of the capacitor C10 is connected with the base electrode of a transistor M5 and serves as a second input end of the second common source amplifying network, and the other end of the capacitor C11 is connected with the base electrode of a transistor M6 and serves as a third input end of the second common source amplifying network;

The emitter of the transistor M5 is grounded, the collector of the transistor M5 is used as the first output end of the second common-source amplifying network, the emitter of the transistor M6 is grounded, and the collector of the transistor M6 is used as the second output end of the second common-source amplifying network.

The beneficial effects of the above-mentioned further scheme are:

compared with the conventional amplification network, the common source amplification network adopts the transformer for impedance transformation and realizes equal power distribution of signals, thereby improving the defects of high insertion loss and narrow bandwidth of the conventional common source amplification network, enabling the common source amplification network to realize good power output and simultaneously taking into account impedance matching and power distribution; the LC resonant circuit (the capacitor C7, the microstrip line TL29, the capacitor C6 and the microstrip line TL 28) is added to the first-stage output of the amplifying network and used for suppressing the resonance frequency of the secondary output, so that the efficiency of the first-stage amplifier (the transistor M1 and the transistor M4) is improved, and the conventional amplifying network interstage matching does not adopt the network, the interstage power distribution circuit has no impedance matching function and has a narrow bandwidth.

Further, the output matching network comprises a multiplexing transformer T4; microstrip line TL16, microstrip line TL17, microstrip line TL18, microstrip line TL19, microstrip line TL20, microstrip line TL21, microstrip line TL22, microstrip line TL23, microstrip line TL24, microstrip line TL25, microstrip line TL26, microstrip line TL27, microstrip line TL30, microstrip line TL31, microstrip line TL32, microstrip line TL33; capacitor C12, capacitor C13, capacitor C14, and capacitor C15;

The first input side and the second input side of the multiplexing transformer T4 are connected with a power supply VCC;

one end of the first input side of the multiplexing transformer T4 is connected with one end of a microstrip TL27, the other end of the microstrip TL27 is connected with one end of a microstrip TL25 and one end of a suspended microstrip TL26, the other end of the microstrip TL25 is connected with one end of a capacitor C12 and is used as the first input end of the output matching network, and the other end of the capacitor C12 is connected with a grounding microstrip TL 32;

the other end of the first input side of the multiplexing transformer T4 is connected with one end of a microstrip TL24, the other end of the microstrip TL24 is respectively connected with one end of a microstrip TL22 and one end of a suspended microstrip TL23, the other end of the microstrip TL22 is connected with one end of a capacitor C13 and is used as a second input end of the output matching network, and the other end of the capacitor C13 is connected with a grounding microstrip TL 33;

one end of the second input side of the multiplexing transformer T4 is connected with one end of a microstrip TL17, the other end of the microstrip TL17 is connected with one end of a microstrip TL16 and one end of a suspended microstrip TL18, the other end of the microstrip TL16 is connected with one end of a capacitor C14 and is used as a third input end of the output matching network, and the other end of the capacitor C14 is connected with a grounding microstrip TL 30;

The other end of the second input side of the multiplexing transformer T4 is connected with one end of a microstrip TL20, the other end of the microstrip TL20 is respectively connected with one end of a microstrip TL19 and one end of a suspended microstrip TL21, the other end of the microstrip TL19 is connected with one end of a capacitor C15 and is used as a fourth input end of the output matching circuit network, and the other end of the capacitor C15 is connected with a grounding microstrip TL 31;

one end of the output side of the multiplexing transformer T4 is grounded, and the other end of the output side of the multiplexing transformer T4 is used as the output end of the output matching network.

The beneficial effects of the above-mentioned further scheme are:

the output matching circuit network adopted by the invention performs equal power synthesis on four paths of output signals, the T-shaped matching network is adopted to complete the first impedance transformation, the multipath synthesis transformer T4 is adopted to complete the second impedance transformation and signal combination, the collector power supply of each final-stage amplifier is fed through the multipath synthesis transformer T4, and the inductance bit of a choke coil is saved; the power synthesis is carried out by adopting the multi-path synthesis transformer T4 after the first impedance transformation, so that the impedance traction phenomenon among all branches of the amplifier with the traditional power synthesis structure is restrained, all paths of amplifiers synthesized by the final stage can be started or closed, and different numbers of starting amplifiers correspond to different power class outputs, so that multimode operation is realized; in addition, the four-way final-stage amplifier LC resonant circuits (capacitor C12, microstrip line TL 32), (capacitor C13, microstrip line TL 33), (capacitor C14, microstrip line TL 30) and (capacitor C15, microstrip line TL 31) are used for suppressing the secondary output resonant frequency and further improving the efficiency of the final-stage amplifiers (M2, M3, M5 and M6). The output matching circuit network adopted by the invention not only saves the inductance position of the choke coil and reduces the area of the output network, but also can support multi-mode work with different power grades, and the impedance matching network has wide bandwidth and low insertion loss.

The beneficial effects of the invention are as follows:

the invention adopts the common source amplifying network and a novel four-way synthesis structure to realize high-power output, suppresses the impedance traction phenomenon between branches of the amplifier of the traditional power synthesis structure, simplifies the output matching network, ensures that the amplifier can realize multi-mode operation of multiple power class output, simultaneously can realize impedance matching and low insertion loss output, and has the advantages of multi-mode operation, high efficiency, high power output capability, high power gain, good input and output matching characteristics and the like.

Drawings

Fig. 1 is a block diagram of a multimode high-efficiency power amplifier according to the present invention.

Fig. 2 is a schematic diagram of a multimode high-efficiency power amplifier circuit provided by the invention.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.

The embodiment of the invention provides a multimode high-efficiency power amplifier, which is shown in figure 1 and comprises an input matching shunt network, a first common source amplifying network, a self-adaptive linear bias network, a second common source amplifying network and an output matching shunt network;

The first output end and the second output end of the first common source amplifying network are respectively connected with the first input end and the second input end of the output matching circuit network, and the first output end and the second output end of the second common source amplifying network are respectively connected with the third input end and the fourth input end of the output matching circuit network;

As shown in fig. 1, the first common source amplifying network includes a driving stage amplifying unit P1, a driving stage amplifying unit P3, a driving stage amplifying unit P5, and a first inter-stage matching shunt network; the second common source amplifying network comprises a driving stage amplifying unit P2, a driving stage amplifying unit P4, a driving stage amplifying unit P6 and a second interstage matching shunt network;

As shown in fig. 2, the input matching shunt network in the embodiment of the present invention includes a capacitor C1, a capacitor C2, and a capacitor C3; microstrip line TL1, microstrip line TL2, microstrip line TL3, microstrip line TL4, microstrip line TL5, microstrip line TL6, microstrip line TL7, microstrip line TL8, microstrip line TL9; a resistor R1 and a resistor R2; a transformer T1;

As shown in fig. 2, the adaptive linear bias network in the embodiment of the present invention includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a transistor M23, and a transistor M24; resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20; capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, and capacitor C21;

As shown in fig. 2, the first common source amplifying network in the embodiment of the present invention includes a transistor M1, a transistor M2, and a transistor M3; capacitor C4, capacitor C6, capacitor C8, and capacitor C9; microstrip line TL13, microstrip line TL14, microstrip line TL15, microstrip line TL28; a transformer T2;

As shown in fig. 2, the second common-source amplifying network in the embodiment of the present invention includes a transistor M4, a transistor M5, and a transistor M6; a capacitor C5, a capacitor C10, a capacitor C11; a transformer T3; microstrip line TL10, microstrip line TL11, microstrip line TL12, microstrip line TL29;

As shown in fig. 2, the output matching circuit network in the embodiment of the present invention includes a multiplexing transformer T4; microstrip line TL16, microstrip line TL17, microstrip line TL18, microstrip line TL19, microstrip line TL20, microstrip line TL21, microstrip line TL22, microstrip line TL23, microstrip line TL24, microstrip line TL25, microstrip line TL26, microstrip line TL27, microstrip line TL30, microstrip line TL31, microstrip line TL32, microstrip line TL33; capacitor C12, capacitor C13, capacitor C14, and capacitor C15;

In one embodiment of the present invention, the working principle and process introduction of the multimode high-efficiency power amplifier are provided:

the radio frequency input signal enters an input matching shunt network of the power amplifier through an input end IN, is subjected to impedance matching through the input matching shunt network, is equally power-distributed into two paths of signals, respectively enters a first common source amplifying network and a second common source amplifying network to be subjected to power amplification and re-shunt, and four paths of amplified and shunted signals enter an output matching synthesis network to be subjected to impedance matching, and finally form a radio frequency output signal to reach an output end OUT after equal power synthesis;

The amplifiers of the two paths of common-source amplifying networks adopt a common-source connection mode, the inter-stage matching adopts a T-shaped structure to complete the first impedance matching, a transformer is used for carrying out the second impedance transformation and realizing the equal power distribution of signals, the defects of high insertion loss and narrow bandwidth of the inter-stage matching of the traditional common-source amplifying network are overcome, the common-source amplifying network can realize good power output, and meanwhile, the impedance matching and the power distribution are also considered; and an LC resonant circuit is added to the first-stage output of the amplifying network for suppressing the secondary output resonant frequency, so that the efficiency of the first-stage amplifier is improved.

The T-shaped branch consisting of the microstrip line TL1, the microstrip line TL3 and the microstrip line TL2 in the input matching network can complete first matching of input impedance, the capacitor C1 is a blocking capacitor, the circuit consisting of the transformer and the microstrip lines TL 4-TL 9 is subjected to equal power distribution of signals and then impedance matching, the power distribution and impedance secondary transformation are completed, and meanwhile, the first RC suppression circuit (resistor R1 and capacitor C2) and the second RC suppression circuit (resistor R2 and capacitor C3) realize suppression of potential unstable signals of the transistor.

In the output matching network, a T-shaped structure reactance matching network formed by microstrip lines TL 16-27 completes the first impedance matching of each output path, a multiplexing transformer T4 completes the synthesis of the equal-power signals, and LC resonance circuits (a capacitor C12, a microstrip line TL 32), (a capacitor C13, a microstrip line TL 33), (a capacitor C14, a microstrip line TL 30) and (a capacitor C15 and a microstrip line TL 31) are used for suppressing the secondary output resonance frequency.

The self-adaptive linear bias network consists of two groups of three bias circuit units, and six bias circuits, wherein each group of bias circuit provides bias for the amplifiers of the first and second common source amplifying networks respectively, and each bias unit can select a mutually independent power-on mode, so that the on or off of each amplifier can be controlled independently, and multimode operation of different power level outputs is realized.

The principles and embodiments of the present invention have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.

Claims

1. The multimode high-efficiency power amplifier is characterized by comprising an input matching shunt network, a first common-source amplifying network, a self-adaptive linear bias network, a second common-source amplifying network and an output matching shunt network;

the first output end and the second output end of the self-adaptive linear bias network are respectively connected with the first input end of the first common-source amplifying network and the first input end of the second common-source amplifying network; the third output end and the fourth output end of the self-adaptive linear bias network are respectively connected with the second input end of the first common-source amplifying network and the second input end of the second common-source amplifying network; the fifth output end and the sixth output end of the self-adaptive linear bias network are respectively connected with the third input end of the first common-source amplifying network and the third input end of the second common-source amplifying network;

the output end of the output matching circuit network is used as the output end of the multimode high-efficiency power amplifier;

the input matching shunt network comprises a capacitor C1, a capacitor C2 and a capacitor C3; microstrip line TL1, microstrip line TL2, microstrip line TL3, microstrip line TL4, microstrip line TL5, microstrip line TL6, microstrip line TL7, microstrip line TL8, microstrip line TL9; a resistor R1 and a resistor R2; a transformer T1;

one end of the output side of the transformer T1 is connected with one end of a microstrip line TL9, the other end of the microstrip line TL9 is respectively connected with one ends of a microstrip line TL7 and a suspended microstrip line TL8, the other end of the microstrip line TL7 is respectively connected with one end of a capacitor C2 and one end of a resistor R1, and the other end of the capacitor C2 and the other end of the resistor R1 are mutually connected and serve as a first output end of the input matching shunt network;

The other end of the output side of the transformer T1 is connected with one end of a microstrip line TL4, the other end of the microstrip line TL4 is respectively connected with one ends of a microstrip line TL6 and a suspended microstrip line TL5, the other end of the microstrip line TL6 is respectively connected with one end of a capacitor C3 and one end of a resistor R2, and the other end of the capacitor C3 and the other end of the resistor R2 are mutually connected and serve as a second output end of the input matching shunt network;

the adaptive linear bias network comprises a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a transistor M23 and a transistor M24; resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20; capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, and capacitor C21;

the emitter of the transistor M24 is connected with a grounding resistor R19, the base of the transistor M24 is respectively connected with the collector of the transistor M24 and the emitter of the transistor M22, the collector of the transistor M22 is respectively connected with one end of a resistor R18, the base of the transistor M22, a grounding capacitor C21 and the base of the transistor M23, the other end of the resistor R18 and the collector of the transistor M23 are both connected with a power supply VCC, and the emitter of the transistor M23 is connected with a grounding resistor R20 and serves as a sixth output end of the adaptive linear bias network;

the output matching network comprises a multipath synthetic transformer T4; microstrip line TL16, microstrip line TL17, microstrip line TL 18, microstrip line TL19, microstrip line TL20, microstrip line TL21, microstrip line TL22, microstrip line TL23, microstrip line TL24, microstrip line TL25, microstrip line TL26, microstrip line TL27, microstrip line TL30, microstrip line TL31, microstrip line TL32, microstrip line TL33; capacitor C12, capacitor C13, capacitor C14, and capacitor C15;

2. The multimode high efficiency power amplifier of claim 1, wherein the first common source amplifying network comprises a driver stage amplifying unit P1, a driver stage amplifying unit P3, a driver stage amplifying unit P5, and a first inter-stage matching shunt network; the second common source amplifying network comprises a driving stage amplifying unit P2, a driving stage amplifying unit P4, a driving stage amplifying unit P6 and a second interstage matching shunt network;

3. The multimode high efficiency power amplifier of claim 1, wherein the first common source amplifying network comprises a transistor M1, a transistor M2, a transistor M3; capacitor C4, capacitor C6, capacitor C8, and capacitor C9; microstrip line TL13, microstrip line TL14, microstrip line TL15, microstrip line TL28; a transformer T2;

4. The multimode high efficiency power amplifier of claim 1, wherein the second common source amplifying network comprises a transistor M4, a transistor M5, a transistor M6; a capacitor C5, a capacitor C10, a capacitor C11; a transformer T3; microstrip line TL10, microstrip line TL11, microstrip line TL12, microstrip line TL29;