CN114362699A - Amplifier based on power self-adaptive bias adjustment technology - Google Patents
Amplifier based on power self-adaptive bias adjustment technology Download PDFInfo
- Publication number
- CN114362699A CN114362699A CN202111524249.9A CN202111524249A CN114362699A CN 114362699 A CN114362699 A CN 114362699A CN 202111524249 A CN202111524249 A CN 202111524249A CN 114362699 A CN114362699 A CN 114362699A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- transistor
- network
- adaptive bias
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses an amplifier based on a power self-adaptive bias adjusting technology, which comprises an input ESD protection and DC blocking matching network, a first power self-adaptive bias adjusting amplifying network, a second power self-adaptive bias adjusting amplifying network, a two-way differential mode filter network and an output phase synthesis matching network.
Description
Technical Field
The invention belongs to the technical field of 5G communication and integrated circuits, and particularly relates to a design of an amplifier based on a power self-adaptive bias adjustment technology.
Background
With the development of technologies such as software radio, broadband instruments, 5G communication and the like, the system bandwidth rate index is continuously improved, so that the market puts higher requirements on the linearity index of the broadband amplifier therein. In particular, in order to process a high-rate peak-to-average ratio signal, the amplifier is required to have a good linearity index in a wide dynamic range.
In order to improve the linearization index within the wide dynamic range of the driver amplifier chip, the following technical means can be adopted when the chip is designed, but the following technical means have some defects:
(1) in the power back-off technology, a transistor with high power is selected as a small power transistor, so that the amplifier works in a back-off linear amplification region to obtain a high linearity index, but in order to realize high linearity in a wide dynamic range, for example, the size of the transistor is large, the direct current power consumption of the amplifier is greatly sacrificed, and the efficiency of the amplifier is low.
(2) The envelope tracking technology utilizes a detection circuit, a bias adjusting technology and the like to track the output power of an amplifier and automatically adjusts the bias circuit of the amplifier according to the dynamic range of the output power, so that the defect that a high-power transistor is switched one by one in the power back-off technology is overcome.
(2) The intermodulation component cancellation technology utilizes two paths of amplifiers of a main path and an auxiliary path to respectively work in an AB mode and a C mode, so that the auxiliary path C generates a positive third-order intermodulation component, and counteracts the negative third-order intermodulation component of the AB mode of the main path, thereby improving the IP3 index and the P1dB index of the amplifiers, but the main path amplifier and the auxiliary path amplifier directly synthesize a cancellation mode, and the signal fundamental wave and the harmonic phase are different, so that the optimal cancellation effect cannot be achieved.
Disclosure of Invention
Aiming at the defects in the prior art, the amplifier based on the power self-adaptive bias adjustment technology provided by the invention is based on an active self-bias improved Darlington amplification structure and combines with an intermodulation cancellation technology to realize an amplifier structure with high linearity index, higher high-frequency gain index and lower power consumption in a wide dynamic range.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: an amplifier based on a power self-adaptive bias adjusting technology comprises an input ESD protection and blocking matching network, a first power self-adaptive bias adjusting amplification network, a second power self-adaptive bias adjusting amplification network, an output phase synthesis matching network and a two-way differential mode filter network;
the input end of the input ESD protection and DC blocking matching network is used as the radio frequency input end of the amplifier, the output end of the input SED protection and DC blocking matching network is respectively connected with the input end of the first power self-adaptive bias adjustment amplifying network and the input end of the second power self-adaptive bias adjustment amplifying network, the first output end of the first power self-adaptive bias adjustment amplifying network is connected with the first input end of the output phase synthesis matching network, the first output end of the second power self-adaptive bias adjustment network is connected with the second input end of the output phase synthesis matching network, and the output end of the output phase synthesis matching network is used as the radio frequency output end of the amplifier;
and the second output end of the first power self-adaptive bias adjusting and amplifying network and the second output end of the second power self-adaptive bias adjusting and amplifying network are both connected with a double-path differential mode filter network.
The invention has the beneficial effects that: the active self-bias improved stacked Darlington amplification structure based on the power self-adaptive bias adjustment technology can obtain a higher high-frequency high-gain index, can realize a high linearity index in a wide dynamic range by combining a harmonic parasitic component phase compensation technology, and simultaneously filters redundant differential mode signals of the improved stacked Darlington amplification structure by using a differential mode filter network in the middle of two paths of amplification networks, so that the stability of an amplifier is improved.
Further, the input ESD protection and DC blocking matching network comprises a capacitor C1Inductor L1And a ground capacitor C13；
The capacitor C1Is used as the input end of the input ESD protection and DC blocking matching network and is connected with the grounding inductor L1Connected, the capacitor C1The other end of the capacitor (C) and a grounding capacitor (C)13And the output end of the input ESD protection and DC blocking matching network is connected with the input ESD protection and DC blocking circuit.
The beneficial effects of the above further scheme are: the network has an ESD protection function, protects the input end of a circuit amplifier from the threat of external ESD stress, and can realize a good matching function of an input impedance low frequency band.
Further, the first power adaptive bias adjustment amplifying network comprises a transistor Q1Transistor Q2Transistor Q3Transistor Q4Transistor Q5Triode Q6Diode D1Diode D2Capacitor C3Capacitor C4Capacitor C5Capacitor C6Capacitor C7Resistance R3Resistance R4Resistance R5Resistance R6Resistance R7Resistance R8Resistance R9Resistance R10Inductor L3Inductor L4And an inductance L5；
The inductance L3One end of the first power adaptive bias adjusting amplifying network is used as the input end of the first power adaptive bias adjusting amplifying network, and the other end of the first power adaptive bias adjusting amplifying network is respectively connected with a grounding capacitor C3And an inductance L4Is connected to one end of the inductor L4The other end of each of the resistors R and R is connected with3One terminal of (1), a capacitor C4And a transistor Q3The base of the resistor R is connected3The other end of each of the resistors R and R is connected with4And a transistor Q1Is connected with the emitter of the light emitting diode,the resistor R4Another terminal of (1) and a capacitor C4Is connected to the other end of the transistor Q1Base electrodes of the two capacitors are respectively connected with a grounding capacitor C5Diode D2Positive electrode and resistor R6Is connected to one end of the diode D2Cathode and diode D1The anode of the diode D1The negative electrode of (2) is grounded;
the resistor R6And the other end of each of the first and second transistors is connected to a transistor Q1Collector and resistor R5Is connected to one end of the resistor R5The other end of the capacitor is respectively connected with a grounding capacitor C6Resistance R7One terminal of (1), resistance R8One terminal of (1) and an inductance L5Is connected to one end of the resistor R7And the other end of each of the first and second transistors is connected to a transistor Q2Is connected to the base, said transistor Q2Emitter of (2) and transistor Q3The collector of said transistor Q3Respectively with a ground resistance R9And a transistor Q6The base of the resistor R is connected8And the other end of each of the first and second transistors is connected to a transistor Q4Is connected to the base, said transistor Q4Respectively with the transistor Q5Base and capacitor C7Is connected to the capacitor C7The other end of (1) and a ground resistor R10Connection of said inductance L5And the other end of the first power adaptive bias adjusting amplifier network is used as a first output end of the first power adaptive bias adjusting amplifier network and connected with a transistor Q5The collector of said transistor Q5As a second output terminal of said first power adaptive bias adjusting amplifying network, and with a transistor Q6The collector of said transistor Q6The emitter of (2) is grounded.
The beneficial effects of the above further scheme are: the first power self-adaptive bias adjusting amplification network is based on an active self-bias improved stacked Darlington amplification structure of a power self-adaptive bias adjusting technology, the high-frequency gain characteristic of an amplifier can be obviously improved, the isolation index is improved, meanwhile, the bias state under a wide dynamic range can be improved by adopting the power self-adaptive bias structure based on transistors Q2 and Q4, the linearity index is improved, the working conduction angle of the amplifier is selected to be 190-210 degrees, the optimal power output capability is obtained, and three-order negative high-frequency parasitic components are generated.
Further, the second power adaptive bias adjustment network comprises a triode Q7Triode Q8Triode Q9Triode Q10Triode Q11Triode Q12Diode D3Diode D4Capacitor C8Capacitor C9Capacitor C10Capacitor C11Capacitor C12Resistance R11Resistance R12Resistance R13Resistance R14Resistance R15Resistance R16Resistance R17Resistance R18Inductor L6Inductor L7And an inductance L8；
The inductance L7One end of the second power adaptive bias adjusting network is used as the input end of the second power adaptive bias adjusting network, and the other end of the second power adaptive bias adjusting network is respectively connected with a grounding capacitor C11And an inductance L8Is connected to one end of the inductor L8And the other ends of the resistors R1 respectively6One terminal of (1), a capacitor C8And a transistor Q8The base of the resistor R is connected16The other end of each of the resistors R and R is connected with15And a transistor Q7The resistor R of15Another terminal of (1) and a capacitor C8Is connected to the other end of the transistor Q7Base electrodes of the two capacitors are respectively connected with a grounding capacitor C9Diode D4Positive electrode and resistor R17Is connected to one terminal of the transistor D4Cathode and diode D3The anode of the diode D3The negative electrode of (2) is grounded;
the resistor R17And the other end of each of the first and second transistors is connected to a transistor Q7Collector and resistor R18Is connected to one end of the transistor R18The other end of the capacitor is respectively connected with a grounding capacitor C10Resistance R12One terminal of (1), resistance R11One terminal of (1) and an inductance L6Is connected to one end of the resistor R12And the other end of each of the first and second transistors is connected to a transistor Q9Is connected to the base, said transistor Q9Emitter of (2) and transistor Q8The collector of said transistor Q8Respectively with a ground resistance R14And a transistor Q12The base of the resistor R is connected11And the other end of each of the first and second transistors is connected to a transistor Q10Is connected to the base, said transistor Q10Respectively with the transistor Q11Base and capacitor C12Is connected to the capacitor C12The other end of (1) and a ground resistor R13Connection of said inductance L6And the other end of the first power adaptive bias adjusting amplifier network is used as a first output end of a second power adaptive bias adjusting amplifier network and connected with a transistor Q11The collector of said transistor Q11As a second output terminal of said second power adaptive bias adjusting amplifying network, and with a transistor Q12The collector of said transistor Q12The emitter of (2) is grounded.
The beneficial effects of the above further scheme are: the second power self-adaptive bias adjusting amplification network is based on an active self-bias improved stacking Darlington amplification structure of a power self-adaptive bias adjusting technology, the high-frequency gain characteristic of the amplifier can be obviously improved, the isolation index is improved, meanwhile, the bias state under a wide dynamic range can be improved by adopting the power self-adaptive bias structure based on transistors Q9 and Q10, the linearity index is improved, the working conduction angle of the amplifier is selected to be 160-180 degrees, good compromise between output power and low power consumption is obtained, and three-order forward high-frequency parasitic components are obtained.
Further, the output phase synthesis matching network comprises a transformer T1Capacitor C14Capacitor C15Capacitor C16And a capacitor C17；
The transformer T1The homonymous terminal of the primary coil is used as the first input terminal of the output phase synthesis matching network, and the transformer T1The non-homonymous terminals of the primary coil are respectively connected with a grounding capacitor C14And a power supply VC1Connected to a primary winding T of said transformer1First homonymous terminal of secondary coil and capacitor C16Is connected to the capacitor C16And the other end of the transformer T is used as the output end of the output phase synthesis matching network1The non-homonymous terminals of the secondary coil are respectively connected with a grounding capacitor C15And a power supply VC2A second homonymous terminal of the secondary coil of the transformer T1 and a grounding capacitor C connected to serve as a second input terminal of the output phase synthesis matching network17And (4) connecting.
The beneficial effects of the above further scheme are: the first power self-adaptive bias adjusting and amplifying network generates a third-order negative high-frequency parasitic component, the first power self-adaptive bias adjusting and amplifying network obtains the third-order positive high-frequency parasitic component, and the harmonic parasitic component phase compensation is realized through the output phase synthesis matching network, so that the linearity index of the amplifier is improved, and meanwhile, the bias network of the amplifier is simplified by adopting the transformer T1.
Further, the two-way differential mode filter network comprises an inductor L2Capacitor C2Resistance R1And a resistance R2；
The inductance L2One end of each of which is connected to a capacitor C2And a resistor R1Is connected to one end of the resistor R1The other end of the first power self-adaptive bias adjusting amplifying network is connected with a second output end of the first power self-adaptive bias adjusting amplifying network, and the inductor L2The other end of each of the first and second capacitors is connected to a capacitor C2Another terminal of (1) and a resistor R2Is connected to one end of the resistor R2And the other end of the second power adaptive bias adjusting amplifier network is connected with a second output end of the second power adaptive bias adjusting amplifier network.
The beneficial effects of the above further scheme are: and the differential mode filter network between the two amplifying networks filters redundant differential mode signals of the improved stacked Darlington amplifying structure, and improves the stability of the amplifier.
Drawings
Fig. 1 is a schematic block diagram of an amplifier based on a power adaptive bias adjustment technique according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of an amplifier based on a power adaptive bias adjustment technique according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
The embodiment of the invention provides an amplifier based on a power self-adaptive bias adjusting technology, which comprises an input ESD protection and blocking matching network, a first power self-adaptive bias adjusting amplification network, a second power self-adaptive bias adjusting amplification network, an output phase synthesis matching network and a two-way differential mode filter network, wherein the input ESD protection and blocking matching network is connected with the first power self-adaptive bias adjusting amplification network;
the input end of the ESD protection and blocking matching network is used as the radio frequency input end of the amplifier, the output end of the input SED protection and blocking matching network is respectively connected with the input end of the first power self-adaptive bias adjusting amplifying network and the input end of the second power self-adaptive bias adjusting amplifying network, the first output end of the first power self-adaptive bias adjusting amplifying network is connected with the first input end of the output phase synthesis matching network, the first output end of the second power self-adaptive bias adjusting network is connected with the second input end of the output phase synthesis matching network, and the output end of the output phase synthesis matching network is used as the radio frequency output end of the amplifier;
and the second output end of the first power self-adaptive bias adjusting and amplifying network and the second output end of the second power self-adaptive bias adjusting and amplifying network are both connected with a double-path differential mode filter network.
As shown in fig. 2, the first power adaptive bias adjustment amplifying network includes a transistor Q1Transistor Q2Transistor Q3Transistor Q4Transistor Q5Triode Q6Diode D1Diode D2Capacitor C3Capacitor C4Capacitor C5Capacitor C6Capacitor C7Resistance R3Resistance R4Resistance R5Resistance R6Resistance R7Resistance R8Resistance R9Resistance R10Inductor L3Inductor L4And an inductance L5；
Inductor L3One end of the first power self-adaptive bias adjusting amplifying network is used as an input end of the first power self-adaptive bias adjusting amplifying network, and the other end of the first power self-adaptive bias adjusting amplifying network is respectively connected with a grounding capacitor C3And an inductance L4Is connected to an inductor L4The other end of each of the resistors R and R is connected with3One terminal of (1), a capacitor C4And a transistor Q3Base connection of (3), resistor R3The other end of each of the resistors R and R is connected with4And a transistor Q1Emitter connection of, resistor R4Another terminal of (1) and a capacitor C4Is connected to the other end of the transistor Q1Base electrodes of the two capacitors are respectively connected with a grounding capacitor C5Diode D2Positive electrode and resistor R6Is connected to one end of a diode D2Cathode and diode D1Is connected to the anode of diode D1The negative electrode of (2) is grounded;
resistance R6And the other end of each of the first and second transistors is connected to a transistor Q1Collector and resistor R5Is connected to a resistor R5The other end of the capacitor is respectively connected with a grounding capacitor C6Resistance R7One terminal of (1), resistance R8One terminal of (1) and an inductance L5Is connected to a resistor R7And the other end of each of the first and second transistors is connected to a transistor Q2Is connected to the base, transistor Q2Emitter of (2) and transistor Q3Is connected to the collector of transistor Q3Respectively with a ground resistance R9And a transistor Q6Base connection of (3), resistor R8And the other end of each of the first and second transistors is connected to a transistor Q4Is connected to the base, transistor Q4Respectively with the transistor Q5Base and capacitor C7Is connected to a capacitor C7The other end of (1) and a ground resistor R10Connection, inductance L5The other end of the first power line is used as the first power lineA first output terminal of the adaptive bias adjusting amplifier network, and a transistor Q5Is connected to the collector of transistor Q5As a second output terminal of the first power adaptive bias adjusting amplifying network and connected with the transistor Q6Is connected to the collector of transistor Q6The emitter of (2) is grounded.
As shown in FIG. 2, the second power adaptive bias adjustment network includes a transistor Q7Triode Q8Triode Q9Triode Q10Triode Q11Triode Q12Diode D3Diode D4Capacitor C8Capacitor C9Capacitor C10Capacitor C11Capacitor C12Resistance R11Resistance R12Resistance R13Resistance R14Resistance R15Resistance R16Resistance R17Resistance R18Inductor L6Inductor L7And an inductance L8；
Inductor L7One end of the first power adaptive bias adjusting network is used as the input end of the second power adaptive bias adjusting network, and the other end of the first power adaptive bias adjusting network is respectively connected with the grounding capacitor C11And an inductance L8Is connected to an inductor L8And the other ends of the resistors R1 respectively6One terminal of (1), a capacitor C8And a transistor Q8Base connection of (3), resistor R16The other end of each of the resistors R and R is connected with15And a transistor Q7Emitter connection of, resistor R15Another terminal of (1) and a capacitor C8Is connected to the other end of the transistor Q7Base electrodes of the two capacitors are respectively connected with a grounding capacitor C9Diode D4Positive electrode and resistor R17Is connected to one terminal of a transistor D4Cathode and diode D3Is connected to the anode of diode D3The negative electrode of (2) is grounded;
resistance R17And the other end of each of the first and second transistors is connected to a transistor Q7Collector and resistor R18Is connected to one terminal of a transistor R18The other end of the capacitor is respectively connected with a grounding capacitor C10Resistance R12One terminal of (1), resistance R11And at one end ofInductor L6Is connected to a resistor R12And the other end of each of the first and second transistors is connected to a transistor Q9Is connected to the base, transistor Q9Emitter of (2) and transistor Q8Is connected to the collector of transistor Q8Respectively with a ground resistance R14And a transistor Q12Base connection of (3), resistor R11And the other end of each of the first and second transistors is connected to a transistor Q10Is connected to the base, transistor Q10Respectively with the transistor Q11Base and capacitor C12Is connected to a capacitor C12The other end of (1) and a ground resistor R13Connection, inductance L6And the other end of the first power adaptive bias adjusting amplifier network is used as a first output end of a second power adaptive bias adjusting amplifier network and connected with a transistor Q11Is connected to the collector of transistor Q11As a second output terminal of the second power adaptive bias adjusting amplifying network, and connected with the transistor Q12Is connected to the collector of transistor Q12The emitter of (2) is grounded.
As shown in FIG. 2, the output phase synthesis matching network includes a transformer T1Capacitor C14Capacitor C15Capacitor C16And a capacitor C17；
Transformer T1The homonymous terminal of the primary coil is used as the first input terminal of the output phase synthesis matching network, and the transformer T1The non-homonymous terminals of the primary coil are respectively connected with a grounding capacitor C14And a power supply VC1Connecting the primary winding T of the transformer1First homonymous terminal of secondary coil and capacitor C16Is connected to a capacitor C16The other end of the transformer T is used as the output end of the output phase synthesis matching network1The non-homonymous terminals of the secondary coil are respectively connected with a grounding capacitor C15And a power supply VC2Connected to the second input terminal of the output phase synthesis matching network, the second dotted terminal of the secondary winding of transformer T1 and the grounding capacitor C17And (4) connecting.
As shown in fig. 2, the two-way differential-mode filter network includes an inductor L2Capacitor C2Resistance R1And a resistance R2；
Inductor L2One end of each of which is connected to a capacitor C2And a resistor R1Is connected to a resistor R1The other end of the first power self-adaptive bias adjusting amplifying network is connected with a second output end of the first power self-adaptive bias adjusting amplifying network, and an inductor L2The other end of each of the first and second capacitors is connected to a capacitor C2Another terminal of (1) and a resistor R2Is connected to a resistor R2And the other end of the second power adaptive bias adjusting amplifier network is connected with a second output end of the second power adaptive bias adjusting amplifier network.
The specific working principle and process of the present invention are described below with reference to fig. 2:
the radio frequency signal enters an input ESD protection and DC blocking matching network, after input impedance matching, the radio frequency signal simultaneously enters a first power self-adaptive bias adjusting amplification network and a second power self-adaptive bias adjusting amplification network for signal amplification in an equal power or unequal power distribution mode, then simultaneously enters an output phase synthesis matching network for power and phase synthesis in a power synthesis mode, and then enters an output port of an amplifier. The working conduction angle of an amplifier of the first power self-adaptive bias adjusting amplification network is selected to be 190-210 degrees, so that the optimal power output capability is obtained, and three-order negative high-frequency parasitic components are generated; the working conduction angle of an amplifier of the second power self-adaptive bias adjusting amplification network is selected to be 160-180 degrees, so that good compromise between output power and low power consumption is obtained, and three-order forward high-frequency parasitic components are obtained; through the output phase synthesis matching network, the third-order negative high-frequency parasitic component generated by the first power self-adaptive bias adjusting and amplifying network and the third-order positive high-frequency parasitic component generated by the second power self-adaptive bias adjusting and amplifying network are subjected to harmonic parasitic component phase compensation, so that the linearity index is improved.
Claims (6)
1. An amplifier based on a power self-adaptive bias adjusting technology is characterized by comprising an input ESD protection and blocking matching network, a first power self-adaptive bias adjusting amplifying network, a second power self-adaptive bias adjusting amplifying network, an output phase synthesis matching network and a two-way differential mode filter network;
the input end of the input ESD protection and DC blocking matching network is used as the radio frequency input end of the amplifier, the output end of the input SED protection and DC blocking matching network is respectively connected with the input end of the first power self-adaptive bias adjustment amplifying network and the input end of the second power self-adaptive bias adjustment amplifying network, the first output end of the first power self-adaptive bias adjustment amplifying network is connected with the first input end of the output phase synthesis matching network, the first output end of the second power self-adaptive bias adjustment network is connected with the second input end of the output phase synthesis matching network, and the output end of the output phase synthesis matching network is used as the radio frequency output end of the amplifier;
and the second output end of the first power self-adaptive bias adjusting and amplifying network and the second output end of the second power self-adaptive bias adjusting and amplifying network are both connected with a double-path differential mode filter network.
2. The power adaptive bias adjustment technology-based amplifier according to claim 1, wherein the input ESD protection and dc blocking matching network comprises a capacitor C1Inductor L1And a ground capacitor C13；
The capacitor C1Is used as the input end of the input ESD protection and DC blocking matching network and is connected with the grounding inductor L1Connected, the capacitor C1The other end of the capacitor (C) and a grounding capacitor (C)13And the output end of the input ESD protection and DC blocking matching network is connected with the input ESD protection and DC blocking circuit.
3. The power adaptive bias adjustment technique based amplifier according to claim 1, wherein the first power adaptive bias adjustment amplification network comprises a transistor Q1Transistor Q2Transistor Q3Transistor Q4Transistor Q5Triode Q6Diode D1Diode D2Capacitor C3Capacitor C4Capacitor C5Capacitor C6Capacitor C7Resistance R3Resistance R4Resistance R5Resistance R6Resistance R7Resistance R8Resistance R9Resistance R10Inductor L3Inductor L4And an inductance L5；
The inductance L3One end of the first power adaptive bias adjusting amplifying network is used as the input end of the first power adaptive bias adjusting amplifying network, and the other end of the first power adaptive bias adjusting amplifying network is respectively connected with a grounding capacitor C3And an inductance L4Is connected to one end of the inductor L4The other end of each of the resistors R and R is connected with3One terminal of (1), a capacitor C4And a transistor Q3The base of the resistor R is connected3The other end of each of the resistors R and R is connected with4And a transistor Q1The resistor R of4Another terminal of (1) and a capacitor C4Is connected to the other end of the transistor Q1Base electrodes of the two capacitors are respectively connected with a grounding capacitor C5Diode D2Positive electrode and resistor R6Is connected to one end of the diode D2Cathode and diode D1The anode of the diode D1The negative electrode of (2) is grounded;
the resistor R6And the other end of each of the first and second transistors is connected to a transistor Q1Collector and resistor R5Is connected to one end of the resistor R5The other end of the capacitor is respectively connected with a grounding capacitor C6Resistance R7One terminal of (1), resistance R8One terminal of (1) and an inductance L5Is connected to one end of the resistor R7And the other end of each of the first and second transistors is connected to a transistor Q2Is connected to the base, said transistor Q2Emitter of (2) and transistor Q3The collector of said transistor Q3Respectively with a ground resistance R9And a transistor Q6The base of the resistor R is connected8And the other end of each of the first and second transistors is connected to a transistor Q4Is connected to the base, said transistor Q4Respectively with the transistor Q5Base and capacitor C7Is connected to the capacitor C7The other end of (1) and a ground resistor R10Connection of said inductance L5The other end of (a)A first output terminal of the first power adaptive bias adjusting amplifying network and a transistor Q5The collector of said transistor Q5As a second output terminal of said first power adaptive bias adjusting amplifying network, and with a transistor Q6The collector of said transistor Q6The emitter of (2) is grounded.
4. The power adaptive bias adjustment technique based amplifier of claim 1, wherein the second power adaptive bias adjustment network comprises a triode Q7Triode Q8Triode Q9Triode Q10Triode Q11Triode Q12Diode D3Diode D4Capacitor C8Capacitor C9Capacitor C10Capacitor C11Capacitor C12Resistance R11Resistance R12Resistance R13Resistance R14Resistance R15Resistance R16Resistance R17Resistance R18Inductor L6Inductor L7And an inductance L8；
The inductance L7One end of the second power adaptive bias adjusting network is used as the input end of the second power adaptive bias adjusting network, and the other end of the second power adaptive bias adjusting network is respectively connected with a grounding capacitor C11And an inductance L8Is connected to one end of the inductor L8And the other ends of the resistors R1 respectively6One terminal of (1), a capacitor C8And a transistor Q8The base of the resistor R is connected16The other end of each of the resistors R and R is connected with15And a transistor Q7The resistor R of15Another terminal of (1) and a capacitor C8Is connected to the other end of the transistor Q7Base electrodes of the two capacitors are respectively connected with a grounding capacitor C9Diode D4Positive electrode and resistor R17Is connected to one terminal of the transistor D4Cathode and diode D3The anode of the diode D3The negative electrode of (2) is grounded;
the resistor R17And the other end of each of the first and second transistors is connected to a transistor Q7Collector and resistor R18Is connected to one end of the transistor R18The other end of the capacitor is respectively connected with a grounding capacitor C10Resistance R12One terminal of (1), resistance R11One terminal of (1) and an inductance L6Is connected to one end of the resistor R12And the other end of each of the first and second transistors is connected to a transistor Q9Is connected to the base, said transistor Q9Emitter of (2) and transistor Q8The collector of said transistor Q8Respectively with a ground resistance R14And a transistor Q12The base of the resistor R is connected11And the other end of each of the first and second transistors is connected to a transistor Q10Is connected to the base, said transistor Q10Respectively with the transistor Q11Base and capacitor C12Is connected to the capacitor C12The other end of (1) and a ground resistor R13Connection of said inductance L6And the other end of the first power adaptive bias adjusting amplifier network is used as a first output end of a second power adaptive bias adjusting amplifier network and connected with a transistor Q11The collector of said transistor Q11As a second output terminal of said second power adaptive bias adjusting amplifying network, and with a transistor Q12The collector of said transistor Q12The emitter of (2) is grounded.
5. The power adaptive bias adjustment technology-based amplifier according to claim 1, wherein the output phase synthesis matching network comprises a transformer T1Capacitor C14Capacitor C15Capacitor C16And a capacitor C17；
The transformer T1The homonymous terminal of the primary coil is used as the first input terminal of the output phase synthesis matching network, and the transformer T1The non-homonymous terminals of the primary coil are respectively connected with a grounding capacitor C14And a power supply VC1Connected to a primary winding T of said transformer1First homonymous terminal of secondary coil and capacitor C16Is connected to the capacitor C16The other end of (2) being said output phaseThe output end of the bit synthesis matching network, the transformer T1The non-homonymous terminals of the secondary coil are respectively connected with a grounding capacitor C15And a power supply VC2A second homonymous terminal of the secondary coil of the transformer T1 and a grounding capacitor C connected to serve as a second input terminal of the output phase synthesis matching network17And (4) connecting.
6. The power adaptive bias adjustment technology-based amplifier according to claim 1, wherein the two-way differential-mode filter network comprises an inductor L2Capacitor C2Resistance R1And a resistance R2；
The inductance L2One end of each of which is connected to a capacitor C2And a resistor R1Is connected to one end of the resistor R1The other end of the first power self-adaptive bias adjusting amplifying network is connected with a second output end of the first power self-adaptive bias adjusting amplifying network, and the inductor L2The other end of each of the first and second capacitors is connected to a capacitor C2Another terminal of (1) and a resistor R2Is connected to one end of the resistor R2And the other end of the second power adaptive bias adjusting amplifier network is connected with a second output end of the second power adaptive bias adjusting amplifier network.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111524249.9A CN114362699A (en) | 2021-12-14 | 2021-12-14 | Amplifier based on power self-adaptive bias adjustment technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111524249.9A CN114362699A (en) | 2021-12-14 | 2021-12-14 | Amplifier based on power self-adaptive bias adjustment technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114362699A true CN114362699A (en) | 2022-04-15 |
Family
ID=81100291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111524249.9A Pending CN114362699A (en) | 2021-12-14 | 2021-12-14 | Amplifier based on power self-adaptive bias adjustment technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114362699A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114679140A (en) * | 2022-04-19 | 2022-06-28 | 江苏卓胜微电子股份有限公司 | High-linearity radio frequency power amplifier |
| CN117559925A (en) * | 2024-01-12 | 2024-02-13 | 电子科技大学 | Multimode high-efficiency power amplifier |
-
2021
- 2021-12-14 CN CN202111524249.9A patent/CN114362699A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114679140A (en) * | 2022-04-19 | 2022-06-28 | 江苏卓胜微电子股份有限公司 | High-linearity radio frequency power amplifier |
| CN117559925A (en) * | 2024-01-12 | 2024-02-13 | 电子科技大学 | Multimode high-efficiency power amplifier |
| CN117559925B (en) * | 2024-01-12 | 2024-03-29 | 电子科技大学 | Multimode high-efficiency power amplifier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109951159B (en) | Doherty power amplifier based on transformer | |
| CN114362699A (en) | Amplifier based on power self-adaptive bias adjustment technology | |
| CN110677132B (en) | Radio frequency linear power amplifier circuit | |
| WO2023087627A1 (en) | Broadband doherty power amplifier | |
| WO2023082933A1 (en) | Radio frequency power amplifier | |
| CN108574464B (en) | Low-power-consumption high-linearity dual-mode millimeter wave broadband stacked low-noise amplifier | |
| CN207869070U (en) | Active biased darlington structure amplifier | |
| WO2023045542A1 (en) | Radio-frequency power amplifier and radio-frequency front-end architecture applied to 5g communication system | |
| CN216162678U (en) | Radio frequency power amplifier | |
| US11848650B2 (en) | Differential power amplifier | |
| CN114679140B (en) | High linearity radio frequency power amplifier | |
| CN101888214A (en) | Cascode power amplifier with improved efficiency and linearity | |
| CN112865717B (en) | High-gain power amplifier based on self-adaptive linearization technology | |
| CN1233090C (en) | Programmable radio frequency predistortion linearizer and method thereof | |
| WO2024067226A1 (en) | Balanced radio frequency power amplifier, radio frequency front-end module, and electronic device | |
| KR101590605B1 (en) | Linear power amplifier for wireless transmitter | |
| CN114362686A (en) | Amplifier based on intermodulation cancellation technology | |
| CN116232246A (en) | Radio frequency power amplifier | |
| CN114362685B (en) | Power amplifier based on high Q value differential coupling technology | |
| CN114362687A (en) | High-linearity power amplifier based on dynamic feedback | |
| CN115412036A (en) | High linearity broadband power amplifier for short-range wireless communication | |
| CN114640316A (en) | Configurable radio frequency power amplifier circuit | |
| WO2021227328A1 (en) | Impedance regulating circuit and method, and bias circuit structure and amplifier | |
| CN108768323B (en) | High-power high-efficiency high-gain reverse F-class stacked power amplifier | |
| Anderson et al. | An asymmetrical parallel-combined cascode CMOS WiFi 5GHz 802.11 ac RF power amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |