CN1175580C - Decoding method and decoder realizing same - Google Patents
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Abstract
The present invention provides a self-adaptation iterative decoding scheme and a decoder for realizing the scheme. The self-adaptation iterative decoding scheme does not need additionally adding a bit and can effectively reduce the average decoding iterative frequencies of parallel link convolution codes and serial link convolution codes. An iterative terminating detector is added in the existing decoder. Under the preconditions of ensuring favorable error rate, hardly increasing decoding complicated degree and without using additional bits, the present invention can reduce the average decoding iterative frequencies of the parallel link convolution codes and the serial link convolution codes, and therefore, the average decoding time delay of the parallel link convolution codes and the serial link convolution codes is reduced.
Description
What the present invention relates to is the error correction/encoding method of transmission information in bad channel, especially relates to interpretation method and code translator thereof in parallel link convolution code and the serial link convolution coding technology.
C.Berrou, A.Glavieux, P.Thitimajshama delivered parallel link convolutional encoding first (Parallel Concatenated Convolutional Codes:PCCC) technology in 1993 at Proceedings of theIEEE International Conference on Communications (ICC ' 93) (1064-1074 page or leaf), had another name called: Turbo code.The parallel link convolutional encoding is described as " near the error correction coding and the decoding of Shannon limit ".Since then, parallel link convolutional encoding is the focus that people study always.
The decoded mode of parallel link convolutional encoding is the iterative decoding of soft input/soft output.Decoder reaches the purpose that reduces error rate by iteration repeatedly, repeatedly exports decode results after the iteration.C.Berrou, A.Glavieux, P.Thitimajshama used maximum iteration time in " near the error correction coding and the decoding of Shannon limit: Turbo code " (ICC ' 93) literary composition is 18 times.What big iterations brought is big decoding delay, and big decoding delay can not satisfy the requirement of real time communication.
In the past few years scientific circles have proposed multiple adaptive iteration decoding algorithm, promptly reduce the method for the average decoding iterations of parallel link convolution code under the prerequisite that not too influences final error rate.J.Hagenauer, the paper " iterative decoding of binary block convolution code " that E.Offer and L.Papke deliver in IEEE Trans.Inform Theory (IT-42,429-445 page or leaf 1996) proposes to reduce by the method for the cross-entropy that calculates the soft output of decoder the average decoding iterations of parallel link convolutional encoding.B.Kim and H.S.Lee propose to reduce by the method for the variance of calculating the soft output of decoder the average decoding iterations of parallel link convolutional encoding in the paper that Proceedings of the IEEE Region 10 Conference (TENCON ' 99,494 are to 497 page of the 1st volume) deliver " reduces the iterations of Turbo code decoder " with external information.But these two kinds of methods are all not so good aspect error rate and average iterations.Effective method is, C.W.Yue, K.B.Letaief, R.S.Cheng, R.D.Murch proposes to add the average decoding iterations that CRC (CRC) bit reduces the parallel link convolution code in frame data in the paper " about the FER performance and the decoding complexity of Turbo code " that IEEE Vehicular Technology Conference (VTC ' 99,2214 are to 2218 pages) delivers.This method can reduce the average decoding iterations of parallel link convolution code effectively, but the CRC that adds (CRC) bit makes the utilance of resource descend again.
Serial link convolutional encoding (Serial Concatenated Convolutional Codes:SCCC) also adopts iterative decoding in addition, also has the problems referred to above.
The purpose of this invention is to provide a kind of decoder that need not the adaptive iteration interpretation method of the average decoding iterations that adds bit and can reduce parallel link convolution code and serial link convolution code effectively and realize this scheme.
Interpretation method of the present invention is made of the following step:
1. will decipher iteration count I and be initialized as 1;
2. the input data are deciphered;
3. as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0.If be 1, finish iterative decoding to these frame data; Otherwise I add 1 and return the 2nd the step;
5. work as I=I
MaxThe time, finish iterative decoding to these frame data;
Wherein use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
Decoder of the present invention stops detector for add an iteration in existing decoder.
The present invention is helpful to the practice of parallel link convolution code and serial link convolution code.Guaranteeing good error probability (bit error rate (BER) BER and FER (Floating Error Rate) FER) and increasing decoding complexity hardly and do not use under the prerequisite of the bit that adds, the present invention can reduce the average decoding iterations of parallel link convolution code and serial link convolution code, thereby has reduced the average decoding delay of parallel link convolution code and serial link convolution code.
The present invention is applicable to the parallel link convolution code and the serial link convolution code of recursive systematic convolutional code and onrecurrent convolution code.The present invention is applicable to the parallel link convolution coder and the serial link convolution code of various code rate, different coding constraint length, different generator polynomial, different interleaving device and different frame length.The present invention only is used in the parallel link convolution code and the serial link convolution code of band tail bit, and is applicable to the various different modes that add tail bit.
The present invention can be used for the generator polynomial situation inequality of each recursive system convolution coder of encoder equally, and just the structure of each iteration termination detector in the decoder should design separately according to corresponding with it recursive system convolution coder generator polynomial.
Below in conjunction with accompanying drawing the present invention is elaborated:
Fig. 1 is conventional parallel link convolution coder structural representation;
Fig. 2 is conventional serial link convolution coder structural representation;
Fig. 3 is the structural representation of an embodiment of termination detector of the present invention;
Fig. 4 is the structural representation of another embodiment of termination detector of the present invention;
The structural representation of one embodiment of Fig. 5 parallel link Convolutional Decoder Assembly of the present invention;
The structural representation of one embodiment of Fig. 6 serial link Convolutional Decoder Assembly of the present invention;
Fig. 7 is a kind of structure diagram of adaptive iteration parallel link Convolutional Decoder Assembly.
Encoder among Fig. 1 can be recursive systematic convolutional code (Recursive SystematicConvolutional codes:RSC) encoder or onrecurrent convolution code (NonrecursiveSystematic Convolutional codes:NSC) encoder.
When designing iteration at the parallel link convolution code of using recursive systematic convolutional code and serial link convolution code and stop detector, the hypothesis encoder all is recursive systematic convolutional code and uses identical generator polynomial that each recursive systematic convolutional code encoder has all used tail bit separately to stop encoder earlier.The generator polynomial of supposing them all is g
f(D)/g
b(D).An iteration stops detector and by a hard decision device, a generator polynomial is
Recursive system convolution coder, Digital Logic NOR gate and a gate-controlled switch constitute.If it is 1 that this iteration stops the detector output logic, assert that then decoding is correct; Otherwise assert that decoding is incorrect.Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input 1 of the output termination adder of hard decision device, the input of the output termination register 1 of adder, the input of the output termination register 2 of register 1, the input of the output termination register 3 of register 2, ..., the input of the output termination register M of register M-1, register 1,2 ... the output of M is according to feedback multinomial g
b(D) feed back to the input of adder 2, the input 2 of the output termination adder of adder 2, adder 1 output and register 1,2 ... the output of M-1 connects M input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector.Its workflow is before frame data input iteration to be stopped all register zero clearings in the detector, with switch opens, import the data of a frame then, when the data (comprising all tail bit) of a frame when being input to the input of register 1, switch closure, the result of output NOR gate computing.
The formation and the principle that stop detector at the iteration of the parallel link convolution code of using the nonrecursive system convolution code and the design of serial link convolution code are as follows: use the parallel link convolution code or the serial link convolution code of nonrecursive system convolution code, all use complete 0 bit as hangover.The constraint length K of supposing nonrecursive system convolution codes all in parallel link convolution code or the serial link convolution code all is M+1, and promptly its register number is M.Iteration termination detector at this parallel link convolution code and the design of serial link convolution code by a hard decision device, a generator polynomial is
Convolution coder, Digital Logic NOR gate and a gate-controlled switch constitute, its operation principle is to judge declaring the result firmly and whether be Binary Zero entirely through tail bit in the decoding soft output in back.If it is 1 that this iteration stops the detector output logic; Otherwise output logic is 0.Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination register 1 of hard decision device, the input of the output termination register 2 of register 1, the input of the output termination register 3 of register 2, ..., the input of the output termination register M of register M-1, the output of hard decision device and register 1,2, ... the output of M-1 connects M input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector.Its workflow is before frame data input iteration to be stopped all register zero clearings in the detector, with switch opens, import the data of a frame then, when the data (comprising all tail bit) of a frame when being input to the input of register 1, switch closure, the result of output NOR gate computing.
Encoder among Fig. 2 can be recursive systematic convolutional code (Recursive SystematicConvolutional codes:RSC) encoder or onrecurrent convolution code (NonrecursiveSystematic Convolutional codes:NSC) encoder.
Describe the embodiment of the termination detector arrangement of employed parallel link convolution code (Turbo code) design in the cdma2000 standard that proposes at Qualcomm company among the present invention with reference to Fig. 3, wherein feed back generator polynomial g
b(D)=1+D
2+ D
3Its structure is: the input data connect the input of hard decision device, the input port a of the output termination binary adder 1 of hard decision device, the input port b of the output termination binary adder 1 of binary adder 2, the input of the output termination register 1D of binary adder 1, the input of the output termination register 2D of register 1D, the input of the output termination register 3D of register 2D, the input of binary adder 2 meets register 2D respectively, the output of 3D, three inputs of NOR gate meet register 1D respectively, the output of 2D and adder 1, a controllable switch is received the output of NOR gate, and this controllable switch is output as the output that this iteration stops detector.
Describe another most preferred embodiment of the present invention with reference to Fig. 4: at nonrecursive system convolution code constraint length in the parallel link convolution coder is the termination detector of 4 (being that the register number is 3) design.Its structure is: the input data connect the input of hard decision device, the input of the output termination register 1D of hard decision device, the input of the output termination register 2D of register 1D, three inputs of NOR gate connect the output of register 1D, 2D and hard decision device respectively, a controllable switch is received the output of NOR gate, and this controllable switch is output as the output that this iteration stops detector.
Figure 5 shows that a kind of schematic diagram that uses iteration to stop the parallel link Convolutional Decoder Assembly embodiment of detector.N iteration stops the output conduct of detector and the input of door.This decoder is to design at the parallel link encoder for convolution codes that has N group hangover (tail) bit.This decoder can use any one decoding algorithm, as maximum a posteriori probability MAP, Log-MAP and Max-Log-MAP decoder etc.
New adaptive iteration decoding scheme of the present invention comprises the steps:
1. will decipher iteration count I and be initialized as 1;
2. will carry out demodulation multiplexer from the data that channel receives and conciliate canceller, and the data of corresponding first group of convolution code check bit in the dateout and systematic code data will be input to decoder 1 decipher.The output of decoder 1 is input to interleaver 1 and iteration stops detector 1.The data that the output of interleaver 1 and demultiplexing are separated the second group system convolution code check bit of canceller output are input to decoder 2, by this process data remaining decoder of process and interleaver, the output of last decoder N is input to iteration and stops detector N and deinterleaver 1,2, the output of deinterleaver 1 is as the input of next iteration decoder 1, and the output that all iteration stop detector is input to and door;
3. as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0.If be 1, finish iterative decoding to these frame data, the output of deinterleaver 2 is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5. work as I=I
Max, finish iterative decoding to these frame data, the output of deinterleaver 2 is input to the hard decision device, the hard decision device is output as the output of final decoding.
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
Figure 6 shows that a kind of schematic diagram that uses iteration to stop the serial link Convolutional Decoder Assembly embodiment of detector.2 iteration stop the output conduct of detector and the input of door.This decoder is to design at the serial link encoder for convolution codes that has 2 groups of hangovers (tail) bit.This decoder can use any one decoding algorithm, as maximum a posteriori probability MAP, Log-MAP and Max-Log-MAP decoder etc.
New adaptive iteration decoding scheme of the present invention comprises the steps:
1. will decipher iteration count I and be initialized as 1;
2. the data that will receive from channel are conciliate canceller 1 to demultiplexing and be carried out demultiplexing and conciliate deletion, the data of corresponding convolution code check bit in the dateout and systematic code data are input to decoder 1 decipher.The output of decoder 1 is input to deinterleaver 1 and iteration stops detector 1.The output of deinterleaver 1 is input to demultiplexing and separates canceller 2, its output is input to decoder 2, the output of decoder 2 is input to iteration and stops detector 2 and interleaver 1, and the output of interleaver 1 is as the input of next iteration decoder 1, and the output that all iteration stop detector is input to and door;
3. as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0.If be 1, finish iterative decoding to these frame data, the output of decoder 2 is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5. work as I=I
Max, finish iterative decoding to these frame data, the output of decoder 2 is input to the hard decision device, the hard decision device is output as the output of final decoding.
In the above-mentioned steps, use I
MaxWith the maximum decoding iterations that representative allows, use I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
The present invention can combine with other adaptive iteration decoding algorithms (the adaptive iteration decoding algorithm that adds CRC (CRC) bit as use), reaches the purpose that reduces the iterative decoding number of times.
Add CRC (CRC) bit in view of all using in existing most wireless communication systems, the present invention combines and can use the condition that adds CRC (CRC) bit on a small quantity to be issued to extraordinary decoding effect (especially aspect error rate and the decoding delay) with the adaptive iteration decoding algorithm that use adds CRC (CRC) bit.
Fig. 7 is for method of the present invention with add the embodiment of the adaptive iteration parallel link Convolutional Decoder Assembly that cyclic redundancy code (CRC) method is used in combination.Cyclic redundancy code (CRC) checker and iteration termination detector all arrive in the output of N decoder input, if cyclic redundancy code (CRC) checker verification succeeds wherein, output logic 1, otherwise output logic 0.The output of N cyclic redundancy code (CRC) checker and N iteration termination detector all is input to and door.If be output as logical one, finish whole iterative decoding process with door.
End interpretation method of the present invention can also comprise the steps:
1. will decipher iteration count I and be initialized as 1;
2. the input data are deciphered;
3. as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0.If be 1, finish iterative decoding to these frame data, the output of deinterleaver 2 is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step.
5. work as I=I
MaxThe time, finish iterative decoding to these frame data, the output of deinterleaver 2 is input to the hard decision device, the hard decision device is output as the output of final decoding.
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
Claims (8)
1. adaptive iteration code translator that is applied to parallel link recursive convolution sign indicating number is characterized by described decoder and comprises that a demodulation multiplexer, one are separated canceller, a N feedback generator polynomial is [g
b(D)] and the register number be that recursive convolution code decoder, the N-1 interleaver of M, 2 deinterleavers, a N iteration stop detector, one and door and a hard decision device; The syndeton of described decoder comprises: the input of demodulation multiplexer is the input of whole decoder, the output termination of demodulation multiplexer is separated the input of canceller, kN output separating canceller connects the input 2 of decoder (1) respectively, ..., k+1, the input 2 of decoder (2), ..., k+1, ... and the input 2 of decoder (N), ..., k+1, the output termination iteration of decoder (1) stops the input of detector (1) and the input of interleaver (1), iteration stops the output termination of detector (1) and the input 1 of door, the input 1 of the output termination decoder (2) of interleaver (1), the output termination iteration of decoder (2) stops the input of detector (2) and the input of interleaver (2), iteration stops the output termination of detector (2) and the input 2 of door, the input 1 of the output termination decoder (3) of interleaver (2), ..., the input 1 of the output termination decoder (i) of interleaver (i-1 (2＜i＜N)), the output termination iteration of decoder (i) stops the input of detector (i) and the input of interleaver (i), iteration stops the output termination of detector (i) and the input i of door, ..., the input 1 of the output termination decoder (N) of interleaver (N-1), the output termination iteration of decoder (N) stops the input of detector (N), the input of the input of deinterleaver (1) and deinterleaver (2), iteration stops the output termination of detector (N) and the input N of door, the input 1 of the output termination decoder (1) of deinterleaver (1), the input of the output termination hard decision device of deinterleaver (2), the output of hard decision device is the output of decoder; Wherein said iteration stops detector and comprises: a hard decision device, a generator polynomial are
Encoder for convolution codes, a NOR gate and a controllable switch; This NOR gate is the NOR gate of M input port; This controllable switch is closure when the whole frame data that comprise tail bit are input to the input of register (1) only, at next frame data input front opening; Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input 1 of the output termination adder of hard decision device, the input of the output termination register (1) of adder, the input of the output termination register (2) of register (1), the input of the output termination register (3) of register (2), ..., the input of the output termination register (M) of register (M-1), register (1), (2), ... output (M) feeds back to the input of adder (2) according to feedback multinomial gb (D), the input 2 of the output termination adder of adder (2), the output of adder (1) and register (1), (2), ... output (M-1) connects M input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector; Iterative decoder has a decoding iteration count to write down the iterations of decoding.
2. adaptive iteration method that is applied to parallel link recursive convolution sign indicating number is characterized by the work of following these steps to:
1). will decipher iteration count I and be initialized as 1;
2). will carry out demultiplexing from the data that channel receives and conciliate deletion, the data of the corresponding first group system convolution code check bit in the dateout and systematic code data are input to decoder (1) to be deciphered, the output of decoder (1) is input to interleaver (1) and iteration stops detector (1), the data that the output of interleaver (1) and demultiplexing are separated the second group system convolution code check bit of canceller output are input to decoder (2), by this process data remaining decoder of process and interleaver, the output of last decoder (N) is input to iteration and stops detector (N) and deinterleaver (1), deinterleaver (2), the output of deinterleaver (1) is as the input of next iteration decoder (1), and the output that all iteration stop detector is input to and door;
3). as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4). work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0; If be 1, finish iterative decoding, and the output of deinterleaver (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
Max, finishing iterative decoding, and the output of deinterleaver (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding;
Wherein, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
3. adaptive iteration code translator that is applied to serial link recursive convolution sign indicating number is characterized by described decoder and comprises that 2 demodulation multiplexers, 2 are separated canceller, 2 feedback generator polynomials are [g
b(D)] and the register number be that the recursive convolution code decoder of M, 1 interleaver, 1 deinterleaver, 2 iteration stop detectors, one and door, a gate-controlled switch and a hard decision device; The syndeton of described decoder comprises: the input of demodulation multiplexer (1) is the input of whole decoder, the output termination of demodulation multiplexer (1) is separated the input of canceller (1), separate the output 1 of canceller (1), ..., k connects the input 2 of decoder (1) respectively, ..., k+1, the output termination iteration of decoder (1) stops the input of detector (1) and the input of deinterleaver, iteration stops the output termination of detector (1) and the input 1 of door, the input of the output termination demodulation multiplexer (2) of deinterleaver, the output termination of demodulation multiplexer (2) is separated the input of canceller (2), separate the output 1 of canceller (2), ..., n connects the input 1 of decoder (2), ..., n, the output termination iteration of decoder (2) stops the input of detector (2), the input of the input of interleaver and hard decision device, iteration stops the output termination of detector (2) and the input 2 of door, the input 1 of the output termination decoder (1) of interleaver, the output of hard decision device is the output of decoder; Wherein said iteration stops detector and comprises: a hard decision device, a generator polynomial are
Encoder for convolution codes, a NOR gate and a controllable switch; This NOR gate is the NOR gate of M input port; This controllable switch is closure when the whole frame data that comprise tail bit are input to the input of register (1) only, at next frame data input front opening; Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input 1 of the output termination adder of hard decision device, the input of the output termination register (1) of adder, the input of the output termination register (2) of register (1), the input of the output termination register (3) of register (2), ..., the input of the output termination register (M) of register (M-1), register (1), (2) ... output (M) is according to feedback multinomial g
b(D) feed back to the input of adder (2), the input 2 of the output termination adder of adder (2), the output of adder (1) and register (1), (2) ... output (M-1) connects M input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector; Iterative decoder has a decoding iteration count to write down the iterations of decoding.
4. adaptive iteration interpretation method that is applied to serial link recursive convolution sign indicating number is characterized by the work of following these steps to:
1). will decipher iteration count I and be initialized as 1;
2). the data that will receive from channel be conciliate canceller (1) to demultiplexing and be carried out demultiplexing and conciliate deletion, the data of corresponding convolution code check bit in the dateout and systematic code data are input to decoder (1) decipher; The output of decoder (1) is input to deinterleaver (1) and iteration stops detector (1); The output of deinterleaver (1) is input to demultiplexing and separates canceller (2), its output is input to decoder (2), the output of decoder (2) is input to iteration and stops detector (2) and interleaver (1), the output of interleaver (1) is as the input of next iteration decoder (1), and the output that all iteration stop detector is input to and door;
3). as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4). work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0; If be 1, finish iterative decoding, and the output of deinterleaver (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
Max, finishing iterative decoding, and the output of deinterleaver (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
5. adaptive iteration code translator that is applied to parallel link onrecurrent convolution code is characterized by described decoder and comprises a demodulation multiplexer, one and separate onrecurrent Convolutional Decoder Assembly that canceller, a N register number are M, a N-1 interleaver, 2 deinterleavers, a N iteration and stop detector, one and door, a gate-controlled switch and a hard decision device; The syndeton of described decoder comprises: the input of demodulation multiplexer is the input of whole decoder, the output termination of demodulation multiplexer is separated the input of canceller, kN output separating canceller connects the input 2 of decoder (1) respectively, ..., k+1, the input 2 of decoder (2), ..., k+1, ... and the input 2 of decoder (N), ..., k+1, the output termination iteration of decoder (1) stops the input of detector (1) and the input of interleaver (1), iteration stops the output termination of detector (1) and the input 1 of door, the input 1 of the output termination decoder (2) of interleaver (1), the output termination iteration of decoder (2) stops the input of detector (2) and the input of interleaver (2), iteration stops the output termination of detector (2) and the input 2 of door, the input 1 of the output termination decoder (3) of interleaver (2), ..., the input 1 of the output termination decoder (i) of interleaver (i-1 (2＜i＜N)), the output termination iteration of decoder (i) stops the input of detector (i) and the input of interleaver (i), iteration stops the output termination of detector (i) and the input i of door, ..., the input 1 of the output termination decoder (N) of interleaver (N-1), the output termination iteration of decoder (N) stops the input of detector (N), the input of the input of deinterleaver (1) and deinterleaver (2), iteration stops the output termination of detector (N) and the input N of door, the input 1 of the output termination decoder (1) of deinterleaver (1), the input of the output termination hard decision device of deinterleaver (2), the output of hard decision device is the output of decoder; Described iteration stops detector and comprises: a hard decision device, a generator polynomial are
Encoder for convolution codes, a NOR gate and a controllable switch; This NOR gate is the NOR gate of M input port; This controllable switch is closure when the whole frame data that comprise tail bit are input to the input of register (1) only, at next frame data input front opening; Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination register (1) of hard decision device, the input of the output termination register (2) of register (1), the input of the output termination register (3) of register (2), ..., the input of the output termination register (M) of register (M-1), the output of hard decision device and register (1), (2), ... output (M-1) connects M input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector; Iterative decoder has a decoding iteration count to write down the iterations of decoding.
6. adaptive iteration interpretation method that is applied to parallel link onrecurrent convolution code is characterized by the work of following these steps to:
1). will decipher iteration count I and be initialized as 1;
2). will carry out demultiplexing from the data that channel receives and conciliate deletion, the data of the corresponding first group system convolution code check bit in the dateout and systematic code data are input to decoder (1) to be deciphered, the output of decoder (1) is input to interleaver (1) and iteration stops detector (1), the data that the output of interleaver (1) and demultiplexing are separated the second group system convolution code check bit of canceller output are input to decoder (2), by this process data remaining decoder of process and interleaver, the output of last decoder (N) is input to iteration and stops detector (N) and deinterleaver (1), deinterleaver (2), the output of deinterleaver (1) is as the input of next iteration decoder (1), and the output that all iteration stop detector is input to and door;
3). as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4). work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0; If be 1, finish iterative decoding, and the output of decoder (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
Max, finishing iterative decoding, and the output of decoder (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding;
Wherein, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, the span of parameter I t is I
Min≤ I
t≤ I
Max-1.
7. adaptive iteration code translator that is applied to serial link onrecurrent convolution code is characterized by described decoder and comprises that 2 demodulation multiplexers, 2 are separated canceller, 2 feedback generator polynomials are [g
b(D)] and the register number be that the onrecurrent Convolutional Decoder Assembly of M, 1 interleaver, 1 deinterleaver, 2 iteration stop detectors, one and door, a gate-controlled switch and a hard decision device; The syndeton of described decoder comprises: the input of demodulation multiplexer (1) is the input of whole decoder, the output termination of demodulation multiplexer (1) is separated the input of canceller (1), k output separating canceller (1) connects the input 2 of decoder (1) respectively, ..., k+1, the output termination iteration of decoder (1) stops the input of detector (1) and the input of deinterleaver, iteration stops the output termination of detector (1) and the input 1 of door, the input of the output termination demodulation multiplexer (2) of deinterleaver, the output termination of demodulation multiplexer (2) is separated the input of canceller (2), separate the input 1 of n the output termination decoder (2) of canceller (2), ..., n, the output termination iteration of decoder (2) stops the input of detector (2), the input of the input of interleaver and hard decision device, iteration stops the output termination of detector (2) and the input 2 of door, the input 1 of the output termination decoder (1) of interleaver, the output of hard decision device is the output of decoder; Described iteration stops detector and comprises: a hard decision device, a generator polynomial are
Encoder for convolution codes, a NOR gate and a controllable switch; This NOR gate is the NOR gate of M input port; This controllable switch is closure when the whole frame data that comprise tail bit are input to the input of register (1) only, at next frame data input front opening; Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination register (1) of hard decision device, the input of the output termination register (2) of register (1), the input of the output termination register (3) of register (2), ..., the input of the output termination register (M) of register (M-1), the output of hard decision device and register (1), (2), ... output (M-1) connects M input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector; Iterative decoder has a decoding iteration count to write down the iterations of decoding.
8. adaptive iteration interpretation method that is applied to serial link onrecurrent convolution code is characterized by the work of following these steps to:
1). will decipher iteration count I and be initialized as 1;
2). the data that will receive from channel be conciliate canceller (1) to demultiplexing and be carried out demultiplexing and conciliate deletion, the data of corresponding convolution code check bit in the dateout and systematic code data are input to decoder (1) decipher; The output of decoder (1) is input to deinterleaver (1) and iteration stops detector (1); The output of deinterleaver (1) is input to demultiplexing and separates canceller (2), its output is input to decoder (2), the output of decoder (2) is input to iteration and stops detector (2) and interleaver (1), the output of interleaver (1) is as the input of next iteration decoder (1), and the output that all iteration stop detector is input to and door;
3). as I＜I
MinOr I
t＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4). work as I
Min≤ I≤I
tThe time, judge with door to be output as 1 or 0; If be 1, finish iterative decoding, and the output of decoder (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
Max, finishing iterative decoding, and the output of decoder (2) is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding;
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows, parameter I
tSpan be I
Min≤ I
t≤ I
Max-1.
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