CN1129257C - Maximum-likelihood decode method f serial backtracking and decoder using said method - Google Patents
Maximum-likelihood decode method f serial backtracking and decoder using said method Download PDFInfo
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Abstract
The present invention discloses a maximum likelihood decoding method for serial backtracking. In the method, the state numbers of nodes on a previous window survival path are compared with the state numbers of nodes on a rear window survival path to judge the connection property of the paths. If the paths are completely connected, parallel path soft backtracking is carried out for the newly-received nodes of a rear window; the soft information of a previous window in a register set is reserved. If the paths are partially connected, soft information corresponding to path connection parts in the register set is reserved; parallel path backtracking is carried out for nodes in non-connection parts. If the paths are not at all connected, the parallel path soft backtracking is carried out for all nodes in the rear window.
Description
The present invention relates to the coding/decoding method of the rich sign indicating number of spy (Turbo) in the wireless mobile communications mobile system, relate in particular to a kind of coding/decoding method of the viterbi algorithm based on soft inputting and soft output, i.e. maximal-probability decode method, and the decoder that uses this coding/decoding method.
In wireless communication system, transmission signals can be subjected to the interference of factors such as time diffusion, decline because of transmission medium is inhomogeneous and unstable, causes the mistake of the bit generation randomness that receives.In order to prevent the interference of interchannel noise, must adopt certain mode to improve the transmission reliability and the validity of information.Facts have proved that the error correction/encoding method that reduces the error rate by the increase redundancy is the effectively means of a class.Especially, in mobile communication and satellite communication system, error correction/encoding method is widely used.
Turbo code is the very strong sign indicating number of a kind of error correcting capability.Its encoder can be made of the cascade system of two or more sub-encoders by serial or parallel connection, more generally makes two encoder for convolution codes parallel connections.
Fig. 1 is a kind of structural representation of Turbo code encoder.It is the Turbo code encoder of advising in cdma 2000 and the WCDMA motion.In the figure, Turbo code encoder 10 comprises two regression system convolution code (RSC) sub-encoders 14 and 16 in parallel up and down.First sub-encoders 14 is directly imported in input information position one tunnel, and second sub-encoders 16 is imported by interleaver 12 in another road.The effect of interleaver is to the rearrangement of input data, adjusts the distribution of weight.Therefore, import weight distribution and first sub-encoders 14 different of the bit stream of second sub-encoders 16.First sub-encoders 14 and second sub-encoders 16 are respectively to the data coding, then with encoded data input card punch 18.The multichannel bits punching sampling of 18 pairs of two sub-encoders 14 of card punch and 16 outputs and and the string conversion, modulate data on suitable code check (such as 1/2,1/3 or 1/4 code check etc.) output.
Fig. 2 illustration sub-encoders 14 and 16 structure among Fig. 1.Encoder for convolution codes uses usually that (n0, k0 m) characterize.Wherein n0 is the output bit of encoder; K0 is the input bit of encoder; And m is the number of shift register in the encoder.Encoder can also be represented its characteristic with constraint length K, and it equals encoder for convolution codes internal displacement the number of registers m and adds 1, is used for determining the scope of zone field bit affects.Shown in Fig. 2 is (3,1, a 3) encoder for convolution codes.Its constraint length is 4, and code check is 1/3.It is the structure in the cdma2000 motion.If adopt the structure in the WCDMA motion, encoder is (2,1,3) so, does not have Y
1Output.
As seen from Figure 2, encoder comprises three shift registers that are connected in series mutually 20.When input was imported one, the content in each shift register was transmitted to the right successively.Encoder also comprises a plurality of modulo 2 adders 22, and they make addition process according to certain coding rule to the output signal of input signal and shift registers at different levels.In the figure, corresponding to the input of the information of a bit, encoder will be exported three bits, i.e. X, Y
0And Y
1X is the information bit identical with input information, Y
0And Y
1Be two check bits.When error code takes place because of channel disturbance in X, Y
0And Y
1Can be used to error correction.In addition, encoder also comprises a tail bit controller 24.When frame data input finishes, need be to shift register 20 zero clearings.At this moment, the switch of tail bit controller 24 can be switched to the below, by three beats, with the bit in three shift registers 20 as importing zero clearing successively.
The recursive iteration mode is adopted in the decoding of Turbo code.According to different decoding algorithms, mainly be divided into maximum a posteriori probability (MAP) decoding algorithm and maximum likelihood (SOVA) decoding algorithm.Fig. 3 illustration a kind of structure of Turbo code decoder 30.It uses the SOVA decoding algorithm.At first, separate perforating device 31 and separate punching to received signal, it is equivalent to the inverse operation of card punch 18 in the Turbo encoder 10 shown in Figure 1.For example,, separate perforating device 31 and will dock the breath of collecting mail and go here and there and change for the situation of (3,1,3) sub-encoders, and the information bit zero padding by card punch 18 is destroyed, three tunnel information are reverted to six the tunnel.In the signal of separating perforating device 31 output, corresponding to three tunnel information X, the Y of the coding result of first sub-encoders 14
0And Y
1Import first soft inputting and soft output (SISO) decoder 32, corresponding to three tunnel information X ', the Y of the coding result of second sub-encoders 16
0' and Y
1' input second soft inputting and soft the output decoder.In addition, in order to improve the decode precision of siso decoder device, each decoder 32 and 33 also needs to import a prior information Z or Z '.The initial value of prior information Z can be set to zero.Specifically, the decoding of the coding result of 32 pairs first sub-encoders 14 of the first siso decoder device except that the soft information of output, is also exported an additional extrinsic information.These output informations are after interleaver 34 interweaves, as the prior information Z ' input second siso decoder device 33.Corresponding soft information and extrinsic information are exported in the coding result decoding of 33 pairs second sub-encoders 16 of the second siso decoder device.Then, these output informations revert to the order before interweaving through deinterleaver 36 deinterleavings, and import the first siso decoder device 32 as prior information Z.So iterate, decode precision is more and more higher, and the error rate is more and more lower.Through after the iteration repeatedly,, then import deinterleaver 37 and carry out deinterleaving, the order before reduction interweaves if think and reached required precision.Because the output of deinterleaver is signed numbers (for example, 0.8 ,-1.2,5.5 or the like) of some expression probability, so need make hard decision with the information after 38 pairs of deinterleavings of decision device.When information greater than 0 the time, decision device output 1; When information less than 0 the time, decision device output 0.The information that obtains after decoding can not equal 0.At last, decision device output decoder result recovers original information X.
United States Patent (USP) the 5th, 406, No. 570 (call in the following text patent ' No. 570) have been introduced a kind of soft output Viterbi algorithm (that is SOVA) structure of decoder (corresponding to SISO32 among Fig. 3,33).The denomination of invention of this patent is " by decision weighted method of convolution code being carried out maximum likelihood decoding; reach corresponding decoder (Method for a Maximum Likelihood Decoding of a Convolutional Code withDecision Weighting, and Corresponding Decoder) ".Its summary of the invention is included in this by reference.
Patent ' No. 570 elder generation is that first grid chart of L and second grid chart that length is L ' carry out Viterbi traceback (that is, survivor path is recalled) to length.Then, in second grid chart, begin to seek parallel backtracking path from the L node to L+L ' node from the L node.In second grid chart, for certain node k, as the hard decision Sk of survivor path and the hard decision S of parallel route
k' when unequal, do following calculating:
Llr=min (llr ', Mdiff
k) (1) wherein, llr is the soft value of information after the current renewal, llr ' is the soft value of information that previous moment keeps, and Mdiff
kBe hard decision S on the node k place survivor path
kThe accumulative total path metric value with the judgement 1-S
kAccumulative total path metric value poor.
What adopted patent ' No. 570 is the f serial backtracking method.Strictly speaking, the f serial backtracking method be to each node in the window successively by formula (1) compare, the soft information result with each node leaves in the shift register group then.After all nodes in the window (for example, a window comprises L node) are recalled end, node of window slip, the data that first register is stored in the Output Shift Register group, and receive new data.Then, again each node in the new window is repeated above-mentioned comparison procedure.Sliding window is finished at last the soft information of a frame bit stream is recalled so again and again.
Yet, in patent ' No. 570, when sliding window, only a node that increases newly in second grid chart is carried out parallel route and recalls (that is, the window node that slides only carries out a parallel route and recalls).This means that the inventor supposes that the survivor path in window slip front and back first grid chart and second grid chart does not have to change when node of window slip is also exported old data thus and received a new data.Obviously, this hypothesis only when a window length equals frame length, could guarantee 100% correct.In other words, only recalling under the bigger and reasonable situation of channel situation of window length, recalling the result just has than higher reliability.But actual conditions often can't satisfy this 2 point.
Should see, compare that the f serial backtracking method operand of patent ' No. 570 is very little with the f serial backtracking method of strictness.For example, suppose that length of window is L.By the f serial backtracking method of described strictness, whole window is recalled need carry out 1+2+ ... + L=L (L+1)/2 minor node is recalled.And in patent ' No. 570 since the hypothesis window slide before and after survivor path constant, recall as long as promptly carry out the L minor node as long as data of new reception are recalled just passable the back so each window slides.
Based on above-mentioned analysis, we know in the SOVA algorithm, in order to guarantee precision, need to keep the long window of recalling, but this can cause memory size excessive.Otherwise,, then can cause precise decreasing if reduce to recall length of window for conserve memory.
An object of the present invention is, provide a kind of and can guarantee decode precision, and can reduce the f serial backtracking SOVA coding/decoding method that soft information is recalled number of times.
Another object of the present invention is that a kind of decoder that uses f serial backtracking SOVA coding/decoding method of the present invention is provided.
In order to achieve the above object, according to one aspect of the present invention, provide a kind of maximal-probability decode method of f serial backtracking, this method may further comprise the steps:
(a) be that the window bit stream of L carries out Viterbi traceback to length, obtain survivor path, and the Viterbi hard decision and the path status information of each node on described survivor path of storing each node;
(b) the described Viterbi hard decision that obtains according to step (a) begins all nodes the described window are recalled as parallel route from last node of described window, and stores the soft information and the parallel route hard decision of described all nodes;
(c) described soft information and the described hard decision that step (b) is obtained carries out the output of m point, and wherein m is the integer of 1≤m≤L;
(d) with the described hard decision of step (c) output corresponding described soft information is modulated, obtain soft output;
(e) described window is moved m node, and receive m new data, thereby form a new window;
(f) described new window is carried out Viterbi traceback, obtain new survivor path, and store corresponding Viterbi hard decision and all nodes path status information on described new survivor path;
(g) the newer survivor path and the survivor path of last window judge whether described new survivor path is connected with the survivor path of last window;
(h) according to the judged result of step (g), and, selectively the node in the described new window is carried out parallel route and recall, obtain corresponding soft information and parallel route hard decision according to described new Viterbi hard decision;
(i) described soft information and the described hard decision that step (h) is obtained carries out the output of m point;
(j) with the described hard decision of step (i) output corresponding described soft information is modulated, obtain soft output; And
(k) repeating step (e) is to the process of step (j), up to frame data are disposed.
In the maximal-probability decode method of the invention described above, to carry out parallel route to m node of new reception at least and recall.And,, so all nodes in the described new window are carried out recalling of parallel route if judge the complete divergence of survivor path of the survivor path and the last window of described new window.Partly be connected with the survivor path of last window if judge the survivor path of described new window, so the node in the part of survivor path and last window divergence in the described new window carried out parallel route and recall.Be connected fully with the survivor path of last window if judge the survivor path of described new window, so new m the node that receives of described new window carried out parallel route and recall.
In said method, parallel route recalls resulting soft information and hard decision promptly can adopt single-point output, also can adopt multiple spot output.
According to another aspect of the present invention, a kind of decoder that uses above-mentioned f serial backtracking maximal-probability decode method is provided, it comprises:
Branch metric calculator is used to calculate the branch path metric value from certain state of certain node to certain state of next node;
Add than selecting calculator, be used to calculate the accumulative total path metric value sum on described branch path metric value and the previous path, calculate two the accumulative total path metric values and the poor absolute value thereof of current state, two accumulative total path metric values that calculate are compared, therefrom select bigger accumulative total path metric value and corresponding path thereof;
Path memory is used to store described adding than the described path of selecting calculator to select;
The state measurement memory is used to store described adding than the described accumulative total path metric value that selects calculator to select;
The difference memory is used to store the described absolute value that adds than the difference of two accumulative total path metric values of the current state of selecting calculator to calculate;
Recall processor, it comprises:
Recall processing unit, be used for carrying out Viterbi traceback computing and parallel route trace-back operation according to from the routing information of path memory and poor from the accumulative total path metric value of difference memory;
First registers group, length is L, is used to store describedly recall processing unit to carrying out routing information and the hard decision that Viterbi traceback obtained when front window;
Second registers group, length is L, is used to store describedly recall processing unit to carrying out parallel route and recall soft information and the hard decision that is obtained when front window;
Symbol modulation is used for the described soft information of recalling processor output is carried out the hard decision modulation, exports soft output; And
Control circuit, it links to each other with above-mentioned each unit, is used to control the contact between these unit;
In addition, describedly recall processor and also comprise:
The 3rd registers group, length is L-m, is used for storing L-m the routing information that register is stored in first memory group described in last window back, wherein m represents that a window recalls the node number of exporting soft information when finishing from second registers group;
Whether comparing unit is used for the routing information in more described in order first registers group and described the 3rd registers group corresponding registers, be connected with the survivor path of last window, and send a signal to described control circuit to judge the survivor path when front window;
Counter is used for counting recalling node;
And, described controller is configured to, according to signal from described comparing unit, order and describedly recall processing unit and the node in the front window is carried out parallel route selectively recall, and when the counting in the described counter surpasses a predetermined value, the soft value of information and parallel route hard decision that preceding m register in order output second registers group stored, to second registers group m position that moves to left, and with in path information storage to the three registers group in L-m register before in first registers group.
This shows that the present invention carries out path status that Viterbi traceback obtained number with an additional register set stores to last window data.Then, to back one window when recalling, the state of each node on the state of each node on the last window survivor path number and the back window survivor path number is compared, judge the connecting in path with this.If the path is connected fully, so only one a window new node that receives in back is carried out that parallel route is soft recalls, and keep the soft traceback information and the parallel route hard decision of last window in the registers group.If the path part is connected, the soft information and the hard decision that keep node corresponding in the registers group so with being connected part, and being carried out parallel route, the non-node (comprising the node that newly receives) that is connected part in path recalls, with recalling the content that obtains soft information and hard decision renewal registers group corresponding registers.If the complete divergence in path needs so all nodes in one window of back are carried out that parallel route is soft recalls, and upgrades the content of all registers in the registers group.
This shows that the present invention judges the connecting in path, window slip front and back by the path status information that keeps in the registers group, and selectively the node in the new window is carried out parallel route according to judged result and recall.Therefore, avoided the identical part of survivor path is carried out softly recalling, recalled number of times thereby reduced.On the other hand, in the present invention, the survivor path of reference does not have deviation with the survivor path of reality when recalling owing to soft information, so guaranteed decode precision.
Fig. 1 is a kind of structure of Turbo code encoder;
Fig. 2 is the structure chart of RSC sub-encoders in the Turbo code encoder;
Fig. 3 is the structure chart of Turbo code decoder;
Fig. 4 is a schematic diagram, illustration according to the operation principle of the SOVA coding/decoding method of preferred embodiment of the present invention;
Fig. 5 is a flow chart, illustration according to the course of work of the SOVA coding/decoding method of preferred embodiment of the present invention;
Fig. 6 one block diagram, illustration the structure of soft inputting and soft output decoder in the Turbo code decoder shown in Figure 3;
Fig. 7 is a block diagram, illustration recall the structure of processor.
Below in conjunction with Fig. 4 and Fig. 5, preferred embodiment of the present invention is described.
Fig. 4 is a schematic diagram, illustration according to the operation principle of the SOVA coding/decoding method of preferred embodiment of the present invention.In Fig. 4, dotted line is represented survivor path, and solid line is represented parallel route.As shown in Figure 4, suppose that a window comprises L node when Viterbi traceback that carries out survivor path and parallel route soft recalled.Earlier first window is carried out Viterbi traceback, obtain corresponding survivor path, and with the Viterbi hard decision S of each node
k(S
k=0 or 1,0≤k≤L-1) and the state S[k of each node on survivor path] (for example S[k]=0～7,0≤k≤L-1) be stored in respectively in the corresponding registers of registers group A.Registers group A can be made up of L register, and each register comprises two territories, is respectively applied for storage Viterbi hard decision of respective nodes and state number.Then, the soft information that begins all nodes of first window are done parallel route from last node L-1 is recalled.Specifically, to node n (0≤n≤L-1) carry out parallel route to recall, and recall through node k (during 0≤k≤n), with the parallel route hard decision S of node k
k' with survivor path on the hard decision S of this node
k(that is the value of k+1 register among the registers group A) compares.If different, then this is recalled the Mdiff of starting point n
nThe value of k+1 register compares among value and the registers group B.Here, Mdiff
nValue is the absolute value of difference of two cumulative metrics values of two states from node n to previous node, registers group B is made up of L register, and each register comprises two territories, be respectively applied for the memory parallel path and recall soft information and the hard decision that is obtained, the initial value of register is set to infinity.Through relatively, if Mdiff
nLess, then use Mdiff
nUpgrade the value of k+1 register.Otherwise keep original value.In fact, this comparison and renewal process are exactly the formula 1 that provides in the background technology.After node n is dated back to the starting point of first window always, again node n-1 is carried out parallel route and recall.And so forth, recall until first window and finish.At this moment, storing the Viterbi hard decision of first a window L node and corresponding state number among the registers group A, and the soft information of storing first a window L node among the registers group B.In addition, also stored the parallel route hard decision corresponding among the registers group B with each soft information.
One window recall can single-point after finishing output, also can multiple spot output.In the present embodiment, adopt 2 outputs.Specifically, first window recall finish after, soft information and the hard decision preserved in preceding 2 registers of output register group B.Then, with the content of registers group B two positions that move to left, and the value of last two registers is made as infinity.In addition, the path status that also L-2 the register in back among the registers group A will be stored number stores among the additional register set A ' in order.In the present embodiment, owing to adopt 2 outputs, so registers group A ' is made up of L-2 register.
Next recalling of second window described.Sliding window receives 2 new data.Then, a new window is carried out Viterbi traceback, obtain new survivor path, and hard decision that will corresponding each node and state number are stored among the registers group A.As seen from Figure 4, in the present embodiment, the state of respective nodes is number different in the state of the second window Viterbi traceback terminal point number and first window.This explanation survivor path complete divergence need carry out that parallel route is soft recalls to whole nodes of second window.Specifically, in Fig. 4, the terminal point of second window is a node 2, and its state number is 1, and the state of node 2 on survivor path number is 0 in first window.The state of first node is number inconsistent in old window and the new window, so the complete divergence of survivor path.Therefore, need all nodes to second window to carry out that parallel route is soft recalls in this case.Its trace-back process is the same with the process that the above-mentioned first window parallel route is recalled.
Second window recall finish after, storing the Viterbi hard decision of second each node of window and the state of each node on survivor path number among the registers group A, and storing soft information and the parallel route hard decision that second window is all recalled acquisition among the registers group B.
Soft information and the hard decision of preserving in preceding 2 registers of output register group B once more.Then, with the content of registers group B two positions that move to left, and the value of last two registers is made as infinity.Equally, also the path status that L-2 the register in back among the registers group A will be stored number stores among the registers group A ' in order.
Next the trace-back process of the 3rd window is described.Sliding window receives 2 new data.Then the 3rd window is carried out Viterbi traceback, obtain new survivor path, and hard decision that will corresponding each node and state number are stored among the registers group A.As shown in Figure 4, the state of corresponding node is number identical the state of the survivor path of the 3rd window from node 4 to node L+1 number and second window.This explanation survivor path is connected fully.At this moment, the value of L-2 register before can keeping among the registers group B.Only need calculate soft traceback information, and upgrade the value of last two registers among the registers group B with soft information that calculates and hard decision 2 data (they are corresponding to node L+2 and L+3) of new reception.The soft retrogressive method of parallel route as hereinbefore.The 3rd window recall finish after, storing the Viterbi hard decision of the 3rd each node of window and the state of each node on survivor path number among the registers group A, and storing the soft information and the parallel route hard decision of the 3rd window among the registers group B.The same with the situation of first and second windows, the content among the output register group B in preceding 2 registers.Then, with the content of registers group B two positions that move to left, and the value of last two registers is made as infinity.Equally, also the path status that L-2 the register in back among the registers group A will be stored number stores among the registers group A ' in order.
See the situation of recalling of four-light again.As shown in Figure 4, the survivor path of four-light from node 6 to node 9 state number and the 3rd window on the survivor path state of respective nodes number identical.But the state of four-light node No. 10 is that the state of 2, the three window nodes No. 10 is 3, both differences.This explanation survivor path partly is connected.At this moment, can keep the value of preceding 4 registers among the registers group B, calculate soft traceback information, and upgrade the value of the 5th to L register among the registers group B with soft information that calculates and hard decision from node 10 to node L+5.The soft retrogressive method of parallel route as hereinbefore.Four-light recall finish after, storing the Viterbi hard decision of each node of four-light and the state of each node on survivor path number among the registers group A, and storing the soft information and the parallel route hard decision of four-light among the registers group B.
So in the manner described above, sliding window again and again carries out the path to the new window of each acquisition and is connected and judges, selectively the node in the window is carried out parallel route according to judged result then and recalls, up to finishing recalling a frame bit stream.
In the above-described embodiments, the description that second window, the 3rd window and four-light parallel route are recalled is three kinds of situations in order to illustrate that the path is connected.In actual trace-back process, these three kinds of situations can occur by any order.
Fig. 5 is a flow chart, illustration according to the course of work of the SOVA coding/decoding method of preferred embodiment of the present invention.In the present embodiment, recalling length of window is L, and adopts the m point.
Supposing that last window has been recalled finishes.In step 502, among the output register group B before the soft information and the hard decision of m register-stored, with m the position that move to left of the content in L-m the register in back, and with among the registers group B at last the value of m register be made as infinity; The path status information stores that L-m the memory in back among the registers group A stored is in additional register set A '.In step 504, receive m new data, carry out the Viterbi traceback of a new window, the Viterbi hard decision that calculates and the state of each node on survivor path number are stored among the registers group A.In step 506, set i=1.In step 508, judge among the registers group A path status that i register store number whether with registers group A ' in the path status stored of i register number equate.If equate that then process proceeds to step 510.In step 510, i is increased 1.Then, in step 512, judge whether that all states that registers group A ' is stored number all contrast.If all compare, represent that original routing information, soft information and hard decision can keep.Process proceeds to step 518, the L-i+1=m point of new reception is carried out parallel route recall.One window recall finish after, if a frame is recalled also do not finish, then process is got back to step 502, carries out m point output.If finished the recalling of frame data, then trace-back process finishes.
If step 512 is judged all states of being stored among all relatively not intact registers group A ' number, process is returned step 508 so, and the value of registers group A and the middle next register of A ' is compared.If in step 508, judge among the registers group A that path status that i register store number is not equal among the registers group A ' path status that i register store number, process proceeds to step 518 so.In step 518, keep among the registers group B before soft information and hard decision in i-1 register, a L-i+ 1 node in back is carried out soft information recalls, and will recall the soft information that obtains and hard decision and be stored in register respectively in back L-i+1 register.Then, process proceeds to step 514, and a window is recalled and finished.
Next in conjunction with Fig. 6 and Fig. 7, illustrate the device of implementing SOVA coding/decoding method of the present invention.Fig. 6 one block diagram, illustration the structure of soft inputting and soft output (SISO) decoder in the Turbo code decoder shown in Figure 3.As shown in the drawing, branch path metric calculator (BMU) 41 calculates from certain state of certain node and arrives the path metric value that two kinds of next nodes may states, and result of calculation sent into adds than selecting calculator (ACS) 42.Add than selecting calculator 42 the accumulative total path metric value addition on branch path metric value and the previous path, calculate two the accumulative total path metric values and the poor absolute value thereof of current state, two accumulative total path metric values that calculate are compared, therefrom select bigger accumulative total path metric value and corresponding path thereof, then with selection result respectively input state metric memory (SMM) 45 and path memory 43, and in the absolute value input difference memory 46 with the difference of two accumulative total path metric values calculating on the current state.The poor of accumulative total path metric value that processor 47 provides according to routing information that provides according to path memory 43 and difference memory 46 is provided, carries out Viterbi traceback and parallel route and recall, export soft information llr and hard decision.48 pairs of symbol-modulated are recalled the soft information of processor 47 outputs and are carried out the hard decision modulation, also claim symbol-modulated.Specifically,, then soft information is taken advantage of positive sign,, then soft information is taken advantage of negative sign if hard decision is input as 0 if hard decision is input as 1.Obtain soft output thus.At this moment, if decoding does not also reach predetermined precision, then to do normalization 49 and calculate, as the extrinsic information of next stage iteration input.
In addition, in this soft inputting and soft output decoder, also comprise controller 44, it is used to control the contact between above-mentioned each parts.
Fig. 7 is a block diagram, illustration recall the structure of processor 47.As shown in Figure 7, recall processor 47 and comprise and recall processing unit 470, the accumulative total path metric value that its provides according to routing information and difference memory 46 from path memory 43 poor carries out Viterbi traceback and parallel route and recalls.State that Viterbi traceback is obtained number and Viterbi hard decision are stored among the registers group A, and parallel route soft information and the parallel route hard decision that obtains that trace back is stored among the registers group B.When a window recall finish after, under the control of controller 44, among the output register group B before the value of m register, and make afterwards value in L-m the register m position that moves to left.In addition, controller 44 also indicates path status that back L-m register among the registers group A stored number to store among the registers group A '.Then, controller 44 control is recalled 470 pairs of new windows of processing unit and is carried out Viterbi traceback, and the path status that will newly obtain number and Viterbi hard decision are stored among the registers group A.Then, in comparing unit 474, with among the registers group A about number comparing successively about the path status of last window among the path status of a new window number and the registers group A '.When not finding path status number not simultaneously, comparing unit 474 sends a signal to controller 44.Controller 44 can keep the value in which register among the registers group B according to this signal deciding, need to upgrade the value in which register, and recalls processing unit 470 and need carry out parallel route to which node and recall.Recall the instruction of processing unit 470, the node of a new window is carried out parallel route selectively recall according to controller 44.In addition, recall processor 47 and also comprise a counter, controller judges whether that according to the counting of counter a window recalls end.If finish, then as previously mentioned, m value among the order output register group B carried out shift left operation to registers group B, and the L-m value among the registers group A stored among the registers group A '.
Because the present invention is carrying out each window before soft information recalls, the path status information of last window survivor path to be compared with the path status information of working as front window, so on memory size, compare with the f serial backtracking method of strictness, f serial backtracking of the present invention need increase an additional registers group A '.Situation for single-point output also preferably increases L-1 register.From operand, even adopt single-point output, the present invention also increases the inferior compare operations of 2 (L-1) (corresponding to step 508 and step 512) at most to recalling of every window L length, and (L-1) inferior storage operation (corresponding to the unloading between registers group A and the A ' in the step 502).If the calculating average probability has then increased (k-1) * 3/2 time comparison and (k-1)/2 time storage operation.If but the situation that survivor path is connected fully in soft information trace-back process appearance is more, the path that is connected part when perhaps survivor path partly is connected is long, can significantly reduce soft number of times of recalling so.
Should be appreciated that in the methods of the invention, the survivor path and the actual survivor path of reference do not have deviation when recalling owing to all soft information, so the soft precision of recalling guarantees.
For Digital Signal Processing (DSP), soft operand of recalling is excessive during owing to Turbo code decoder f serial backtracking, so DSP can only be applicable to the situation of the low code check of Turbo code.But the method for the application of the invention, DSP can be applied to the higher situation of code check in the Turbo code.Simultaneously, in clock cycle well-to-do and the conditional FPGA of scale, PLD design, also can use method of the present invention.
Though the coding/decoding method of Turbo code encoder in cdma2000 and the WCDMA motion and its RSC sub-encoders has been described in preferred embodiment of the present invention, thought of being set forth among the present invention and algorithm change deriving under other modes and also belong within the rights protection scope of the present application.
Claims (15)
1. the maximal-probability decode method of a f serial backtracking is characterized in that, said method comprising the steps of:
(a) be that the window bit stream of L carries out Viterbi traceback to length, obtain survivor path, and the Viterbi hard decision and the path status information of each node on described survivor path of storing each node;
(b) the described Viterbi hard decision that obtains according to step (a) begins all nodes the described window are recalled as parallel route from last node of described window, and stores the soft information and the parallel route hard decision of described all nodes;
(c) described soft information and the described hard decision that step (b) is obtained carries out the output of m point, and wherein m is the integer of 1≤m≤L;
(d) with the described hard decision of step (c) output corresponding described soft information is modulated, obtain soft output;
(e) described window is moved m node, and receive m new data, thereby form a new window;
(f) described new window is carried out Viterbi traceback, obtain new survivor path, and store corresponding Viterbi hard decision and all nodes path status information on described new survivor path;
(g) the newer survivor path and the survivor path of last window judge whether described new survivor path is connected with the survivor path of last window;
(h) according to the judged result of step (g), and, selectively the node in the described new window is carried out parallel route and recall, obtain corresponding soft information and parallel route hard decision according to described new Viterbi hard decision, and;
(i) described soft information and the described hard decision that step (h) is obtained carries out the output of m point;
(j) with the described hard decision of step (i) output corresponding described soft information is modulated, obtain soft output; And
(k) repeating step (e) is to the process of step (j), up to frame data are disposed.
2. maximal-probability decode method as claimed in claim 1 is characterized in that, step (h) is carried out parallel route selectively and recalled and comprise that at least m the node that step (e) is received carries out parallel route and recall.
3. maximal-probability decode method as claimed in claim 2, it is characterized in that, described step (g) is judged the survivor path of described new window and the complete divergence of survivor path of last window, and described step (h) comprises carries out recalling of parallel route to all nodes in the described new window, and upgrades all soft information and parallel route hard decision that last window obtains.
4. maximal-probability decode method as claimed in claim 2, it is characterized in that, described step (g) judges that the survivor path of described new window partly is connected with the survivor path of last window, and described step (h) comprises soft information and the parallel route hard decision partly corresponding with the survivor path linking that keeps last window acquisition, node in the part of survivor path and last window divergence in the described new window is carried out parallel route recall, and upgrade soft information and parallel route hard decision partly corresponding in the last window with non-linking with soft information that obtains and parallel route hard decision.
5. maximal-probability decode method as claimed in claim 2, it is characterized in that, described step (g) judges that the survivor path of described new window is connected fully with the survivor path of last window, and described step (h) comprises that new m the node that receives of described new window carried out parallel route recalls.
6. maximal-probability decode method as claimed in claim 1, it is characterized in that described step (b) and step (h) comprise when recalling through certain node k, this node is compared at hard decision on the survivor path and the hard decision on the parallel route, if unequal, then do following calculating:
llr＝min(llr′，Mdiiff
n)
Wherein, llr is the soft value of information after the current renewal, and llr ' is the soft value of information that previous moment keeps, and Mdiff
nBe to recall hard decision S on the starting point n place survivor path
nThe accumulative total path metric value with the judgement 1-S
nAccumulative total path metric value poor.
7. maximal-probability decode method as claimed in claim 1 is characterized in that m=1.
8. maximal-probability decode method as claimed in claim 1 is characterized in that, m＞1.
9. decoder that uses the f serial backtracking maximal-probability decode method, it comprises:
Branch metric calculator is used to calculate the branch path metric value from certain state of certain node to certain state of next node;
Add than selecting calculator, be used to calculate the accumulative total path metric value sum on described branch path metric value and the previous path, calculate two the accumulative total path metric values and the poor absolute value thereof of current state, two accumulative total path metric values that calculate are compared, therefrom select bigger accumulative total path metric value and corresponding path thereof;
Path memory is used to store described adding than the described path of selecting calculator to select;
The state measurement memory is used to store described adding than the described accumulative total path metric value that selects calculator to select;
The difference memory is used to store the described absolute value that adds than the difference of two accumulative total path metric values of the current state of selecting calculator to calculate;
Recall processor, it comprises:
Recall processing unit, be used for carrying out Viterbi traceback computing and parallel route trace-back operation according to from the routing information of path memory and poor from the accumulative total path metric value of difference memory;
First registers group, length is L, is used to store describedly recall processing unit to carrying out routing information and the hard decision that Viterbi traceback obtained when front window;
Second registers group, length is L, is used to store describedly recall processing unit to carrying out parallel route and recall soft information and the hard decision that is obtained when front window;
Symbol modulation is used for the described soft information of recalling processor output is carried out the hard decision modulation, exports soft output; And
Control circuit, it links to each other with above-mentioned each unit, is used to control the contact between these unit;
It is characterized in that, describedly recall processor and also comprise:
The 3rd registers group, length is L-m, is used for storing L-m the routing information that register is stored in first memory group described in last window back, wherein m represents that a window recalls the node number of exporting soft information when finishing from second registers group;
Whether comparing unit is used for the routing information in more described in order first registers group and described the 3rd registers group corresponding registers, be connected with the survivor path of last window, and send a signal to described control circuit to judge the survivor path when front window;
Counter is used for counting recalling node;
And, described controller is configured to, according to signal from described comparing unit, order and describedly recall processing unit and the node in the front window is carried out parallel route selectively recall, and when the counting in the described counter surpasses a predetermined value, the soft value of information and parallel route hard decision that preceding m register in order output second registers group stored, to second registers group m position that moves to left, and with in path information storage to the three registers group in L-m register before in first registers group.
10. decoder as claimed in claim 9 is characterized in that, describedly recalls processing unit and is configured for and at least m node is carried out parallel route and recall.
11. decoder as claimed in claim 10, it is characterized in that, the described signal indication that described comparing unit sends is described when the survivor path of front window and the complete divergence of survivor path of last window, and describedly recall processing unit and be configured for and described all nodes in the front window are carried out parallel route recall, and upgrade all soft information and parallel route hard decision in described second registers group.
12. decoder as claimed in claim 10, it is characterized in that, the described survivor path when front window of the described signal indication that described comparing unit sends partly is connected with the survivor path of last window, and described recall processing unit be configured for to described in the front window node in the part of survivor path and last window divergence carry out parallel route and recall, and upgrade in described second registers group with non-and be connected partly corresponding soft information and parallel route hard decision.
13. decoder as claimed in claim 10, it is characterized in that, the described survivor path when front window of the described signal indication that described comparing unit sends is connected fully with the survivor path of last window, and describedly recalls processing unit and be configured for and described m node when the front window reception carried out parallel route recall.
14. decoder as claimed in claim 9 is characterized in that, m=1.
15. decoder as claimed in claim 9 is characterized in that, 1＜m≤L.
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| CN101425869B (en) * | 2007-11-02 | 2011-12-07 | 华为技术有限公司 | Decoding method and apparatus |
| CN101262233B (en) * | 2008-04-17 | 2012-09-12 | 四川虹微技术有限公司 | Viterbi coding method |
| CN102468909A (en) * | 2010-11-09 | 2012-05-23 | 中兴通讯股份有限公司 | Method for updating soft information and demodulating equipment |
| CN102142849B (en) * | 2011-02-15 | 2014-07-30 | 无锡物联网产业研究院 | Viterbi decoding method and Viterbi decoder |
| US9385896B1 (en) * | 2015-07-09 | 2016-07-05 | Huawei Technologies Co., Ltd. | Method and apparatus for low-complexity quasi-reduced state soft-output equalizer |
| US11099781B2 (en) * | 2018-07-19 | 2021-08-24 | Silicon Motion, Inc. | Flash memory controller, flash memory module and associated electronic device |
| CN111147086B (en) * | 2019-12-26 | 2022-04-22 | 中国科学院计算技术研究所 | Code modulation method, system, medium and electronic device |
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