CN1333599A - Decoding method and decoder realizing same - Google Patents
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- CN1333599A CN1333599A CN 01130853 CN01130853A CN1333599A CN 1333599 A CN1333599 A CN 1333599A CN 01130853 CN01130853 CN 01130853 CN 01130853 A CN01130853 A CN 01130853A CN 1333599 A CN1333599 A CN 1333599A
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Abstract
The present invention provides a self-adaptive iterated decodign scheme which has no need of externally-adding bit and can effectively reduce average decoding iterative frequency of parallel concatenated convolution code and serial concatenated convolution code and decoder for implementing said scheme. i.e. in the existent decoder an iteration stop detector is added. Said invention can ensure good error rate, almost does not increase decoding complexity and does not use external-added bit, and can reduce average decoding interation frequency so as to reduce average decoding time delay of parallel concatenated convolution code and serial concatenated convolution code.
Description
What this patent related to is the error correction/encoding method of transmission information in bad channel, especially relates to interpretation method and decoder thereof in parallel link convolution code and the serial link convolution coding technology.
C.Berrou, A.G1avieux, P.Thitimajshama delivered parallel link convolutional encoding first (Parallel Concatenated Convolutional Codes:PCCC) technology in 1993 at Proceedings of theIEEE International Conference on Communications (ICC ' 93) (1064-1074 page or leaf) and (have another name called: Turbo code).The parallel link convolutional encoding is described as " near the error correction coding and the decoding of Shannon limit ".Since then, parallel link convolutional encoding is the focus that people study always.
The decoded mode of parallel link convolutional encoding is the iterative decoding of soft input/soft output.Decoder reaches the purpose that reduces error rate by iteration repeatedly, repeatedly exports decode results after the iteration.C.Berrou, A.Glavieux, P.Thitimajshama used maximum iteration time in " near the error correction coding and the decoding of Shannon limit: Turbo code " (ICC ' 93) literary composition is 18 times.What big iterations brought is big decoding delay, and big decoding delay can not satisfy the requirement of real time communication.
In the past few years scientific circles have proposed multiple adaptive iteration decoding algorithm, promptly reduce the method for the average decoding iterations of parallel link convolution code under the prerequisite that not too influences final error rate.J.Hagenauer, the paper " iterative decoding of binary block convolution code " that E.Offer and L.Papke deliver in IEEE Trans.Inform Theory (IT-42,429-445 page or leaf 1996) proposes to reduce by the method for the cross-entropy that calculates the soft output of decoder the average decoding iterations of parallel link convolutional encoding.B.Kim and H.S.Lee propose to reduce by the method for the variance of the soft output of calculating decoder the average decoding iterations of parallel link convolutional encoding in the paper that Proceedings of the IEEE Region 10 Conference (TENCON ' 99.494-497 page or leaf the 1st volume) deliver " reduces the iterations of Turbo code decoder " with external information.But these two kinds of methods are all not so good aspect error rate and average iterations.Effective method is, C.W.Yue, K.B.Letaief.R.S.Cheng, R.D.Murch proposes to add the average decoding iterations that CRC (CRC) bit reduces the parallel link convolution code in frame data in the paper " about the FER performance and the decoding complexity of Turbo code " that IEEE Vehicular Technology Conference (VTC ' 99,2214-2218 page or leaf) delivers.This method can reduce the average decoding iterations of parallel link convolution code effectively, but the CRC that adds (CRC) bit makes the utilance of resource descend again.
Serial link convolutional encoding (Serial Concatenated Convolutional Codes:SCCC) also adopts iterative decoding in addition, also has the problems referred to above.
The purpose of this patent provides a kind of decoder that need not the adaptive iteration decoding scheme of the average decoding iterations that adds bit and can reduce parallel link convolution code and serial link convolution code effectively and realize this scheme.
Interpretation method of the present invention is made of the following step:
1. will decipher iteration count I and be initialized as 1;
2. the input data are deciphered;
3. as I＜I
MinOr I
Min＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I=I
MinThe time, judge with door 1 to be output as 1 or 0.If be 1, finish iterative decoding to these frame data; Otherwise I add 1 and return the 2nd the step;
5. work as I=I
MaxThe time, finish iterative decoding to these frame data; Wherein, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
Decoder of the present invention stops detector for add an iteration in existing decoder.
The present invention is helpful to the practice of parallel link convolution code and serial link convolution code.Guaranteeing good error probability (bit error rate (BER) BER and FER (Floating Error Rate) FER) and increasing decoding complexity hardly and do not use under the prerequisite of the bit that adds, the present invention can reduce the average decoding iterations of parallel link convolution code and serial link convolution code, thereby has reduced the average decoding delay of parallel link convolution code and serial link convolution code.
The present invention is applicable to the parallel link convolution code and the serial link convolution code of recursive systematic convolutional code and onrecurrent convolution code.The present invention is applicable to the parallel link convolution coder and the serial link convolution code of various code rate, different coding constraint length, different generator polynomial, different interleaving device and different frame length.The present invention only is used in the parallel link convolution code and the serial link convolution code of band tail bit, and is applicable to the various different modes that add tail bit.
The present invention can be used for the generator polynomial situation inequality of each recursive system convolution coder of encoder equally, and just the structure of each iteration termination detector in the decoder should design separately according to corresponding with it recursive system convolution coder generator polynomial.
Below in conjunction with accompanying drawing the present invention is elaborated:
Fig. 1 is conventional parallel link convolution coder structural representation;
Fig. 2 is conventional serial link convolution coder structural representation;
Fig. 3 is the structural representation of an embodiment of termination detector of the present invention;
Fig. 4 is the structural representation of another embodiment of termination detector of the present invention;
The structural representation of one embodiment of Fig. 5 parallel link Convolutional Decoder Assembly of the present invention;
The structural representation of one embodiment of Fig. 6 serial link Convolutional Decoder Assembly of the present invention;
Fig. 7 is a kind of structure diagram of adaptive iteration parallel link Convolutional Decoder Assembly.
Encoder among Fig. 1 can be recursive systematic convolutional code (Recursive SystematicConvolutional codes:RSC) encoder or onrecurrent convolution code (NonrecursiveSystematic Convolutional codes:NSC) encoder.
When designing iteration at the parallel link convolution code of using recursive systematic convolutional code and serial link convolution code and stop detector, the hypothesis encoder all is recursive systematic convolutional code and uses identical generator polynomial that each recursive systematic convolutional code encoder has all used tail bit separately to stop encoder earlier.The generator polynomial of supposing them all is g
f(D)/g
b(D).It is [1/g by a hard decision device, a generator polynomial that an iteration stops detector
b(D) ..., D
M-1/ g
b(D)] recursive system convolution coder, a Digital Logic NOR gate and a gate-controlled switch constitute.If it is 1 that this iteration stops the detector output logic, assert that then decoding is correct; Otherwise assert that decoding is incorrect.Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination encoder for convolution codes of hard decision device, the M of an encoder for convolution codes output connects each input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector.Its workflow is before frame data input iteration to be stopped all register zero clearings in the detector, with switch opens, import the data of a frame then, after data (the comprising all tail bit) input of a frame, switch closure, the result of output NOR gate computing.
The formation and the principle that stop detector at the iteration of the parallel link convolution code of using the nonrecursive system convolution code and the design of serial link convolution code are as follows: use the parallel link convolution code or the serial link convolution code of nonrecursive system convolution code, all use complete 0 bit as hangover.The constraint length K of supposing nonrecursive system convolution codes all in parallel link convolution code or the serial link convolution code all is M+1 (wherein the register number is M).At the iteration of this parallel link convolution code and serial link convolution code design stop detector by a hard decision device, generator polynomial be [1 ..., D
M-1] convolution coder, Digital Logic NOR gate and a gate-controlled switch constitute, its operation principle is to judge declaring the result firmly and whether be Binary Zero entirely through tail bit in the decoding soft output in back.If it is 1 that this iteration stops the detector output logic; Otherwise output logic is 0.Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination encoder for convolution codes of hard decision device, the M of an encoder for convolution codes output connects each input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector.
Encoder among Fig. 2 can be recursive systematic convolutional code (Recursive SystematicConvolutional codes:RSC) encoder or onrecurrent convolution code (NonrecursiveSystematic Convolutional codes:NSC) encoder.
Describe the embodiment of the termination detector arrangement of employed parallel link convolution code (Turbo code) design in the cdma2000 standard that proposes at Qualcomm company among the present invention with reference to Fig. 3, wherein feed back generator polynomial g
b(D)=1+D
2+ D
3Its structure is: the input data connect the input of hard decision device, the input port a of the output termination binary adder 1 of hard decision device, the input port b of the output termination binary adder 1 of binary adder 2, the input of the output termination register 1D of binary adder 1, the input of the output termination register 2D of register 1D, the input of the output termination register 3D of register 2D, the input of binary adder 2 meets register 2D respectively, the output of 3D, three inputs of NOR gate meet register 1D respectively, the output of 2D and adder 1, a controllable switch is received the output of NOR gate, and this controllable switch is output as the output that this iteration stops detector.
With reference to Fig. 4 another most preferred embodiment of the present invention is described---at nonrecursive system convolution code constraint length in the parallel link convolution coder is the termination detector of 4 (wherein the register number is 3) design.Its structure is: the input data connect the input of hard decision device, the input of the output termination register 1D of hard decision device, the input of the output termination register 2D of register 1D, three inputs of NOR gate connect the output of register 1D, 2D and hard decision device respectively, a controllable switch is received the output of NOR gate, and this controllable switch is output as the output that this iteration stops detector.
Figure 5 shows that a kind of schematic diagram that uses iteration to stop the parallel link Convolutional Decoder Assembly embodiment of detector.N iteration stops the output conduct of detector and the input of door 1G.This decoder is to design at the parallel link encoder for convolution codes that has N group tail bit (tail bits).This decoder can use any one decoding algorithm, as maximum a posteriori probability MAP, Log-MAP and Max-Log-MAP decoder etc.
New adaptive iteration decoding scheme of the present invention comprises the steps:
1. will decipher iteration count I and be initialized as 1;
2. will carry out demodulation multiplexer (demultiplexer) from the data that channel receives and conciliate canceller (depuncturer), and the data of corresponding first group of convolution code check bit in the dateout and systematic code data will be input to decoder 1T decipher.The output of decoder lT is input to interleaver 1I and iteration stops detector 1M.The data that the output of interleaver 1I and demultiplexing are separated the second group system convolution code check bit of canceller output are input to decoder 2T, by this process data remaining decoder of process and interleaver, the output of last decoder NT is input to iteration and stops detector NM and deinterleaver 1J, 2J, the output of deinterleaver 1J is as the input of next iteration decoder 1M, and the output that all iteration stop detector is input to and door 1;
3. as I＜I
MinOr I
Min＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I=I
MinThe time, judge with door 1 to be output as 1 or 0.If be 1, finish iterative decoding to these frame data, the output of deinterleaver 2J is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5. work as I=I
Max, finish iterative decoding to these frame data, the output of deinterleaver 2J is input to the hard decision device, the hard decision device is output as the output of final decoding.
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
Figure 6 shows that a kind of schematic diagram that uses iteration to stop the serial link Convolutional Decoder Assembly embodiment of detector.2 iteration stop the output conduct of detector and the input of door 1G.This decoder is to design at the serial link encoder for convolution codes that has 2 groups of tail bit (tail bits).This decoder can use any one decoding algorithm, as maximum a posteriori probability MAP, Log-MAP and Max-Log-MAP decoder etc.
New adaptive iteration decoding scheme of the present invention comprises the steps:
1. will decipher iteration count I and be initialized as 1;
2. the data that will receive from channel are conciliate canceller 1X to demultiplexing and be carried out demultiplexing (demultiplexe) and conciliate deletion (depuncture), the data of corresponding convolution code check bit in the dateout and systematic code data are input to decoder 1T decipher.The output of decoder 1T is input to deinterleaver 1J and iteration stops detector 1M.The output of deinterleaver 1J is input to demultiplexing and separates canceller 2X, its output is input to decoder 2T, the output of decoder 2T is input to iteration and stops detector 2M and interleaver 1I, the output of interleaver 1I is as the input of next iteration decoder 1M, and the output that all iteration stop detector is input to and door 1;
3. as I＜I
MinOr I
Min＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4. work as I=I
MinThe time, judge with door 1 to be output as 1 or 0.If be 1, finish iterative decoding to these frame data, the output of deinterleaver 2J is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5. work as I=I
Max, finish iterative decoding to these frame data, the output of deinterleaver 2J is input to the hard decision device, the hard decision device is output as the output of final decoding.
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
The present invention can combine with other adaptive iteration decoding algorithms (the adaptive iteration decoding algorithm that adds CRC (CRC) bit as use), reaches the purpose that reduces the iterative decoding number of times.
Add CRC (CRC) bit in view of all using in existing most wireless communication systems, the present invention combines and can use the condition that adds CRC (CRC) bit on a small quantity to be issued to extraordinary decoding effect (especially aspect error rate and the decoding delay) with the adaptive iteration decoding algorithm that use adds CRC (CRC) bit.
Fig. 7 is for method of the present invention with add the embodiment of the adaptive iteration parallel link Convolutional Decoder Assembly that cyclic redundancy code (CRC) method is used in combination.Cyclic redundancy code (CRC) checker and iteration termination detector all arrive in the output of N decoder input, if cyclic redundancy code (CRC) checker verification succeeds wherein, output logic 1, otherwise output logic 0.The output of N cyclic redundancy code (CRC) checker and N iteration termination detector all is input to and door 1.If be output as logical one, finish whole iterative decoding process with door.
End interpretation method of the present invention can also comprise the steps:
1. will decipher iteration count I and be initialized as 1;
2. the input data are deciphered;
3. as I＜I
MinThe time, I add 1 and return the 2nd the step;
4. work as I
Min≤ I＜I
MaxThe time, judge with door 1 to be output as 1 or 0.If be 1, finish iterative decoding to these frame data, the output of deinterleaver 2J is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step.
5. work as I=I
MaxThe time, finish iterative decoding to these frame data, the output of deinterleaver 2J is input to the hard decision device, the hard decision device is output as the output of final decoding.
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
Claims (7)
1. a decoder that is applied to parallel link convolution code and serial link convolution code is characterized by and adds that in traditional iterative decoder an iteration stops detector.
2. decoder according to claim 1 is characterized by described iteration termination detector and comprises: a hard decision device, an encoder for convolution codes, a NOR gate and a controllable switch; The encoder for convolution codes that described iteration stops in the detector is to be [g at the feedback generator polynomial
b(D)] recursive systematic convolutional code design (wherein its register number is M), its generator polynomial is [1/g
b(D) ..., D
M-1/ g
b(D)]; This NOR gate is the NOR gate of M input port; This controllable switch is only closed in whole frame data (comprising tail bit) input back, at next frame data input front opening; Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination encoder for convolution codes of hard decision device, the M of an encoder for convolution codes output connects each input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector.
3. decoder according to claim 1 is characterized by described iteration termination detector and comprises: a hard decision device, an encoder for convolution codes, a NOR gate and a controllable switch; The encoder for convolution codes that iteration stops in the detector is at nonrecursive system convolution code (wherein its register number is M) design, its generator polynomial be [1 ..., D
M-1]; This NOR gate is the NOR gate of M input port; This controllable switch is only closed in whole frame data (comprising tail bit) input back, at next frame data input front opening; Syndeton comprises in described iteration termination detector: data are from the input input of hard decision device, the input of the output termination encoder for convolution codes of hard decision device, the M of an encoder for convolution codes output connects each input of NOR gate respectively, a controllable switch is received the output of NOR gate, and controllable switch is output as the output that this iteration stops detector.
4. adaptive iteration decoding scheme is characterized by by the following step and constitutes:
1). will decipher iteration count I and be initialized as 1;
2). the input data are deciphered;
3). as I＜I
MinOr I
Min＜I＜I
MixThe time, I add 1 and return the 2nd the step;
4). work as I=I
MinThe time, judge with door 1 to be output as 1 or 0; If be 1, finish iterative decoding to these frame data, the output of deinterleaver is input to the hard decision device, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
MaxThe time, finish iterative decoding to these frame data, the output of deinterleaver is input to the hard decision device, the hard decision device is output as the output of final decoding;
Wherein, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
5. adaptive iteration decoding scheme according to claim 4 is characterized by also and can be made of the following step:
1). will decipher iteration count I and be initialized as 1;
2). will carry out demultiplexing (demultiplex) from the data that channel receives and conciliate deletion (depuncture), and the data of the corresponding first group system convolution code check bit in the dateout and systematic code data will be input to decoder 1T decipher.The output of decoder 1T is input to interleaver 1I and iteration stops detector 1M.The data that the output of interleaver 1I and demultiplexing are separated the second group system convolution code check bit of canceller output are input to decoder 2T, by this process data remaining decoder of process and interleaver, the output of last decoder NT is input to iteration and stops detector NM and deinterleaver 1J, 2J, the output of deinterleaver 1J is as the input of next iteration decoder 1M, and the output that all iteration stop detector is input to and door 1;
3). as I＜I
MinOr I
Min＜I＜I
MixThe time, I add 1 and return the 2nd the step;
4). work as I=I
MinThe time, judge with door 1 to be output as 1 or 0; If be 1, finish iterative decoding, and the output of deinterleaver 2J is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
Mix, finishing iterative decoding, and the output of deinterleaver 2J is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding;
Wherein, use I
MixThe maximum decoding iterations that representative allows is with the minimum decoding iterations of Imin representative permission.
6. adaptive iteration decoding scheme according to claim 4 is characterized by also and can be made of the following step:
1). will decipher iteration count I and be initialized as 1;
2). the data that will receive from channel are conciliate canceller 1X to demultiplexing and be carried out demultiplexing (demultiplex) and conciliate deletion (depuncture), the data of corresponding convolution code check bit in the dateout and systematic code data are input to decoder 1T decipher; The output of decoder 1T is input to deinterleaver 1J and iteration stops detector 1M; The output of deinterleaver 1J is input to demultiplexing and separates canceller 2X, its output is input to decoder 2T, the output of decoder 2T is input to iteration and stops detector 2M and interleaver 1I, the output of interleaver 1I is as the input of next iteration decoder 1M, and the output that all iteration stop detector is input to and door 1;
3). as I＜I
MinOr I
Min＜I＜I
MaxThe time, I add 1 and return the 2nd the step;
4). work as I=I
MinThe time, judge with door 1 to be output as 1 or 0; If be 1, finish iterative decoding, and the output of deinterleaver 2J is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
Max, finishing iterative decoding, and the output of deinterleaver 2J is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding;
In the above-mentioned steps, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
7. adaptive iteration decoding scheme according to claim 4 is characterized by also and can be made of the following step:
1). will decipher iteration count I and be initialized as 1;
2). the input data are deciphered;
3). as I＜I
MinThe time, I add 1 and return the 2nd the step;
4). work as I
Min≤ I＜I
MaxThe time, judge with door 1 to be output as 1 or 0; If be 1, finish iterative decoding, and the output of deinterleaver 2J is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding; Otherwise I add 1 and return the 2nd the step;
5). work as I=I
MaxThe time, finishing iterative decoding, and the output of deinterleaver 2J is input to the hard decision device these frame data, the hard decision device is output as the output of final decoding;
Wherein, use I
MaxThe maximum decoding iterations that representative allows is used I
MinThe minimum decoding iterations that representative allows.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306713C (en) * | 2002-12-10 | 2007-03-21 | 三星电子株式会社 | Error correction in CDMA mobile communication system using turbo codes |
| CN100369403C (en) * | 2006-02-20 | 2008-02-13 | 东南大学 | Parallel realizing method accepted by iterative detection decoding of wireless communication system |
| CN106533453A (en) * | 2015-09-15 | 2017-03-22 | 中兴通讯股份有限公司 | Decoding method and decoder |
| CN108011640A (en) * | 2016-11-01 | 2018-05-08 | 中国科学院沈阳自动化研究所 | One kind is used for the universal method of (2,1, N) convolutional encoding |
-
2001
- 2001-08-28 CN CNB011308532A patent/CN1175580C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306713C (en) * | 2002-12-10 | 2007-03-21 | 三星电子株式会社 | Error correction in CDMA mobile communication system using turbo codes |
| CN100369403C (en) * | 2006-02-20 | 2008-02-13 | 东南大学 | Parallel realizing method accepted by iterative detection decoding of wireless communication system |
| CN106533453A (en) * | 2015-09-15 | 2017-03-22 | 中兴通讯股份有限公司 | Decoding method and decoder |
| CN106533453B (en) * | 2015-09-15 | 2020-12-22 | 上海中兴软件有限责任公司 | Decoding method and decoder |
| CN108011640A (en) * | 2016-11-01 | 2018-05-08 | 中国科学院沈阳自动化研究所 | One kind is used for the universal method of (2,1, N) convolutional encoding |
| CN108011640B (en) * | 2016-11-01 | 2021-01-12 | 中国科学院沈阳自动化研究所 | General method for (2,1, N) convolutional coding |
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