CN100542050C - A kind of method for designing that has adaptivity and high speed turbo decoder - Google Patents

Abstract

The present invention relates to the turbo decoding technique, specifically a kind of method for designing that has adaptivity and high speed turbo decoder.It is that Frame is divided into several segments, introduce a plurality of local MAP decoders concurrently to reduce the time delay that produces by the Frame scale, and then reduce the time delay of whole turbo decoder, reducing aspect the delay that produces because of iteration, the invention provides based on the local iteration of local MAP decoder and calculate method of shutting down; Two kinds of local turbo decoding policies and highly-parallel structure are combined, make up and to have (be at least in theory almost be arbitrarily at a high speed) the high speed turbo decoder design method that postpones between atomic hour; Stop based on local MAP decoding and local iterative computation,, make up the turbo coding/decoding method and the architectural schemes that have adaptivity, have maximum flexibility in conjunction with various traditional ARQ methods.

Description

A kind of method for designing that has adaptivity and high speed turbo decoder

Technical field

The present invention relates to the turbo decoding technique, specifically a kind of method for designing that has adaptivity and high speed turbo decoder, wherein mainly comprise local MAP algorithm (also claiming local bcjr algorithm), high speed MAP algorithm, high speed turbo algorithm, have the turbo algorithm of adaptivity, and the architectural schemes of these decoder design realizations, the proposition of these algorithms and scheme is based on theoretical proof and simulating, verifying.

Background technology

The development of digital communication technology requires more and more higher data transmission rate and transmission speed, thereby needs transmitting and receiving apparatus at a high speed, and is particularly outstanding to the requirement of high speed algorithm and high speed framework aspect; Coding and decoding technology is as one of core part of digital communication technology, be one of indispensable means of correcting data error and transmission quality assurance, it also is one of the challenging key component that possesses skills most, from theoretical side, coding and decoding technology is to level off to the concrete constructive method of the Shannon limit of being established in the information theory most effectively, different because of the foundation of structural theory and range of application, and many different coding methods and coding/decoding method are arranged, wherein convolution code and turbo sign indicating number are one of coding techniquess that is most widely used, be widely used in all kinds of wired and wireless telecommunication systems, comprise 2G, 2.5G, 3G and the 4G system of advising, the Viterbi algorithm is as the optimal sequence coding/decoding method of convolution code, be widely used for three more than ten years, and the turbo sign indicating number to be 93 years important method with revolutionary contribution in France invention (please be entitled as Near Shannon limit error-correcting coding and decoding:Turbocodes referring to people such as C.Berrou, IEEE Int.Conf.On Comm., pp 1064-1070, May, 1993 original article), turbo Code And Decode method approaches the performance performance of the Shannon limit with it, become one of most important result on the communication history, this method and design are promptly applied among many communication systems.

Various high speed decoders be designed in recent years very active field, the research of the High Speed Viterbi decoder relevant with the present invention is very active in the 1980s, focus mainly concentrated on parallel processing and the architecture design aspect to the decoder trellis state at that time, the then rise of breakthrough on the algorithm and turbo coding/decoding method for want of and rarer people sets foot in recent years, it is that the stage of this direction is summed up that G.Fettweis and H.Meyr are published in article that IEEE Communications Magazine magazine in May, 1991 version 46-55 page or leaf is entitled as High speedparallel Viterbi decoding:algorithm and VLSI architecture; Work about the aspect of high speed turbo decoder, then work as referring to following article: (1) P.Beerel and K.Chugg, A low latency SISO with application tobroadband turbo decoding, IEEE JSAC Vol.19, No 5, May 2001, pp860-870, (2) A.Worm, H.Lamm and N.When, VLSI architectures for high-speed MAPdecoders, Proceedings on Design, Automation and Test in Europe, 2001, pp258-265, (3) J.Hagenauer, M.Moerz and A.Schaefer, Analog decodersand receivers for high speed applications, Proceedings of 2002International Zurich Seminar on Broadband Communications, February19-21, Zurich, Switzerland, pp3-1-3-8; In general, the design of high speed decoder can be divided into three interdependent piths: algorithm research, architecture design, hardware is realized, wherein: the research work of hardware realization aspect mainly concentrates on analog line and realizes the high speed logic computing, J.Hagenauer, M.Moerz and A.Schaefer are published in Proceedings of 2002 International ZurichSeminar on Broadband Communications (February 19-21, Zurich, Switzerland, the article that is entitled as Analog decoders and receivers for high speedapplications pp3-1-3-8) is this representative summation on the one hand; Aspect architecture design and the work of hardware realization aspect mainly concentrate on the effective architecture design and the optimization of decoder, the work of this respect is mainly carried out in the design process of decoder product, can be with reference to the description of product and the design summary of many companies; For introducing the present invention better, at first enumerate several pieces of main lists of references as the starting point of further explaining, ABC about Viterbi decoding algorithm and digital communication system, at the monograph Principles of Viterbi and Omura of digital communication and coding (McGraw-Hill, detailed introduction is arranged 1979), then be entitled as Viterbi decoding algorithm for convolutionalcodes with repeat request (IEEE Trans.Info.Theory as the Yamamoto-Itoh index of Viterbi decoding application technology important supplement at Yamamoto and Itoh, Vol 26, No 5, pp540-547,1980) in the original papers detailed description is arranged; As the convolution code MAP decoding algorithm that has better performance than Viterbi decoding (initials that also can the author and be called as bcjr algorithm) with minimal information bit error probability, then see also people's such as L.Bahl article Optimal decoding oflinear codes for minimizing symbol error rate (IEEE Trans.Info.Theory, Vol 20, pp284-287, March, 1974), this a kind of decoding algorithm basis that is the turbo decoder; For clean cut system Viterbi algorithm very commonly used in engineering design, then can be referring to the monograph of above-mentioned Viterbi and Omura or the paper of G.Fettweis and H.Meyr, this important realization skill and (being mainly used in MAP decoder and the further turbo decoder) window algorithm that on this basis, further develops, be in order to reduce the very important use algorithm of decoder design required memory, this list of references on the one hand is mainly three pieces of following papers: (1) A.Viterbi, An intuitivejustification and a simplification of a simplified implementation of theMAP decoder for convolutional codes, IEEE JSAC Vol 16, No 2, pp260-264, February, 1998, (2) S.Benedetto et al, Soft input soft output MAP moduleto decode parallel and serial concatenated codes, TDA Progress Report42-127, JPL, 1996, (3) S.Pietrobon, Efficient implementation ofcontinuous MAP decoders and a synchronization technique for turbodecoders, pp586-589, Proc.Int.Sym.Inform.Theory Appl., Victoria, B.C.Canada, 1996, closely-related with high speed turbo coding/decoding method is the high-speed LDPC coding/decoding method, about this situation on the one hand please referring to the article A 690-mW 1-Gb/s1024-b of A.Blansky and C.Howland, rate-1/2 low-density code decoder, IEEE Journal of Solid-stateCircuits, Vol.37, No.3,2002, pp404-412 and wherein listed document, the research of this coding/decoding method is a very active in recent years association area, aspect commercial decoder design, Flarion company has the digit rate of now having put on market to reach the high-speed LDPC decoder design of 10Gbps, can do the reference of this respect design.

The design of high speed turbo decoder is the essential and guardian technique difficult problem of modern communication systems, especially because the turbo sign indicating number mainly is to be used for high-speed data transmission, therefore the design of high speed turbo decoding becomes in recent years very active research field, the design of high speed turbo decoder is divided into three interdependent piths: algorithm design, architecture design, hardware is realized, wherein: mainly concentrate on analog line realization high speed logic computing aspect in the work aspect the hardware realization, above-mentioned J.Hagenauer, the article of M.Moerz and A.Schaefer is the representational summation of this respect, utilizes existing circuit technology can design the turbo decoder that output rating reaches 10Gbps; Work aspect framework mainly concentrates on effective architecture design of the key components MAP decoder of turbo decoder, original framework technology can be designed the high speed turbo decoder that effective output rating reaches 54Gbps, the work of this respect sees also above-mentioned (1) P.Beerel and K.Chugg, (2) A.Worm, H.Lamm and N.When, (3) J.Hagenauer, people's such as M.Moerz and A.Schaefer article and institute's quoted passage are offered; Work at the algorithm face is the emphasis of high speed turbo decoder research, the work in past mainly concentrates on parser and optimized Algorithm aspect, because on the problem aspect turbo sign indicating number theory and the turbo decoding algorithm convergence, still lack satisfactory answer at present, aspect theoretical, also await further analyzing, thereby still there be not " optimization " now (before turbo decoding convergence thoroughly solves, the discussion of optimal algorithm is not very clear and definite) the turbo decoding algorithm, and the work of architecture design and hardware realization aspect none be not to be subjected to the restriction of algorithm and to define; Above summation has been summarized substantially in high speed turbo high speed decoder design aspect technology situation roughly.

Summary of the invention

For overcoming algorithm deficiency and the speed limit in the existing high speed turbo decoder design technology, the object of the invention provides a kind of method for designing that has adaptivity and turbo decoder at a high speed, it is a kind of brand-new high speed MAP decoding algorithm and then high speed turbo decoding algorithm and framework implementation based on local MAP decoder, algorithm foundation of the present invention is local MAP decoding algorithm, the framework foundation then is the parallel placement of local MAP decoder, to realize the design of high speed MAP decoder and then high speed turbo decoder; On the basis of local MAP decoder,, then can obtain having the turbo decoding algorithm and the decoder design that have adaptivity in conjunction with the ARQ method (being included in the new A RQ method of being set up in the turbo decoding that is similar to traditional Yamamoto-Itoh index) and the local iteration stopping method of each quasi-tradition.

To achieve these goals, technical solution of the present invention is as follows:

The method for designing that has the turbo decoder of adaptivity: based on local MAP decoder technique, adopt bilateral window, in conjunction with the ARQ scheme that comprises Yamamoto-Itoh type index,, make it possess the ability of adaptive channel signal attenuation to improve the quality of turbo decoding; Wherein comprise two same compositions the MAP decoder that has adaptivity, have adaptivity turbo decoder control system, have the turbo decoder of adaptivity data turnover system, have the external interface of the turbo decoder of adaptivity; (separate by staggered (turbointerleaver) and reciprocal cross mistake (turbo deinterleaver) respectively between the MAP decoder that has adaptivity of described two same compositions, it is input as data sampling, external information and LLR value, is output as to feed back to LLR value and the external information that next composition has adaptivity MAP decoder);

The described MAP decoder that has adaptivity comprises M local MAP decoder, M data segment corresponding to Frame, in the average SNR estimated value of this corresponding data segment or the ARQ scheme index that comprises Yamamoto-Itoh type index during less than given threshold value, the sampling of described part can be resend, and promptly realizes adaptivity;

The branch road scheme module that all has described each local MAP decoder decides this part MAP decoder whether should avoid decoding and directly enters sleep state (a local MAP decoder of having slept keeps sleep state in remaining interative computation), promptly calculate hard or soft local virtual SNR value or quality index with LLR value and external information, check whether local quality index or virtual SNR surpass certain threshold value or arrived at asymptotic behaviour, if local quality index or virtual SNR passing threshold or asymptotic check, then branch road should part MAP decoder, otherwise move local MAP decoder, (" branch road " is so expression output LLR value and external information value should be to import the computing of need not decoding of LLR and external information value), when a certain local MAP decoder during, promptly enter sleep state by branch road; When all local MAP decoders all enter sleep state, then finish the turbo decode procedure that has adaptivity;

The described turbo decoder control system that has adaptivity is to be used to control, coordinate and to dispatch whole each part and its function that has the turbo decoder of adaptivity, and M local MAP decoder all had an independently control system; The described data turnover system that has the turbo decoder of adaptivity is used to control, the turnover of coordination data, and each local MAP decoder all has a data turnover system; The described external interface that has the turbo decoder of adaptivity is used for being connected and communication of this decoder and interior other parts of communication system, and each local MAP decoder all has and outside communication system;

The size of supposing to comprise the decoded Frame of tail position is L, use M local MAP decoder, the MAP decoding method for designing of described band adaptivity is as follows: the MAP decoder that 1) has adaptivity comprises M the data segment of M local MAP decoder corresponding to whole Frame, supposes the big or small long enough of bilateral window; 2) data segment that will have bad SNR value is given up the MAP decoding that is used to have adaptivity with the various ARQ schemes of transmission again, if the average SNR value of a data segment is lower than certain threshold value, then can give up this data segment and require transmission again, if can before local MAP decoding, can estimate that its average SNR value and its SNR value are lower than the threshold value that sets, can not need move this part MAP decoder, directly skip this data segment and directly requirement transmission again; 3) the local ARQ scheme of using Yamamoto-Itoh type index can be used to have among the MAP coding/decoding method of adaptivity, if Yamamoto-Itoh type desired value is lower than certain threshold value on the data segment, then can give up this data segment and require transmission again, if can before local MAP decoding, can estimate Yamamoto-Itoh type desired value and be lower than the threshold value that sets, can not move this part MAP decoder, directly skip this data segment and directly requirement transmission again;

The size of supposing to comprise the decoded Frame of tail position is L, uses M local MAP decoder; Described local MAP decoding method for designing: 1) if i=1 uses sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation forward based on butterfly structure, with sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, to information data bit { x ₀, x ₁..., x _M-1Carry out the MAP decoding, export the LLR value; 2) if i=N-1 or i=N use sampling { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sampling startup, to data bit { x based on butterfly structure _L-2M, x _L-M+1..., x _L-1Carry out MAP decoding, output LLR value because the identical starting point of recurrence is backward arranged, overlaps two kinds of situations, and the calculating repetition of latter two window (promptly latter two window decode simultaneously) is arranged; 3) if 1＜i＜N-1 uses sampling { ξ _{2 (i-1) M}, ξ _{2 (i-1) M+1}..., ξ _{2 (i+2) M-2}, ξ _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sampling startup based on butterfly structure, output LLR value is to data bit { x _IM, x _IM+1..., x _{(i+1) M-1}Decode and carry out the MAP decoding;

In the described local MAP decoding method for designing: 1) if i=1 uses sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation forward based on butterfly structure, and the initial value setting is with a (0)=1 and a (i)=0, and i ≠ 0 is good; With sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, be provided with initial value with $b_i=\frac{1}{N_{\mathrm{state}}}$ For good; 2) if i=N-1 or i=N use sampling { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, and it is good that initial value evenly is set, and with the backward recursive calculation of same sampling startup based on butterfly structure, initial value is set b (0)=1 and b (i)=0, and i ≠ 0 is good; 3) if 1＜i＜N-1 uses sampling { ξ _{2 (i-1) M}, ξ _{2 (i-1) M+1}..., ξ _{2 (i+2) M-2}, ξ _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, and it is good that initial value evenly is set, with the backward recursive calculation of same sampling startup based on butterfly structure, it is good that initial value evenly is set.

The method for designing of high speed turbo decoder: with local MAP decoding algorithm is foundation, parallel placement by local MAP decoder comes the framework foundation, on the basis of local MAP decoder, adopt bilateral window, combination to comprise the ARQ method and the local iteration stopping method of Yamamoto-Itoh type index, form the speed of MAP decoder with raising, and then improve the speed of whole turbo decoder; Wherein: comprise high speed MAP decoder, the high speed turbo decoder control system of two same compositions, the data turnover system of high speed turbo decoder, the external interface of high speed turbo decoder; (the high speed MAP decoder of two same compositions is separated by staggered (turbo interleaver) and reciprocal cross mistake (turbo deinterleaver), to the soft sampling of the input of each high speed MAP, external information and LLR value, each high speed MAP decoder is output as and feeds back to next LLR value and the external information of forming high MAP decoder);

Described each high speed MAP decoder comprises the parallel work-flow corresponding to M local MAP decoder of M data segment of whole Frame (pressing the frame that original time sequence arrangement or the time sequencing after de-interleaver are arranged);

Described each local MAP decoder all has a decoding branch road scheme to confirm whether local MAP decoder should enter sleep state, promptly calculate corresponding hard or soft virtual SNR value or quality index with input LLR value and external information, check whether virtual SNR value or local product index surpass threshold value or arrived at asymptotic behaviour, if approximate SNR value or quality index surpass the check threshold value or have arrived at asymptotic behaviour, the local MAP decoder of branch road, otherwise move this part MAP decoder and decode that (" branch road " expression here directly will import LLR value and external information value as exporting LLR value and external information value in computing, and the computing of not decoding), when local MAP decoder enters sleep state during by branch road, can not activate one at next iteration cycle and enter dormant local MAP decoder, each forms the number that has entered dormant local MAP decoder in the high speed MAP decoder can constantly increase along with iteration, after all local MAP decoders enter sleep state, iteration stopping and finished high speed turbo decode procedure;

Described high speed turbo decoder control system is used to control, coordinate and dispatch each part and its various functions of whole high speed turbo decoder, and M local MAP decoder all had an independently control system; The data turnover system of described high speed turbo decoder is used to control, the turnover of coordination data, and each local MAP decoder all has a data turnover system; The external interface of described high speed turbo decoder is used for being connected and communication of this decoder and interior other parts of communication system, and each local MAP decoder all has and outside communication system;

The decoded data frame length of supposing to comprise the tail bit is L, with M local MAP decoder, described high speed MAP decoding method for designing is: 1) high speed MAP decoder comprises M the data segment that M local MAP decoder corresponds to whole Frame, supposes that wherein the size of all bilateral windows is equal to and the size long enough; 2) the local MAP decoder of the M in the parallel work-flow high speed MAP decoder carries out local MAP decoding respectively to M data segment of whole Frame, and these computings are when parallel processing as far as possible (yes sampling situation about having possessed under); 3) can be in conjunction with the MAP decoder that has adaptivity in high speed MAP decoder, i.e. design according to high speed MAP decoder is used in combination the ARQ scheme; The various ARQ schemes that data segment with bad SNR value can be given up and transmit again are used to have the MAP decoding of adaptivity, if the average SNR value of a data segment is lower than certain threshold value, then can give up this data segment and require transmission again, if can before local MAP decoding, can estimate that its average SNR value and its SNR value are lower than the threshold value that sets, just can not need move this part MAP decoder, directly skip this data segment and directly requirement transmission again; This is based on the MAP decoding that has adaptivity of local ARQ scheme and local MAP decoder; 4) the local ARQ scheme of using Yamamoto-Itoh type index can be used among the MAP coding/decoding method that has adaptivity based on local MAP decoder, if the minimum Yamamoto-Itoh type index on data segment is lower than certain threshold value, then can gives up this data segment and require and resend; 5) decoding speed of high speed MAP decoder is by the degree of concurrence decision of local MAP decoder, if the whole parallel processings of all local MAP decoders, then high speed MAP decoder has the highest speed of service, if all local MAP decoders are serial process one by one all, then high speed MAP decoder has the minimum speed of service;

Below be the extreme case of two designs: if use L local MAP decoder (promptly each sample all being set up a local MAP decoder) and all parallel processings, then obtain possible maximum speed MAP decoding, if use a local MAP decoder (promptly not adopting window algorithm fully), then be the slowest traditional MAP coding/decoding method;

Described local MAP decoding method for designing: 1) if i=1 uses sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start the meter of recurrence forward based on butterfly structure, with sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, to information data bit { x ₀, x ₁..., x _M-1Carry out the MAP decoding, export the LLR value; 2) if i=N-1 or i=N use sampling { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sampling startup, to data bit { x based on butterfly structure _L-2M, x _L-M+1..., x _L-1Carry out MAP decoding, output LLR value because the identical starting point of recurrence is backward arranged, overlaps two kinds of situations, and the calculating repetition of latter two window (promptly latter two window decode simultaneously) is arranged; 3) if 1＜i＜N-1 uses sampling { ξ _{2 (i-1) M}, ξ _{2 (i-1) M+1}..., ξ _{2 (i+2) M-2}, ξ _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sampling startup based on butterfly structure, output LLR value is to data bit { x _IM, x _IM+1..., x _{(i+1) M-1}Decode and carry out the MAP decoding;

In the described local MAP decoding method for designing: 1) if i=1 uses sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation forward based on butterfly structure, and initial value is with a (0)=1 and a (i)=0, and i ≠ 0 is good; With sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, initial value is set $b_i=\frac{1}{N_{\mathrm{state}}}$ For good; 2) if i=N-1 or i=N use sampling { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, and it is good that initial value evenly is set, and with the backward recursive calculation of same sampling startup based on butterfly structure, initial value is set with b (0)=1 and b (i)=0, and i ≠ 0 is good; 3) if 1＜i＜N-1 uses sampling { ξ _{2 (i-1) M}, ξ _{2 (i-1) M+1}..., ξ _{2 (i+2) M-2}, ξ _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, and it is good that initial value evenly is set, with the backward recursive calculation of same sampling startup based on butterfly structure, it is good that initial value evenly is set.

Compared with prior art the present invention has more following beneficial effect:

The present invention has found local MAP coding/decoding method (specific implementation of this algorithm is called as local MAP decoder), and invented on this basis that can to design be in theory almost to be the high speed MAP decoding algorithm and the architecture design scheme of arbitrary speed at least, compare with the method that must start anew to decode one by one according to the time sequencing of sampling originally, the local MAP decoder of the present invention can utilize the window algorithm after the improvement, any a part of sample (being fractional sample) is carried out the MAP decoding, this local MAP decoding algorithm is former non-existent method, this method be to prior art mentioned for saving the substantial improvements and the whole new set of applications (not merely being) of the monolateral window algorithm that internal memory foundes in order to save internal memory, the parallel arranged of local MAP decoder, it promptly is the basis of high speed MAP decoder design method, because each local MAP decoder even can be designed to only be used for handling an information bit position, therefore the present invention provides to design has the high speed MAP coding/decoding method with set time delay irrelevant with the message transmission digit rate, thereby the invention provides that can to reach be in theory almost to be the high speed MAP coding/decoding method of arbitrary speed at least, and the combination in any of two local MAP decoders that are connected and cut apart character, then provided with traditional MAP coding/decoding method compatibility, to the highest MAP decoder design method, these have then showed harmony and aesthetic feeling in the high speed MAP decoding design to decoding speed from minimum; The present invention is based on high speed MAP decoder, high speed turbo decoder be designed to easy to do work because the turbo decoding serial arrangement of a series of MAP decoder only in itself, that is to say the repeated use of two MAP decodings that are connected; In addition, also provide as the local MAP decoder of this invention core and to have had the MAP decoder design method local solution code function, that have adaptivity, this class decoder did not exist in the past, and new method not only can compatible traditional ARQ scheme based on Yamamoto-Itoh type index, and can utilize the various ARQ schemes of decoding based on local MAP, the present invention also can be on the basis in conjunction with local turbo iteration stopping algorithm, the turbo decoder that has maximum adaptivity that design has the partial operation function; Wherein need what is particularly worth mentioning is that: the local MAP decoder that the present invention utilized can be used to the local iteration stopping method of combination in the turbo decoding that has adaptivity (this is a kind of new iteration stopping method, proposed first in the present invention), when a local MAP decoder stops in the turbo iteration, then in iteration hereafter, will be stopped forever, the present invention claims this part MAP decoder to enter sleep state, and the introducing of the local MAP decoder of this sleep state makes turbo coding/decoding method provided by the present invention have the adaptivity and the control flexibility of maximum possible.

Description of drawings

Fig. 1 is the schematic diagram of the local MAP decoder of the present invention.

Fig. 2 is the schematic diagram that the present invention has adaptivity turbo decoding.

Fig. 3 is that the present invention has the schematic diagram that adaptivity is formed the MAP decoder.

Fig. 4 is the schematic diagram that the local MAP decoder of the present invention props up dataway operation.

Fig. 5 is local MAP (BCJR) decoder of a high-speed parallel of the present invention schematic diagram.

Fig. 6 is the local MAP decoder of a present invention time series decomposing schematic representation.

Fig. 7 is the local MAP decoder states of a present invention room and time sequence decomposing schematic representation.

Fig. 8-the 1st, the performance performance figure of the parallel local max* decoding algorithm of the present invention.

Fig. 8-the 2nd, the performance performance figure of the parallel local max decoding algorithm of the present invention.

Embodiment

The invention will be further described below by accompanying drawing.

Modern data network for broadband connections and high amount of traffic amount, must design corresponding high speed decoder carries out correcting data error and guarantees the data information transmission quality, at the high speed decoder design field a large amount of research and design work have been arranged, especially at the design aspect of Viterbi with very extensive use and turbo decoder, here only list the design example that some are known, so as to causing further discussion to high speed turbo decoder; At first for high speed turbo decoder design, worked in the past and mainly concentrate on the architecture aspect and realize that the improvement aspect is (please referring to above-mentioned A.Worm, H.Lamm andN.When and J.Hagenauer, people's such as M.Moerz and A.Schaefer article), based on realizing that with analog line the turbo decoder digit rate of high speed logic computing can reach the flow of 10Gbps, adopt the architecture conscientiously optimized and can reach the flow of 300Mbps based on the turbo decoder of MAP algorithm through rigorous design, with regard to the key technology details aspect that realizes the turbo decoder, the window technique that is used for the ACS butterfly computation that the decoder trellis state handles and is used to reduce the decoder required memory by emphatically and research in depth (please referring to above-mentioned (1) A.Viterbi, (2) S.Benedetto etal, (3) people's such as S.Pietrobon article), especially vitally in the MAP decoder design be used to reduce the window technique of turbo decoder stores (for the method that above document provided, the present invention's system is referred to as monolateral window technique), the development of advancing of these technology then is the bilateral window technique that the author introduced, and local MAP coding/decoding method of on this basis, inventing and local MAP decoder design, it is that speed is almost high MAP decoder and turbo decoder arbitrarily in theory at least that the parallel arranged of this local MAP decoder then obtains the present invention; In addition, the turbo decoder that has adaptivity can be set up on the basis that stops algorithm, all kinds of ARQ schemes in conjunction with local turbo decoder, all kinds of local iteration, and this also is an important content of the present invention; A kind of new algorithm that has approximate error (error is controlled by window size) of the MAP of being used for decoding will be proposed below the present invention, the local solution code method is used to make up the turbo decoder that has adaptivity at first, unexpectedly, with some local decoder parallel arranged, then can construct at a high speed and have the turbo decoder of adaptivity.

Under the prerequisite that is without loss of generality, the present invention supposes that code check r is 1/2, S _TotalBe the whole status numbers of network of decoding accordingly, the size that is used for the Frame of convolution coder is L, supposes that in addition encoder starts and finish (suitable tail bit) in nought state, suppose in addition $M={\left\{m_i\right\}}_{i=0}^{L-1}$ Be the information bit bit stream that has sent, convolution coder is output as $X={\{x_i,p_i\}}_{i=0}^{L-1}$ (obvious x _i=m _iSet up for the system type coding), employing BPSK is modulated at noise variance and is ${\mathrm{\σ}}^2=\frac{N_0}{2}$ Awgn channel on send, receive sampled value and be $Y={\{y_i,t_i\}}_{i=0}^{L-1},$ Wherein $y_i=x_i\sqrt{E_b}+n_i,$ $t_i=p_i\sqrt{E_b}+n_i^{\′},$ Polarity is 0 →+1 and 1 →-1, and case of external information list entries is Z={z ₀, z ₁..., z _L-1, wherein $z_i=\log \frac{p(m_i=+1)}{p(m_i=-1)},$ Thereby have $p\left[m_i\right]=\frac{e^{m_i{z}_i/2}}{e^{-z_i/2}+e^{z_i/2}},$ m _i=± 1; A kind of local MAP coding/decoding method proposed by the invention, can be used to make up have an adaptivity or high speed MAP decoder and turbo decoder, decode for high speed turbo, the present invention relies on the parallel method (mainly being the parallel processing to each Frame section) of height to improve the speed of forming the MAP decoder, and then improve the speed of whole turbo decoder, if ignore the realization cost, this scheme is can design in theory greatly to almost being any high-speed high speed turbo decoder really at least, turbo coding/decoding method for the band adaptivity, the present invention then is based on and uses local MAP decoder technique, in conjunction with the various traditional ARQ scheme that comprises the Yamamoto-Itoh index, these schemes can make the present invention give up the data segment that has bad SNR value fully, and utilize the ARQ scheme to resend bad data segment, so as to improving the quality of turbo decoding, this scheme flexibly makes the turbo decoder can possess the ability of adaptive channel signal attenuation, this specific character thereby be called as adaptivity.Aspect realization, the measurement index of realizing cost mainly comprises silicon area and power consumption, because aspect algorithm, as long as enough big window is arranged, the local MAP algorithm of the present invention (essence is a kind of progressive approximate data) just has the performance that almost is tantamount to perfect condition MAP algorithm, and the parallel placement of local MAP decoder, obviously be parallel algorithm and architectural approach, thereby can't have a strong impact on the performance performance of MAP decoder, also can seriously not reduce the performance performance of turbo decoder, the present invention has also provided the notional result of following verification algorithm and numerical simulation result so that further confirm and illustrate the present invention.

Some notional result, SNR and virtual SNR calculate:

Make S _iBe state corresponding to the decoding network of i-th information bit timeslice, below the MAP decoding is based in the prior art forward and backward the information bit of the optimum of recurrence formula information bit is detected:

$\left(1\right),\mathrm{\α}\left(S_i\right)=\underset{S_{i-1}}{\mathrm{\Σ}}\mathrm{\α}\left(S_{i-1}\right)\mathrm{\γ}(S_{i-1}\→S_i),$ α(S ₀)＝1，S ₀＝0，α(S ₀)＝0，S ₀≠0，

$\left(2\right),\mathrm{\β}\left(S_i\right)=\underset{S_{i+1}}{\mathrm{\Σ}}\mathrm{\β}\left(S_{i+1}\right)\mathrm{\γ}(S_i\→S_{i+1}),$ β(S _L)＝1，S _L＝0，α(S _L)＝0，S _L≠0，

Soft decision LLR value is calculated by the formula that is referred to below as the log-MAP algorithm:

$\left(3\right),L_i=\log \frac{p[m_i=+1|Y]}{p[m_i=-1|Y]}=\log \frac{\underset{S+}{\mathrm{\Σ}}\mathrm{\α}\left(S_i\right)\mathrm{\γ}(S_i\→S_{i+1})\mathrm{\β}\left(S_{i+1}\right)}{\underset{S-}{\mathrm{\Σ}}\mathrm{\α}\left(S_i\right)\mathrm{\γ}(S_i\→S_{i+1})\mathrm{\β}\left(S_{i+1}\right)},$

Following formula is called as the log-MAP algorithm in realization, wherein γ (S _i→ S _i) be branch metric; The ML algorithm is optimum on the continuous path of search the best; And the dynamic programming method that the Viterbi decoder utilizes when searching for optimal path on awgn channel effective path to cut down: ACS operate (add, compare and select), on mathematics, supposes based on the sample that i.i.d distributes, $X=\arg \left\{\underset{X}{\max }p\right[Y\left|X\right]\},$ And have:

$p\left[Y\right|X\}=\underset{i=0}{\overset{L-1}{\mathrm{\Π}}}p[y_i\left|x_i\right]p\left[t_i\right|p_i]={\left(\frac{1}{\sqrt{2\mathrm{\π}}\mathrm{\σ}}\right)}^{2L}{e}^{-\frac{1}{2{\mathrm{\σ}}^2}\underset{i=0}{\overset{L-1}{\mathrm{\Σ}}}\{{(x_i-y_i)}^2+{(p_i-t_i)}^2\}},$

Optimal path has the minimum value of Euclidean distance square, has the maximal correlation path metric in other words, the adeditive attribute of associated pathway tolerance and corresponding network provide butterfly structure efficiently for the ACS computing, the individual path that this structure has reduced when associated pathway tolerance is upgraded effectively calculates, thereby improved the computational efficiency of Viterbi decoder largely, yet analysis result of the present invention: Viterbi decoding has parallel with the MAP decoding forward following and recursive sequence backward:

$\left(4\right),{\mathrm{\α}}^{*}\left(S_i\right)={\max }_{S_{i-1}}\left\{{\mathrm{\α}}^{*}\left(S_{i-1}\right)\mathrm{\γ}(S_{i-1}\→S_i)\right\},$ α ^*(S ₀)＝1，S ₀＝0，α ^*(S ₀)＝0，S ₀≠0，

$\left(5\right),{\mathrm{\β}}^{*}\left(S_i\right)={\max }_{S_{i+1}}\left\{{\mathrm{\β}}^{*}\left(S_{i+1}\right)\mathrm{\γ}(S_i\→S_{i+1})\right\},$ β ^*(S _L)＝1，S _L＝0，β ^*(S _L)＝0，S _L≠0，

(sequence can be regarded simply as the Viterbi decoder is moving on opposite time orientation backward to be actually another kind of different explanation to the Viterbi coding/decoding method with recursive sequence backward forward, or the decoding forward after the sample that receives a whole frame), soft decision LLR value is calculated by following formula:

$\left(6\right),L_i^{*}=\log \frac{\underset{S+}{\mathrm{\Σ}}{\mathrm{\α}}^{*}\left(S_i\right)\mathrm{\γ}(S_i\→S_{i+1}){\mathrm{\β}}^{*}\left(S_{i+1}\right)}{\underset{S-}{\mathrm{\Σ}}{\mathrm{\α}}^{*}\left(S_i\right)\mathrm{\γ}(S_i\→S_{i+1}){\mathrm{\β}}^{*}\left(S_{i+1}\right)},$

Following formula is called as the max-log-MAP algorithm in realization.

As mentioned above, key of the present invention and essential technique are local MAP decoder algorithm and strategy, it is further developing and improving famous sliding window technique, key breakthrough point is for to be revised as bilateral window technique with original monolateral window technique, and be to reduce technology that Viterbi decoder and MAP decoder (and then turbo decoder) internal memory found to be applied to local MAP decoding originally with this, and then apply it to high speed MAP decoder, and make up in the middle of the design of the MAP decoder that has adaptivity in conjunction with various traditional ARQ schemes, the SNR correlation of the traceback length of bilateral window algorithm (comprise according to intuition and propose and be the monolateral window algorithm of experimental verification) and intercepted Viterbi decoder (the most original monolateral window algorithm) is proved by inventor's notional result, content mainly is briefly to enumerate relevant notional result below the present invention, algorithm and architectural schemes are as the guide of actual decoder engineering design;

The theoretical proof of Viterbi decoding window algorithm:

For Viterbi decoding, as at network { x _i, p _i, x _I+1, p _I+1..., x _I+W, p _I+WA last state of selecting at random begins to recall, traceback length is W, recalls the path to (i-1)-th position x _I-1The probability that does not give the incident E of identical position judgement satisfies following formula:

$\left(7\right),p\left(E\right)\≤N_{\mathrm{state}}\·Q\left(\sqrt{\frac{{\mathrm{WE}}_b}{{\mathrm{KN}}_0}}\right),$

N wherein _StateBe the sum of decoder network state number, K is the constraint length of decoder network, significantly, and lim _{W → ∞}P (E)=0;

The theoretical proof of log-MAP and max-log-MAP decoding window algorithm:

For window size is W, and intercepted log-MAP in two ends or max-log-MAP decoding then have:

$\left(8\right),E\left[\right|L_i-L_i^{\left(W\right)}\left|\right]\≤{\mathrm{Ce}}^{-W}[1+N_{\mathrm{total}}(2^{2W}-1)e^{-\frac{d_f{E}_b}{2{\mathrm{\σ}}^2}}],$

Wherein C is a constant, N _StateBe the sum of network state number, L _i ^(W)Be the LLR value that generates by window technique, significantly, ${\lim }_{W\→\∞}E\left[\right|L_i{-L}_i^{\left(W\right)}\left|\right]=0;$

These results show, Viterbi is decoded, (always set up under the non-vanishing situation of this power output that transmitting under at SNR greater than zero situation, otherwise there is not the discussion meaning), as long as traceback length long enough, by beginning to recall from free position, just can obtain good Viterbi decoding performance, the LLR value that promptly has an approximate Viterbi decoding of bilateral window levels off to the LLR value that desirable Viterbi decodes when window size levels off to infinity, so sliding window is opened greatly more, the performance of local Viterbi decoding is approaching more ideal just, and in other words, local Viterbi decoding algorithm is the coding/decoding method of asymptotic optimum; And for the MAP decoder, (always set up under the non-vanishing situation of this power output that transmitting under at SNR greater than zero situation, otherwise there is not the discussion meaning), similarly, the LLR value that has an approximate MAP decoding of bilateral window levels off to desirable MAP decoding LLR value when window size levels off to infinity, sliding window is opened greatly more, and the performance that local MAP decodes is with regard to approaching more ideal, thus, the local MAP decoding algorithm coding/decoding method that also is asymptotic optimum.

Adopt bilateral sliding window technique, the present invention can draw the local MAP decoder scheme that the back will be talked about, when designing and operating these decoders, also need to monitor and control the behavior of these decoders with some index, the chances are observes operating SNR (signal to noise ratio) value for the most direct monitoring method, thereby the present invention lists in the following prior art simple SNR method of estimation (please referring to the monograph Turbo codes of C.Heegard and S.Wicker, Kluwer Academic Press, 1999 and wherein listed document):

$\left(9\right),{\mathrm{\σ}}^2\≈{\left[\frac{1}{K}\underset{i=1}{\overset{K}{\mathrm{\Σ}}}(y_i+t_i+s_i)\right]}^2+\left[\frac{1}{K}\underset{i=1}{\overset{K}{\mathrm{\Σ}}}\right\{{(y_i-{\mathrm{\μ}}_0)}^2+{(t_i-{\mathrm{\μ}}_0)}^2+{(s_i-{\mathrm{\μ}}_0)}^2\left\}\right]-1,$

Wherein ${\mathrm{\μ}}_0=\frac{1}{3K}\underset{i=1}{\overset{K}{\mathrm{\Σ}}}(y_i+t_i+s_i),$ Estimate for symbol energy, can use:

$\left(10\right),E_s\≈\frac{1}{3K}\underset{i=0}{\overset{K-1}{\mathrm{\Σ}}}[y_i^2+t_i^2+s_i^2],$

$\left(11\right),E_s\≈{\left\{\frac{1}{3K}\underset{i=0}{\overset{K-1}{\mathrm{\Σ}}}\right[(y_i-{\mathrm{\μ}}_0)\mathrm{sign}\left(y_i\right)+(t_i-{\mathrm{\μ}}_0)\mathrm{sign}\left(t_i\right)+(s_i-{\mathrm{\μ}}_0)\mathrm{sign}\left(s_i\right)\left]\right\}}^2;$

Owing to the preliminary treatment that before the turbo decoding, needs to sample, various types of SNR methods of estimation are widely studied in the turbo decoding, the present invention at first quotes S.Pietrobon, Efficientimplementation of continuous MAP decoders and a synchronizationtechnique for turbo decoders, pp586-589, Proc.Int.Sym.Inform.TheoryAppl., Victoria, B.C.Canada, 1996, and T.Summers and G.Wilson, SNRmismatch and online estimation in turbo decoding, IEEE Trans.Comm., Vol46, No 4, pp421-423, result among the April 1998 understands problem of pretreatment better, and wherein, the LUT of the logarithm correction term in the MAP decoding is generated by following formula:

$\left(12\right),c\log (1+e^{-\frac{x}{c}}),$

Wherein c is by equation $c=\frac{A{\mathrm{\σ}}^2}{4}$ Provide, constant A is provided by following formula:

$\left(13\right),A=\frac{C^{*}(2^{q-1}-1)}{\mathrm{mag}\left(\mathrm{\σ}\right)},$

C wherein ^*=0.65, q is the bit value in the digital quantization scheme, and

$\left(14\right),\mathrm{mag}\left(\mathrm{\σ}\right)\≈\mathrm{\σ}\sqrt{\frac{2}{\mathrm{\π}}}\≈0.798\mathrm{\σ},$

So just can calculate the LUT of required logarithm correction term easily; Practical operation is assigned to each sampling of being divided by pre-reason value c just, and is clearly visible:

$\left(15\right),\frac{1}{c}=\frac{4*\mathrm{mag}\left(\mathrm{\σ}\right)}{0.65*(2^{q-1}-1)*{\mathrm{\σ}}^2}\≈\frac{4*0.798}{0.65*(2^{q-1}-1)*\mathrm{\σ}},$

Also can correspondingly design different approximate Preprocessing Algorithm; The article of S.Pietrobon that enumerates previously and T.Summers and S.Wilson has drawn the typical amount on the following soft sampling statistical significance:

(16)E(|ξ _i|)＝mag(σ)≈0.798σ，

(17)E(|ξ _i| ²)＝E+σ ²≈σ ²；

Article according to T.Summers and S.Wilson has again:

$\left(18\right),\frac{E\left(y_i^2\right)}{{\left[E\left(\right|y_i\left|\right)\right]}^2}=\frac{E\left(t_i^2\right)}{{\left[E\left(\right|t_i\left|\right)\right]}^2}=\frac{E\left(s_i^2\right)}{{\left[E\left(\right|s_i\left|\right)\right]}^2}=f\left(\frac{E_s}{{\mathrm{\σ}}^2}\right)=f\left(\mathrm{\β}\right),$

Wherein function f (β) is provided by following formula:

$\left(19\right),f\left(\mathrm{\β}\right)=\frac{1+\frac{E_s}{{\mathrm{\σ}}^2}}{{\{\sqrt{\frac{2}{\mathrm{\π}}}{e}^{-\frac{E_s}{2{\mathrm{\σ}}^2}}+\sqrt{\frac{E_s}{{\mathrm{\σ}}^2}}[\mathrm{erf}\left(\sqrt{\frac{E_s}{2{\mathrm{\σ}}^2}}\right)\left]\right\}}^2},$

$\mathrm{\β}=\frac{E_s}{{\mathrm{\σ}}^2}$ Expression SNR value; Utilize $z=\frac{E\left(y_i^2\right)}{{\left[E\left(\right|y_i\left|\right)\right]}^2}$ Mean value, according to the article of Summers and Wilson, can find required SNR value by following formula $\mathrm{\β}=\frac{E_s}{{\mathrm{\σ}}^2}$ Be approximately:

(20)β≈-34.0516z ²+65.9548z-23.6184；

The present invention now provides following result according to theory analysis: the turbo iteration can increase the corresponding SNR operating value of decoder (the present invention is referred to as virtual SNR or inherent SNR value) of equal valuely, definition $Q\left(T\right)=\frac{1}{2\left|T\right|}\underset{i\∈T}{\mathrm{\Σ}}{x}_i{z}_i,$ Z wherein _iBe outside input information, T is the set of a continuous sampling index in the Frame, | T| is the quantity of index, and the present invention provides from mean virtual SNR value and can be calculated by following formula:

$\left(21\right),\mathrm{AverageSNR}\left(T\right)=\mathrm{StartSNR}+Q\left(T\right)+\frac{1}{\left|T\right|}\left\{\frac{{\mathrm{\σ}}^2}{8E_b}\underset{i\∈T}{\mathrm{\Σ}}{z}_i^2\right\},$

The practical version of virtual SNR (hard or soft) then is:

$\left(22\right),\mathrm{AverageS}{\mathrm{NR}}_H\left(T\right)=\mathrm{StartSNR}+Q_H\left(T\right)+\frac{1}{\left|T\right|}\left\{\frac{{\mathrm{\σ}}^2}{8E_b}\underset{i\∈T}{\mathrm{\Σ}}{z}_i^2\right\},$

$\left(23\right),\mathrm{AverageS}{\mathrm{NR}}_S\left(T\right)=\mathrm{StartSNR}+Q_S\left(T\right)+\frac{1}{\left|T\right|}\left\{\frac{{\mathrm{\σ}}^2}{8E_b}\underset{i\∈T}{\mathrm{\Σ}}{z}_i^2\right\},$

Wherein $\mathrm{StartSNR}=\frac{1}{2}\underset{i\∈T}{\mathrm{\Σ}}\left\{\frac{E_b}{{\mathrm{\σ}}^2}(x_i^2+p_i^2)\right\}=\frac{E_b}{{\mathrm{\σ}}^2},$ For initial SNR, work as T={0,1 ..., during L-1}, preceding formula is the quality index of frame; Work as T={0,1 ..., N-1} and W=0,1 ..., during L-1, these quality index just and be used for the Yamamoto-Itoh index similar (referring to the article of above-mentioned H.Yamamoto and K.Itoh) of the classics of the ARQ scheme that Viterbi decodes are worked as T={i, i+1 ..., i+W-1} and i=0,1 ..., during L-W-1}, these quality index are the mean value of some external informations that move basically, and the present invention is called this index the local quality index that monitors local decoder.

MAP (BCJR) decoder, architecture and further popularization:

Realize MAP decoding and turbo decoding key technology and do not lie in the butterfly structure (this and Viterbi decode and be very different) that design decoding trellis state is handled, this being used to upgraded the structure that reduces amount of calculation in the processing at the ACS path metric, in actual design, can be designed to handle 2 simultaneously, 4,8 or the butterfly structure of the trellis state of more decoding, the many more states of parallel processing simultaneously, the speed of Viterbi decoder is fast more (this can increase the hardware of actual realization certainly) just, the strategy that the butterfly structure that the decoding trellis state is handled is arranged in parallel was in depth studied (for example article of the Fettweisand H.Meyr that mentions repeatedly of front), but this technology is not very practical for turbo decoding, because the trellis state of used composition MAP sign indicating number is all seldom in the turbo sign indicating number usually; Replacing recalling fully of each Frame with the clean cut system Viterbi decoder of limited traceback length is another traditional important implementation method, this technology further is modified into the technology that is called sliding window, its purpose mainly is to be used for reducing needed internal memory in MAP decoder and the turbo decoder design, the cost of exchange is unnecessary computing naturally, the present invention claims that this class technology is monolateral window algorithm, but this technology can not improve the speed of decoder; Yet, the present invention's improvement has also developed this technology, it is developed into the bilateral window algorithm of MAP decoding, and with this technology first Application among the design of high speed MAP decoder (thereby being different from traditional window algorithm of only setting up) for the internal memory that reduces decoder, thereby introduced local MAP decoding algorithm, and the speed of having broken first by Frame that size caused postpones barrier; Given only to the MAP decoding capability of one piece of data in the frame, the present invention can use the local MAP decoder that is arranged in parallel that whole Frame is decoded, so just can be that to construct in theory almost be the MAP decoder with arbitrary speed at least, opposite extreme situations then is to come data bit is only decoded with a local MAP decoder, the time delay of so whole MAP decodings just is lowered to and only is the processing time of bilateral window, this is a fixing clock cycle constant, and this time delay can utilize the hardware designs of optimization to be dropped to minimum, therefore the inventive method is actually that to have reached be the speed limit of possible in theory high speed MAP decoder at least, thereby also to have reached be the speed limit of possible in theory high speed turbo decoder at least, and by means of Yamamoto-Itoh type index, various ARQ schemes and local iteration stopping algorithm, the MAP decoder and the turbo decoder that have adaptivity also can be set up on the basis of local MAP decoder at an easy rate; The present invention now formally provides local MAP algorithm, and in form, the size of supposing to comprise the Frame of tail position is L, uses M local MAP decoder (entire frame is equally divided into M part, certainly cuts apart with inhomogeneous), supposes $\frac{L}{M}=N$ Be integer, local MAP algorithm is as follows in detail:

Local MAP decoding algorithm:

(1) if i=1 uses sampling { y ₀, y ₁..., y _4M-2, y _4M-1Starting recursive calculation forward based on butterfly structure, initial value is a (0)=1 and a (i)=0, i ≠ 0; With sampling { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, be provided with initial value for ( $b_i=\frac{1}{N_{\mathrm{state}}};$ To information data bit { x ₀, x ₁..., x _M-1Carry out the MAP decoding, export the LLR value;

(2) if i=N-1 or i=N use sampling { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, and initial value evenly is set, with the backward recursive calculation of same sampling startup based on butterfly structure, initial value is set at b (0)=1 and b (i)=0, and i ≠ 0 is to data bit { x _L-2M, x _L-M+1..., x _L-1Carry out MAP decoding, output LLR value note that because the identical starting point of recurrence is backward arranged, and two kinds of situations are overlapped, and the calculating repetition of latter two window (promptly latter two window decode simultaneously) is arranged;

(3) if 1＜i＜N-1 uses sampling { ξ _{2 (i-1) M}, ξ _{2 (i-1) M+1}..., ξ _{2 (i+2) M-2}, ξ _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, and initial value evenly is set, with the backward recursive calculation of same sampling startup, initial value is set evenly based on butterfly structure, output LLR value is to data bit { x _IM, x _IM+1..., x _{(i+1) M-1}Decode and carry out the MAP decoding;

As previously mentioned, local MAP algorithm is the MAP algorithm to classics, the further improvement and the development of the clean cut system MAP algorithm based on monolateral window technique (setting up) commonly used in the engineering design for saving decoder memory, this local MAP algorithm is the following high speed MAP decoding algorithm that will introduce, high speed turbo decoding algorithm, the MAP algorithm that has adaptivity, the basis that has the MAP algorithm of adaptivity, this straightforward procedure is core of the present invention and key point, and local MAP decoder (when decoded data segment has comprised whole frame data) when bilateral window is tending towards infinite is exactly traditional MAP decoder, and local MAP decoder is exactly a clean cut system MAP decoder if only use monolateral window, being connected of this and traditional scheme, not only further confirm the present invention, disclosed MAP decoding algorithm and the MAP algorithm that has adaptivity more, and then turbo decoding algorithm and the harmony that has the turbo algorithm inherence of adaptivity.

Aspect architecture, the design of local MAP decoder then can be made amendment according to the architecture of traditional clean cut system MAP decoder, people are at clean cut system MAP decoder, the architecture of turbo decoder and realization skill aspect have accumulated a large amount of experiences on the basis of practice for many years, and have many through putting into practice the design illustration of abundant checking, the local MAP algorithm that the present invention introduced structurally is the continuity and the further improvement development of the architecture of clean cut system MAP decoder, thereby experience in the past and technological reserve can be applied to local MAP decoder soon, in the middle of the design of turbo decoder and the high speed turbo decoder that is about to be introduced into and the turbo decoder (high speed MAP decoder and the MAP decoder that has adaptivity) that has adaptivity, local MAP decoder as shown in fig. 1.

The turbo decoder design method that has adaptivity:

Use local MAP decoder can on a data segment rather than whole Frame, carry out the MAP decoding, thereby can further set up high speed turbo decoder and have the design of the turbo decoder (based on high speed MAP decoder and have the MAP decoder of adaptivity) of adaptivity, briefly, when utilizing local MAP decoder, can give up data segment and keep data segment with good SNR value with bad SNR value, certainly can also require transmitter to resend bad data section and bad data frame, so just can obtain having the whole frame of low bit error probability, under the help of local MAP decoder, the present invention can revise Yamamoto-Itoh type ARQ scheme index and each quasi-tradition of using at an easy rate, the one piece of data that allows the ARQ scheme have network has the ability that request again sends, so just can give up data segment (rather than whole frame data) at receiving terminal with bad SNR value, and then require transmitter to transmit the data of this section again, the average SNR value of a whole frame will improve and guarantee (promptly guaranteeing the quality of whole Frame by the quality control of local data's section), certainly, the present invention also can be in conjunction with other various dissimilar traditional ARQ methods on the basis of local MAP decoder, and then the transmission again that utilizes local data's section guarantees the quality of entire data frame, this has had substantial different with traditional ARQ method, in addition, on the basis of local MAP decoder, stop algorithm in conjunction with local iteration, the present invention will provide the class turbo coding/decoding method that has adaptivity with delicate structure, this is class the past and non-existent new method, also is a key point place of the present invention; As before, the frame length of supposing to comprise the tail bit is L, with M local MAP decoder (be about to whole Frame and be equally divided into M part, certainly cut apart with inhomogeneous), supposes $\frac{L}{M}=N$ Be integer, have the turbo decoder of adaptivity, the MAP decoder algorithm that has an adaptivity is described in detail as follows.

The MAP decoding method for designing of band adaptivity:

(1) the MAP decoder that has an adaptivity comprises M the data segment of M local MAP decoder corresponding to whole Frame, and the size of supposing all bilateral windows is equal to and long enough (long decode and the performance error that brings to ignoring by approximate MAP);

(2) data segment that will have bad SNR value is given up the MAP decoding that is used to have adaptivity with the various ARQ schemes of transmission again, if the average SNR value of a data segment is lower than certain threshold value, just can give up this data segment and require transmission again, if can before local MAP decoding, can estimate that its average SNR value and its SNR value are lower than the threshold value that sets, just can not need move this part MAP decoder, directly skip this data segment and directly requirement transmission again; This is based on the MAP decoding that has adaptivity of local ARQ scheme and local MAP decoder;

(3) the local ARQ scheme of using the similar index of Yamamoto-Itoh can be used among the MAP coding/decoding method that has adaptivity based on local MAP decoder, if the minimum Yamamoto-Itoh index on data segment is lower than certain threshold value, just can gives up this data segment and require and resend;

Aspect architecture, the design of local MAP decoder can be made amendment on the basis of traditional clean cut system MAP decoder architecture, therefore and the MAP decoder that has an adaptivity can be by means of the improvement of conventional architectures design is designed, the topmost part that realizes is setting up of ARQ scheme and to having the control of adaptivity MAP decoder, the main task of this control in fact then is the control to local MAP decoder, what is particularly worth mentioning is that in realization and have in the process of adaptivity MAP decoder, the designer must consider the requirement of whole communication system and define, rather than only do local consideration.

For the performance that has adaptivity MAP decoder is described, the present invention draws in the row explanation by the performance that has adaptivity Viterbi decoder, the MAP decoder is more excellent than Viterbi decoder on the performance performance, below is the performance results that author of the present invention utilizes traditional skill (please in conjunction with the monograph referring to above-mentioned A.Viterbi and J.Omura) to obtain.

The performance that has adaptivity MAP decoder proves:

If adopt based on having of ARQ scheme of adaptive Viterbi decoding, and the SNR threshold value is T ^*(certainly general supposition less than

), the position error probability of the Frame that so finally receives:

$\left(24\right),p_e\≤Q\left(\sqrt{2d_f{T}^{*}}(1+\frac{A{N}_0}{4E_b})\right)\·e^{d{E}_b/N_0}\·T\left(D\right){|}_{D=e^{-E_b/N_0}},$

D wherein _fBe the free distance of decoding network, p _eBe the probability of error of each node, T (D) is a generating function; What we were same has:

$\left(25\right),p_b\≤Q\left(\sqrt{2d_f{T}^{*}}(1+\frac{A{N}_0}{4E_b})\right)\·e^{d{E}_b/N_0}\·T\left(D\right){|}_{D=e^{-E_b/N_0}},$

P wherein _bBe a decision errors probability, (D, L I) are generating function to T, and L represents length, and I represents in the information sequence 1 number; For the ARQ scheme that adopts based on the Yamamoto-Itoh index of the Viterb decoding that has adaptivity, the data bit probability of error of final frame:

$\left(26\right),p_e\≤Q\left(\sqrt{\frac{2d{E}_b}{N_0}}(1+A)\right)\·e^{d{E}_b/N_0}\·T\left(D\right){|}_{D=e^{-E_b/N_0}},$

D wherein _fBe the free distance of decoding network, p _eBe the probability of error of each node, T (D) is a generating function; We have equally:

$\left(27\right),p_b\≤Q\left(\sqrt{\frac{2d{E}_b}{N_0}}(1+A)\right)\·e^{d{E}_b/N_0}\·T\left(D\right){|}_{D=e^{-E_b/N_0}};$

Above notional result is: the performance performance of information bit position error probability that has the MAP decoder of adaptivity, by means of traditional ARQ scheme and the ARQ scheme of utilizing Yamamoto-Itoh type index, the performance of MAP decoder can improve to some extent, what scheme provided by the invention was the most basic is by means of local MAP coding/decoding method, by the lay equal stress on method of each segment data sampling of new transmission of inspection, the effective SNR value that guarantees the sampling of each segment data also further guarantees effective SNR value of a whole frame sampling, because signal suffered influence in transmission course is different and inhomogeneous, so utilize local MAP algorithm can on validity, surpass ARQ scheme based on a whole frame for the ARQ scheme on basis, yes with the performance performance and the effective information output rating of information bit position error probability is standard in the measurement of validity, because local MAP decoding algorithm can be used to carry out even be small enough to the decoding of a data bit, so provided by the present invention have greatest possible flexibility based on the ARQ scheme that has adaptivity MAP decoding, thereby the present invention is called the MAP coding/decoding method that has adaptivity; But a part that what is particularly worth mentioning is that this method is used the realization index of effective SNR value as ARQ, this but can only depend on estimation in practice, and also enumerated the method for estimation of some SNR values in the preamble, there is a minutia to need to prove that the estimation of SNR value is locally more (estimation that is accurate to each sampling to be arranged preferably well more, because so be the ultimate attainment of adaptivity), yet local method of estimation but has the error that itself exists, (only utilize the estimation of a sampling and the short more error of estimating of section is just big more, be the ultimate attainment of error), so be major issue in the design to this two kinds of ultimate attainment situations compromise.

The present invention now introduces the turbo decoding scheme that have adaptivity of employing based on local MAP decoder, the key of this scheme is the combination and the local turbo iteration stopping scheme of local MAP decoder, the scheme that stops of turbo iteration has a variety of, the present invention has proposed to have introduced local iteration stopping scheme first on the basis of local MAP decoding algorithm, if a frame is divided into the disjoint part of T section: K by data sampling according to time index _i={ d _i, d _I+1..., d _I+1, 0≤i＜T wherein, d ₀=0, d _T+1=L-1, wherein d _i＜d _I+1, at time period M _i={ d _i-W, d _i-W+1 ..., d _i..., d _I+1, d _I+1+ 1 ..., d _I+1The local MAP decoder (wherein W is the synchronous window size) of the last foundation of+W} is in order to cover whole Frame, the present invention has the turbo decoding of adaptivity by the local MAP decoder that is arranged in parallel of forming decoder corresponding to each, then each data segment is used local iteration's stopping criterion respectively, like this, the present invention can avoid traditional unified turbo iteration stopping method, thereby provides maximum adaptivity for turbo decodes; On directly perceived, the sampling that attenuation channel generally can not cause receiving in the Frame has uniform influence, some sampling repeatedly just can draw Useful Information through iteration possibly, simulation result shows, most of data bit error just has been corrected after preceding iteration several times, the error that in fact the required last interative computation of doing is revised is also few, in the turbo decoding algorithm that has adaptivity provided by the present invention is handled, some local MAP decoder may stop at first earlier, because the turbo decoding is based on the operation of whole Frame and adopts turbointerleaver to divide iteration, even some local MAP decoder can at first be stopped, the present invention still needs to proceed the whole turbo decode procedure based on iteration, ability all suspend turbo process of decoding process when each local MAP decoder can be stopped, the invention provides the scheme that can make up a kind of branch road like this and cooperate turbo interleaver and de-interleaver, this branch road scheme can at first be ended some local MAP decoder, and then carry out the turbo iteration, and each is formed the MAP decoder use the MAP piece that has adaptivity, LLR value and external information need be fed equally to the MAP piece that has adaptivity and calculate virtual SNR value (this is with one of traditional MAP decoding serious difference very) in addition, have adaptivity turbo decoding scheme as shown in Figure 2, have adaptivity the MAP decoding scheme as shown in Figure 3.

Now briefly describe the iteration stopping algorithm of turbo of the present invention decoding and local iteration that the present invention will use and stop algorithm, the iteration stopping algorithm is the important supplement and the part of turbo decoding algorithm, its main purpose is to reduce operand by reducing iterations, and then the power consumption of minimizing decoder (this is generally believed it is the method that reduces decoder power consumption effectively), the foundation of these class methods is convergence properties of turbo decoding, based on the turbo decode procedure of interative computation is a progressively correction of data bit process of makeing mistakes, and the convergence property of algorithm itself (mathematical principle of this convergence property does not have as yet at present clearly and to analyze, but the industry that is brought of this revolutionary method influence has greatly promoted the development of communication science, usually mostly everybody institute's foundation is in experiment accumulation and the data that observe) determined finishing iteration computing in advance may, because most data bit bit-errors has obtained correction in front the iteration, iteration afterwards is just in order to correct a spot of mistake, in fact, turbo decoding enter saturated after, the number of times that increases interative computation can not bring substantial error correction contribution, thereby finish in advance the turbo iteration (under the unimportant performance performance loss prerequisite and the stop after entering saturation condition) be must and effectively to reduce operand, and then the means of minimizing decoder power consumption; Mainly contain the following aspects in the work aspect the turbo decoding iteration stopping algorithm: (1) is based on the scheme of cross-entropy, this is one of turbo decoding iteration stopping scheme the earliest, please referring to article J.Hagenauer et al, Iterativedecoding of binary block and convolutional codes, IEEE Trans.InformTheory, Vol.42, pp429-445, March, 1996 and wherein institute's quoted passage offer, (2) scheme of on the basis of cross-entropy, further being simplified, further developing in this respect then is two kinds of methods very commonly used, one is based on the hard decision data bit bit comparison between the two-layer iteration, the 2nd, the sign change of the output external information hard decision between the more two-layer iteration, detailed condition is please referring to article R.Y.Shao, S.Lin and M.P.C.Fossorier, Two simples topping criteria forturbo decoding, IEEE Tans.Comm., Vol.47, No 8, pp1117-1120, August, 1999 and wherein institute's quoted passage offer, wherein the method based on the hard decision data bit bit comparison between the two-layer iteration is used in many designs, this perhaps is the turbo decoding iteration stopping method that is most widely used, (3) the method for using always on the engineering based on turbo decoding experiment and observe phenomena (particularly convergence property), this is the method for a class based on experience and intuition, the concrete decoder design of many combinations and the iteration stopping method set up can be summed up as this class, concrete example comprises: utilize methods such as the threshold value of LLR value or gradual judgement, these class methods have more in the middle of the product design of present each company, please refer to the relevant description of product of each company, (4) other turbo decoding iteration stopping methods, these class methods are some schemes outside the whole bag of tricks of front substantially, about the summary of the situation of this respect and above-mentioned all kinds of turbo decoding iteration stopping methods please referring to article A.Matache, S.Dolinar and F.Pollara, Stoppingrules for turbo decoders, JPL TMO Progress Report 42-142, August, 2000 and wherein institute's quoted passage offer; The present invention needs lay special stress on to be pointed out that above-described a variety of algorithm can use in conjunction with local MAP decoding algorithm, that is to say that a variety of methods (being actually most method) can be used to stop local MAP decoder through suitable modification, this scheme is also to introduce first in the present invention in conjunction with local MAP decoding, and the introduction of this local turbo decoding iteration stopping method makes the turbo decoding possess maximum flexibility and adaptivity.

Existing set forth in detail the present invention has some designing technique details of the turbo decoder of adaptivity, each siso decoder device that has adaptivity comprises several local MAP decoders, virtual SNR value or local quality index are calculated, branch road control is fast, its running details is that each local MAP decoder is all with a local quality index verification unit, this quality inspection unit, part determines whether should be with the bypass of local MAP decoder, use very simple hard decision just can calculate the hard or soft version of local quality index, or the value of virtual SNR, whether each local MAP decoder is at first checked and be decoded, if local virtual SNR value is good, LLR value and external information value just need directly not be passed to next decode phase through decoding so; Otherwise, local MAP decoder will be decoded to corresponding data segment, upgrade LLR value and external information value, this control and calculation mechanism can utilize certain " sleep pattern " the turbo iteration termination to be merged in the scheme of parallel local MAP decoder, so local MAP decoder just needn't move all the time, just can keep " sleep state " when by bypass; Clearly, " sleep state " of local MAP decoder not only reduced computing, also reduced simultaneously decoder power consumption, please note, when LLR value and external information value are directly delivered to next decode phase, also reduced and had needed decode time in the adaptivity turbo decoding, more precisely, as long as increasing local MAP decoder enters sleep, the decode time that each composition has the MAP decoder of adaptivity will become shorter and shorter, be cleverly: if make a local MAP decoder sleep, this local MAP decoder will still keep sleep at next decode phase, the required decode time of each turbo decoding iteration cycle will become shorter and shorter like this, when all local MAP decoders enter resting state, whole turbo decoding iteration termination, the turbo decoding scheme that has adaptivity can be described as follows.

The turbo decoding method for designing of band adaptivity:

(1) the turbo decoder that has the adaptivity MAP decoder that has adaptivity that comprises two same compositions constitutes, separate by staggered (turbo interleaver) and reciprocal cross mistake (turbo deinterleaver) respectively between them, it is input as data sampling, external information and LLR value, is output as to feed back to LLR value and the external information that next composition has adaptivity MAP decoder;

(2) corresponding to M data segment of Frame in the described data sampling, each composition has adaptivity MAP decoder M local MAP decoder, each local MAP decoder is one and has the local MAP decoder of local soft output (output of LLR value is promptly arranged) that each local decoder all has a branch road scheme module to decide this part MAP decoder whether should avoid decoding and directly enters sleep state;

(3) the following operation of branch road scheme of described local MAP decoder: a) at first calculate hard or soft local virtual SNR value or quality index with LLR value and external information, (b) check whether local quality index or virtual SNR surpass certain threshold value or arrived at asymptotic behaviour, (c) if local quality index or virtual SNR passing threshold or asymptotic check, then branch road should part MAP decoder, otherwise move local MAP decoder, " branch road " expression output LLR value and external information value should be input LLR and external information value (computing so need not decode), when local MAP decoder during, then enter sleep state by branch road;

(4) local MAP decoders of having slept will keep sleep state in remaining interative computation, when all local MAP decoders all enter sleep state, just finished the turbo decode procedure that has adaptivity;

(5) Ju Bu soft sampling can be resend, the foundation that resends can be local virtual SNR value or other standards, the local ARQ scheme that use can be similar to the Yamamoto-Itoh index is used among the MAP coding/decoding method that has adaptivity based on local MAP decoder, if the minimum Yamamoto-Itoh index on data segment is lower than certain threshold value, then can gives up this data segment and require and resend;

High speed turbo decoder design method:

Narration now the present invention is based on the high speed turbo decoding algorithm of high speed MAP decoding algorithm, this is the present invention's content of core the most, it also is one of the strongest aspect of practicality, at local MAP decoder, have under the situation that the MAP decoder of adaptivity introduced, introduce high speed MAP coding/decoding method, high speed turbo coding/decoding method is to become very direct and lead-pipe cinch in theory at least; Usually the strategy that makes up the High Speed Viterbi decoder is with the ACS butterfly structure parallel arrangement that is used to handle the decoder trellis state commonly used, utilize parallel processing to improve the speed that the network state is handled, ACS butterfly structure commonly used generally has 2 states simultaneously, 4 states or the like, be arranged in parallel or serial arrangement is balance hardware area (if realizing with ASIC) and a decoder speed and fixed, the work of this respect has many detailed elaborations, and the article of wherein above-mentioned G.Fettweis and H.Meyr is that the stage of this direction is summed up; Yet this strategy, effective to the High Speed Viterbi decoder, but be not suitable for the composition MAP decoder that has only the minority trellis state, thereby in actual applications and be not suitable for the turbo decoder, this means that being arranged in parallel of local MAP decoder is necessary high speed turbo decoding policy, this obviously is based on the high speed turbo decoding policy of high speed MAP decoder, can design more exquisite architecture in practice; The same with the front, the present invention supposes that whole Frame is divided into M part (suppose divide be unified), and the frame length of suppose to comprise the tail bit is L, with the individual local MAP decoder of M (soon entire frame is divided part for M equally, certainly uses inhomogeneous cutting apart), supposes $\frac{L}{M}=N$ Be integer, high speed MAP decoding, high speed turbo decoding scheme then are the comparatively detailed design methods of structure high speed MAP decoder provided by the present invention as shown in Figures 4 and 5 below;

The high speed MAP method for designing of decoding:

(1) high speed MAP decoder comprises M the data segment that M local MAP decoder corresponds to whole Frame, supposes that the size of all bilateral windows is equal to and long enough (long to ignoring the performance error that is brought by the approximate MAP decoding);

(2) the local MAP decoder of the M in the parallel work-flow high speed MAP decoder carries out local MAP decoding respectively to M data segment of whole Frame, and these computings are when parallel processing as far as possible (yes sampling situation about having possessed under);

(3) can be in conjunction with the MAP decoder that has adaptivity in high speed MAP decoder, i.e. design according to high speed MAP decoder is used in combination the ARQ scheme; The various ARQ schemes that data segment with bad SNR value can be given up and transmit again are used to have the MAP decoding of adaptivity, if the average SNR value of a data segment is lower than certain threshold value, then can give up this data segment and require transmission again, if can before local MAP decoding, can estimate that its average SNR value and its SNR value are lower than the threshold value that sets, just can not need move this part MAP decoder, directly skip this data segment and directly requirement transmission again; This is based on the MAP decoding that has adaptivity of local ARQ scheme and local MAP decoder;

(4) the local ARQ scheme of using Yamamoto-Itoh type index can be used for high speed MAP coding/decoding method based on local MAP decoder, if the Yamamoto-Itoh index is lower than certain threshold value on the data segment, then can gives up this data segment and also require to resend;

(5) decoding speed of high speed MAP decoder is by the degree of concurrence decision of local MAP decoder, if the whole parallel processings of all local MAP decoders, then high speed MAP decoder has the highest speed of service, if all local MAP decoders are serial process one by one all, then high speed MAP decoder has the minimum speed of service; Below be the extreme case of two designs: if use L local MAP decoder (promptly each sample all being set up a local MAP decoder) and all parallel processings, then obtain possible maximum speed MAP decoding, if use a local MAP decoder (promptly not adopting window algorithm fully), then be the slowest traditional MAP coding/decoding method;

Now high speed MAP decoder speed of the present invention is made further brief analysis, suppose in a clock cycle, to carry out the processing (this can realize by means of the hardware designs skill) of all decoding network states that need to each data bits, then the decode time of each local MAP decoder postpones (to use suitable hardware technology for 3M clock cycle, the logical gate expense that the LLR value is calculated can drop to zero, these delays thereby be left in the basket at this are disregarded), under complete parallel processing situation, it also is 3M clock cycle that the decode time of high speed MAP decoder postpones, it is a fixing value, so the speed of high speed MAP decoder is in theory almost to reach unlimited at least, for example, if select M=100, then the present invention can carry out MAP decoding (such MAP decoding speed almost is enough near the transfer of data of dealing with any digit rate) to whole Frame in 300 clock cycle, the design tactics of hardware is enough to set up in the more limited clock cycle the local MAP decoder that (can less to having only several clock cycle) finishes still more, at first, for being arranged in parallel of the local MAP decoder of having broken through the data frame size barrier, the speed of whole parallel high speed MAP decoders is irrelevant with the size of Frame, secondly, as long as the speed of high speed MAP decoder is faster than other digit receiver module, just can think that the speed of MAP decoder is enough fast, because do not need speed in actual applications near unlimited MAP decoder; Aspect the realization cost, need to consider because realization costs such as the silicon area expansion that the parallel arranged of local MAP decoder causes, the increases of practical operation power consumption, compare with common MAP implementation, use the parallel arranged of complete parallel local MAP decoder and the ASIC area rough estimate that realizes increases Doubly (yes does not consider relevant additional logic and control logic), the present invention can suitably suppose operation The power consumption of the local MAP decoder of individual parallel processing is the common local MAP decoder operation power consumption of operation

Doubly, the extra computing that the increase of operation power consumption brings mainly due to first synchronous window handling part branch (adopt the monolateral window technique that slides, this part is essential) is compared with common MAP decoder, and dynamic power consumption approximately increases The silicon chip area occupied and the power consumption that note that each local MAP decoder are equally also determined by the concrete layout type of butterfly structure.

After setting up high speed MAP decoding scheme, the present invention can make up high speed turbo decoder at an easy rate, needed only is to make up to form the MAP decoder at a high speed, and the prerequisite of discussing is that the present invention supposes that turbo interleaver and de-interleaver are not the bottlenecks that limits turbo decoder speed certainly.The same with the front, suppose that whole Frame is divided into M part (suppose divide be unified), the frame length of suppose to comprise the tail bit is L, with the individual local MAP decoder of M (soon entire frame is divided part for M equally, certainly uses inhomogeneous cutting apart), supposes $\frac{L}{M}=N$ Being integer, is the comparatively detailed method for designing of structure high speed turbo decoder provided by the present invention below.

The method for designing of high speed turbo decoder:

(1) high speed turbo decoder comprises the high speed MAP decoder of two same compositions, these two high speed MAP decoders are divided by turbo interleaver and de-interleaver to be opened, to the soft sampling of the input of each high speed MAP, external information and LLR value, each high speed MAP is output as and feeds back to next LLR value and the external information of forming high speed MAP decoder;

(2) each high speed MAP comprises M local MAP decoder corresponding to M data segment of whole Frame (pressing the frame that original time sequence arrangement or the time sequencing after de-interleaver are arranged), each local MAP decoder is a local MAP decoder that has soft output LLR value, and each local MAP decoder all has relevant decoding branch road scheme to confirm whether local MAP decoder should enter sleep state;

(3) the branch road scheme of described local MAP decoder is: a) at first calculate corresponding hard or soft approximate SNR value or quality index with input LLR value and external information, (b) check whether approximate SNR value or local product index surpass threshold value or arrived at asymptotic behaviour, (c) if approximate SNR value or quality index surpass the check threshold value or have arrived at asymptotic behaviour, the local MAP decoder of branch road, otherwise move the computing of decoding of this part MAP decoder, here " branch road " expression directly will import LLR value and external information value as exporting LLR value and external information value, and the computing of not decoding, when local MAP decoder enters sleep state during by branch road;

(4) can not activate one at next iteration cycle and enter dormant local MAP decoder, in other words, each forms the number that has entered dormant local MAP decoder in the high speed MAP decoder can constantly increase along with iteration, after all local MAP decoders enter sleep state, iteration stopping and finished high speed turbo decode procedure;

Obviously, the speed of high speed turbo decoder and shared hardware are all mainly decided by wherein two designs of forming high speed siso decoder device (promptly forming high speed MAP decoder for two), do not repeat them here.

Granularity, flexible combination, the realization degree of freedom and numerical result:

The MAP decoder scheme that has adaptivity can pass through data processing, resend or with being similar to Yamamoto-Itoh type index, various traditional ARQ schemes strengthen the decoding quality of data, realize that the key of these schemes is to carry out the local MAP decoder of segment processing, because data segment can be the same long with an entire data frame, or it is the same short with a single sampling, the present invention just can make up the turbo decoder that has adaptivity neatly with the degree of freedom of maximum, the other technologies of using are effective discharges of SNR estimation or ARQ scheme, compare with traditional various ARQ schemes by means of decoding, scheme provided by the present invention is then can be at the enterprising line operate of any one little segment data, this new scheme thereby have very big adaptivity.

The present invention regards the High Speed Viterbi decoding scheme as two kinds of combinations of handling operation: trellis state is handled and data sampling is handled, trellis state can be handled with the mode of parallel or serial with data sampling, and then also these processing can be regarded as state " decomposition " and the combination of sample " decomposition ", the parallel processing degree is high more, just be considered to decompose just thin more, otherwise, the parallel processing degree is low more, just be considered to decompose just thick more, the sequential organization that the hypothetical trellis state is occurred when being handled according to butterfly structure, data sampling is then with the time sequencing tissue of nature, the same shown among Fig. 6 and Fig. 7, each box is corresponding to a local Viterbi decoder, trellis state is decomposed and data sampling decompose can the overall situation or local uniform distribution (the local Viterbi decoder that non-uniform Distribution is certainly arranged), a local Viterbi decoder can be broken down into two local Viterbi decoders, two continuous adjacent local Viterbi decoders of order can be merged into a local Viterbi decoder, this " separate and merge " can finish according to decomposing granularity arbitrarily, similarly, the trellis state decomposition also can " be separated and merge " (to have and segments the complete parallel arranged of butterfly structure of separating most, in contrast, having the butterfly structure that rough segmentation separates then is complete serial arrangement), the High Speed Viterbi decoder can be based on decomposition and combination arbitrarily and is designed, velocity interval then from the slowest (corresponding to the thickest decomposition) to the fastest (corresponding to the thinnest decomposition), the flexibility of this design and freedom have disclosed in the Viterbi decoder design inherent and harmonious grace; Same this decomposition is equally applicable to the analysis to high speed MAP decoder and then high speed MAP decoder, to turbo decoder that has adaptivity and then the analysis that has the turbo decoder of adaptivity.

The performance that the present invention now provides local MAP decoding scheme partly shows the good property of adaptive turbo decoding scheme, only provide and have the different windows size, the turbo decoder capabilities that on static channel, is arranged in parallel based on local MAP decoder, (constraint length is 4 to adopt standard CDMA 2000turbo sign indicating number, code check be 1/3 and code check be 1/2 composition sign indicating number, 640 of every frames), for enough big window size (providing two diagrams of max and max*), performance than the optimum limit reduces and can be left in the basket, at Fig. 8-1, during Fig. 8-2 is described, W20, W15, W10 represents that respectively window size is 20,15 and 10 BPSK modulation symbols; In actual design, can draw the window size of " optimum " with emulation, the present invention notices based on the turbo decoding of max lower than the turbo decoding sensitivity based on max*, this is consistent with our intuition and experience fully.

Wherein: the described turbo decoder control system that has adaptivity is to be used to control, coordinate and to dispatch whole each part and its function that has the turbo decoder of adaptivity, and M local MAP decoder all had an independently control system; The described data turnover system that has the turbo decoder of adaptivity is used to control, the turnover of coordination data, and each local MAP decoder all has a data turnover system; The described external interface that has the turbo decoder of adaptivity is used for being connected and communication of this decoder and interior other parts of communication system, and each local MAP decoder all has and outside communication system.

Described high speed turbo decoder control system is used to control, coordinate and dispatch each part and its various functions of whole high speed turbo decoder, and M local MAP decoder all had an independently control system; The data turnover system of described high speed turbo decoder is used to control, the turnover of coordination data, and each local MAP decoder all has a data turnover system; The external interface of described high speed turbo decoder is used for being connected and communication of this decoder and interior other parts of communication system, and each local MAP decoder all has and outside communication system.

In a word, the present invention proposes the design and the algorithm that make up the turbo decoder have adaptivity and high speed turbo decoder (being based on the MAP decoder that has adaptivity and the basis of high speed MAP decoder naturally), architecture and realization guide, ignoring under the prerequisite that realizes cost, the solution of the present invention has obtained high speed turbo decoder and the complete adaptive designed capacity that has the turbo decoder of adaptivity that at least in theory almost has any fast speed, and theoretical analysis result and numerical result have further been verified these decoding schemes.

Claims (13)

1. one kind has adaptivity turbo decoder, it is characterized in that: based on local MAP decoder technique, adopt bilateral window, in conjunction with the ARQ scheme that comprises Yamamoto-Itoh type index, to improve the quality of turbo decoding, make it possess the ability of adaptive channel signal attenuation; Comprise two same compositions the MAP decoder that has adaptivity, have adaptivity turbo decoder control system, have the turbo decoder of adaptivity data turnover system, have the external interface of the turbo decoder of adaptivity; Separately wrong by the alternation sum reciprocal cross respectively between the MAP decoder that has adaptivity of described two same compositions, the MAP decoder that has adaptivity of two same compositions be input as data sampling, external information and LLR value, be output as the LLR value and the external information that have adaptivity MAP decoder that feed back to next same composition.

2. according to the described adaptivity turbo decoder that has of claim 1, it is characterized in that: the described MAP decoder that has adaptivity comprises M local MAP decoder, M data segment corresponding to Frame, in the average SNR estimated value of this corresponding data segment or the ARQ scheme index that comprises Yamamoto-Itoh type index during less than given threshold value, local sampling is resend, and promptly realizes adaptivity.

3. according to the described method for designing that has adaptivity turbo decoder of claim 1, it is characterized in that: the described MAP decoder that has adaptivity comprises M local MAP decoder, M data segment corresponding to Frame, the branch road scheme module that all has each local MAP decoder decides this part MAP decoder whether should avoid decoding and directly enters sleep state, promptly calculate hard or soft local virtual SNR value or local quality index with LLR value and external information value, check whether local quality index or virtual SNR value surpass certain threshold value or arrived at asymptotic behaviour, if local quality index or virtual SNR value surpass threshold value or arrive at asymptotic behaviour, then branch road should part MAP decoder, otherwise move local MAP decoder, " branch road " is so expression output LLR value and external information value should be to import the computing of need not decoding of LLR and external information value, when a certain local MAP decoder during, promptly enter sleep state by branch road; When all local MAP decoders all enter sleep state, then finish the turbo decode procedure that has adaptivity.

4. according to the described adaptivity turbo decoder that has of claim 1, it is characterized in that: the described turbo decoder control system that has adaptivity is to be used to control, coordinate and to dispatch each part of the whole turbo decoder that has an adaptivity and the function of each part, and M local MAP decoder has an independently control system respectively; The described data turnover system that has the turbo decoder of adaptivity is used to control, the turnover of coordination data, and each local MAP decoder all has a data turnover system; The described external interface that has the turbo decoder of adaptivity is used for being connected and communication of this decoder and interior other parts of communication system, and each local MAP decoder all has the system with external communication.

5. according to the described adaptivity turbo decoder that has of claim 1, it is characterized in that: the size of establishing the decoded Frame that comprises the tail position is L, use M local MAP decoder, the MAP decoding method for designing of band adaptivity is as follows: the MAP decoder that 1) has adaptivity comprises M the data segment of M local MAP decoder corresponding to whole Frame, supposes the big or small long enough of bilateral window; 2) data segment that will have bad SNR value is given up the MAP decoding that is used to have adaptivity with the various ARQ schemes of transmission again, if the average SNR value of a data segment is lower than certain threshold value, then give up this data segment and require transmission again, if can be before local MAP decoding, can estimate its average SNR value, and its average SNR value is lower than the threshold value that sets, and need not move the local MAP decoder of this data segment correspondence, directly skips this data segment and directly requires transmission again; 3) will use the local ARQ scheme of Yamamoto-Itoh type index to be used to have among the MAP coding/decoding method of adaptivity, if Yamamoto-Itoh type desired value is lower than certain threshold value on the data segment, then give up this data segment and require transmission again, if can be before local MAP decoding, can estimate Yamamoto-Itoh type desired value, and be lower than the threshold value that sets, and do not move this part MAP decoder, directly skip this data segment and directly requirement transmission again.

6. according to the described adaptivity turbo decoder that has of claim 1, it is characterized in that: the size of establishing the decoded Frame that comprises the tail position is L, uses M local MAP decoder, the integer of N=L/M; Local MAP decoding method for designing: 1) if i=1 uses sample sequence { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation forward based on butterfly structure, with sample sequence { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, to data bit { x ₀, x ₁..., x _M-1Carry out the MAP decoding, export the LLR value; 2) if i=N-1 or i=N use sample sequence { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sample sequence startup, to data bit { x based on butterfly structure _L-2M, x _L-M+1..., x _L-1Carry out MAP decoding, and output LLR value because the identical starting point of recurrence is backward arranged, overlaps two kinds of situations, and the calculating repetition of latter two window is arranged, and promptly latter two window is decoded simultaneously; 3) if 1＜i＜N-1 uses sample sequence { y _{2 (i-1) M}, y _{2 (i-1) M+1}..., y _{2 (i+2) M-2}, y _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sampling startup based on butterfly structure, output LLR value is to data bit { x _IM, x _IM+1.., x _{(i+1) M-1}Carry out MAP decoding.

7. high speed turbo decoder, it is characterized in that: with local MAP decoding algorithm is foundation, parallel placement by local MAP decoder comes the framework foundation, on the basis of local MAP decoder, adopt bilateral window, combination to comprise the ARQ method and the local iteration stopping method of Yamamoto-Itoh type index, with the speed of the high speed MAP decoder that improves two same compositions, and then improve the speed of high speed turbo decoder; Comprise high speed MAP decoder, the high speed turbo decoder control system of two same compositions, the data turnover system of high speed turbo decoder, the external interface of high speed turbo decoder; The high speed MAP decoder of two same compositions is separately wrong by the alternation sum reciprocal cross, each high speed MAP decoder is imported soft sampling, external information and LLR value, and each high speed MAP decoder is output as the LLR value and the external information of the high speed MAP decoder that feeds back to next same composition.

8. according to the described high speed turbo decoder of claim 7, it is characterized in that: described each high speed MAP decoder comprises the parallel work-flow corresponding to M local MAP decoder of M data segment of whole Frame.

9. according to the described high speed turbo decoder of claim 7, it is characterized in that: each local MAP decoder all has a decoding branch road scheme to confirm whether local MAP decoder should enter sleep state, promptly calculate corresponding hard or soft virtual SNR value or local quality index with input LLR value and external information, check whether virtual SNR value or local quality index surpass threshold value or arrived at asymptotic behaviour, if virtual SNR value or local quality index surpass the check threshold value or have arrived at asymptotic behaviour, the local MAP decoder of branch road then, otherwise move the computing of decoding of this part MAP decoder, here " branch road " expression directly will import LLR value and external information value as exporting LLR value and external information value, and the computing of not decoding, when local MAP decoder enters sleep state during by branch road, can not activate one at next iteration cycle and enter dormant local MAP decoder, the number that has entered dormant local MAP decoder in the high speed MAP decoder of each same composition can constantly increase along with iteration, after all local MAP decoders enter sleep state, iteration stopping and finished high speed turbo decode procedure.

10. according to the described high speed turbo decoder of claim 7, it is characterized in that: described high speed turbo decoder control system is used to control, coordinate and dispatch the various functions of each part and each part of whole high speed turbo decoder, and M local MAP decoder has an independently control system respectively; The data turnover system of described high speed turbo decoder is used to control, the turnover of coordination data, and each local MAP decoder all has a data turnover system; The external interface of described high speed turbo decoder is used for being connected and communication of this decoder and interior other parts of communication system, and each local MAP decoder all has the system with outside communication.

11. according to the described high speed turbo decoder of claim 7, it is characterized in that: when the decoded data frame length that comprises the tail bit is L, with M local MAP decoder, high speed MAP decoding method for designing is: 1) high speed MAP decoder comprises M the data segment that M local MAP decoder corresponds to whole Frame, supposes that wherein the size of all bilateral windows is equal to and the size long enough; 2) the local MAP decoder of the M in the parallel work-flow high speed MAP decoder carries out local MAP respectively to M data segment of whole Frame and decodes; 3) in high speed MAP decoder in conjunction with having the MAP decoder of adaptivity, i.e. design according to high speed MAP decoder is used in combination the ARQ scheme; The data segment that will have bad SNR value is given up the MAP decoding that is used to have adaptivity with the various ARQ schemes of transmission again, if the average SNR value of a data segment is lower than certain threshold value, then give up this data segment and require transmission again, if can be before local MAP decoding, can estimate its average SNR value, and its average SNR value is lower than the threshold value that sets, and just need not move the local MAP decoder of this data segment correspondence, directly skips this data segment and directly requires transmission again; This is based on the MAP decoding that has adaptivity of local ARQ scheme and local MAP decoder; 4) will use the local ARQ scheme of Yamamoto-Itoh type index to be used among the MAP coding/decoding method that has adaptivity based on local MAP decoder, if the minimum Yamamoto-Itoh type index on data segment is lower than certain threshold value, then gives up this data segment and require and resend; 5) decoding speed of high speed MAP decoder is by the degree of concurrence decision of local MAP decoder, if the whole parallel processings of all local MAP decoders, then high speed MAP decoder has the highest speed of service.

12. according to the described high speed turbo decoder of claim 11, it is characterized in that: if use L local MAP decoder, promptly each sample is all set up a local MAP decoder, and all parallel processings, then obtain possible maximum speed MAP decoding, if use a local MAP decoder, promptly do not adopt window algorithm fully, then be the slowest traditional MAP coding/decoding method.

13. according to the described high speed turbo decoder of claim 7, it is characterized in that: local MAP decoding method for designing: the size of establishing the decoded Frame that comprises the tail position is L, uses M local MAP decoder, the integer of N=L/M; 1) if i=1 uses sample sequence { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation forward based on butterfly structure, with sample sequence { y ₀, y ₁..., y _4M-2, y _4M-1Start recursive calculation backward based on butterfly structure, to data bit { x ₀, x ₁..., x _M-1Carry out the MAP decoding, export the LLR value; 2) if i=N-1 or i=N use sample sequence { y _2L-4M, y _2L-4M+1..., y _2L-2, y _2L-1Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sample sequence startup, to data bit { x based on butterfly structure _L-2M, x _L-M+1..., x _L-1Carry out MAP decoding, and output LLR value because the identical starting point of recurrence is backward arranged, overlaps two kinds of situations, and the calculating repetition of latter two window is arranged, and promptly latter two window is decoded simultaneously; 3) if 1＜i＜N-1 uses sample sequence { y _{2 (i-1) M}, y _{2 (i-1) M+1}..., y _{2 (i+2) M-2}, y _{2 (i+2) M-1}Start recursive calculation forward based on butterfly structure, with the backward recursive calculation of same sample sequence startup based on butterfly structure, output LLR value is to data bit { x _IM, x _IM+1..., x _{(i+1) M-1}Carry out MAP decoding.

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