CN117527045A - Method, device and receiver for receiving reverse burst data of satellite communication - Google Patents

Abstract

The invention relates to the technical field of satellite communication, and particularly provides a satellite communication reverse burst data receiving method, device and receiver. The method aims to solve the problem of resource utilization and burst data receiving efficiency of a reverse link. To this end, the method of the invention comprises: when channel data is received, obtaining data to be written and accompanying parameters according to the channel data, and writing the data to be written into an external memory according to the accompanying parameters; and acquiring a bandwidth allocation instruction packet, analyzing the bandwidth allocation instruction packet to obtain an analysis result, determining a data reading position according to the analysis result, reading burst data from the external memory according to the data reading position, and transmitting the read burst data to a baseband processing module.

Description

Method, device and receiver for receiving reverse burst data of satellite communication

Technical Field

The invention relates to the technical field of satellite communication, and particularly provides a satellite communication reverse burst data receiving method, device and receiver.

Background

In satellite communication systems, the flow of information from a master station through a satellite to a remote station is referred to as Forward Link (Forward Link) and the flow of information from a remote station through a satellite to a master station is referred to as reverse Link (Return Link). In a multi-user satellite communication system, frequency division and time division multiple access (MF-TDMA) communication is commonly used, in which a large number of users transmit data in a time-sharing manner, and the instantaneous data stream rate at the receiver side is very high, which may cause packet loss due to memory overlapping each other if not properly handled, so that in a satellite communication system based on MF-TDMA, user data of a plurality of different frequency channels needs to be properly handled. The current common method is to allocate bandwidths in advance, different users send data at allocated time according to the bandwidths allocated in advance, and a time synchronization mechanism can ensure that the data do not overlap each other when arriving at a receiver. Therefore, bandwidth allocation in the reverse channel is accomplished by the system by forward transmitting bandwidth allocation signaling packets (Bandwidth Allocation Packet, BAP). BAP is sent to multiple users by broadcast or multicast, and BAP is also sent to the receiver of the physical layer at the same time. BAP tells multiple users what time to send and how much bandwidth data to send, and also tells the receiver what time to receive the data and gathers the data to different users.

Such multi-user data reception and aggregation is very challenging at high speed transmission because of the need to compromise the relationship of multiple channels, multiple users and multiple time slots simultaneously, as well as the capability and delay of receiver signal processing, and the effect of time synchronization differences. Even more challenging, these implementations are temporarily not implemented by upper layer software, and performance requirements can only be met by Field Programmable Gate Arrays (FPGAs) or chip implementations. Therefore, it is necessary to design and implement a control logic of a circuit with reasonable structure and optimized resources, so as to improve the reverse link data receiving efficiency by improving the utilization rate of the resources, and overcome the challenges brought by broadband satellite data communication.

Disclosure of Invention

The invention aims to provide a satellite communication reverse burst data receiving method, a satellite communication reverse burst data receiving device and a satellite communication reverse burst data receiving receiver, which are used for solving the problems of resource utilization rate of a reverse link and burst data receiving efficiency.

In a first aspect, the present invention provides a method for receiving reverse burst data of satellite communication, which is applied to a reverse receiver, wherein the reverse receiver includes a baseband processing module and an external memory; the method comprises the following steps:

When channel data is received, obtaining data to be written and accompanying parameters according to the channel data, and writing the data to be written into an external memory according to the accompanying parameters;

and acquiring a bandwidth allocation instruction packet, analyzing the bandwidth allocation instruction packet to obtain an analysis result, determining a data reading position according to the analysis result, reading burst data from the external memory according to the data reading position, and transmitting the read burst data to a baseband processing module.

In one technical scheme of the satellite communication reverse burst data receiving method, the accompanying parameters include: frame number, write length per time, subchannel number and frame start address; the writing the data to be written into the external memory according to the accompanying parameters specifically comprises: and determining a data writing position according to the sub-channel number, the frame starting address and the writing length, writing the data to be written into the external memory according to the data writing position and the writing length, and storing the frame number in the accompanying parameter as a writing frame number.

The determining a data writing position according to the sub-channel number, the frame start address and the write length each time, and writing the data to be written into the external memory according to the data writing position and the write length each time may specifically include: when writing for the first time, determining an initial writing position according to the sub-channel number and the frame starting address, or directly acquiring the set initial writing position from a read-only memory, writing the data to be written into the external memory based on the initial writing position and each writing length, and determining a current offset address according to the initial writing address and each writing length; and when the writing is not performed for the first time, determining a base address according to the sub-channel number, determining a writing position according to the base address and the current offset address, writing the data to be written into the external memory based on the writing position and the writing length each time, and updating the current offset address.

Further, the obtaining the data to be written and the accompanying parameters according to the channel data specifically includes: and outputting the channel data after DDR preprocessing to obtain data to be written and an accompanying command queue, wherein the accompanying parameter is stored in the accompanying command queue. The DDR pre-processed channel data is frame-synchronized channel data. The method further comprises the following steps before the data to be written are written into the external memory: judging whether the accompanying command queue is not empty, and executing the writing of the data to be written into the external memory when the accompanying command queue is not empty.

In one technical scheme of the satellite communication reverse burst data receiving method, the analyzing the bandwidth allocation instruction packet to obtain an analysis result specifically includes: analyzing the bandwidth allocation instruction packet according to the message format of the bandwidth allocation instruction packet to obtain a frame number, a sub-channel number, the number of burst data to be read, and a user identifier and a time slot size corresponding to each burst data; determining a data type identifier according to the user identifier, and determining a time slot offset according to the time slot size; the frame number, the sub-channel number, the number of burst data to be read, the user identification corresponding to each burst data, the time slot size, the time slot offset and the data type identification are used as the obtained analysis result; and storing the user identification, the time slot size, the time slot offset and the data type identification corresponding to each burst data into a bandwidth allocation table.

Further, the determining a data reading position according to the analysis result, and reading the burst data from the external memory according to the data reading position specifically includes:

determining a base address according to the sub-channel number in the analysis result, determining a data reading position according to the base address and the time slot offset stored in the bandwidth allocation table, and determining the length of burst data to be read according to the time slot size stored in the bandwidth allocation table;

reading burst data from the external memory according to the length of the burst data to be read and the data reading position; and storing the read burst data into a data burst frame buffer.

Further, the writing of the data to be written into the external memory further includes saving a writing frame number; the method further comprises the following steps: judging whether a data reading condition is met, if yes, executing the reading burst data, otherwise, not executing the reading burst data;

the data reading conditions are specifically as follows: the frame number obtained by analyzing the bandwidth allocation instruction is matched with a stored written frame number; the residual space of the data burst frame buffer area is larger than the length of burst data to be read, the external memory stores complete burst data, and the number of the read burst data is smaller than that of the burst data to be read;

The length of the burst data to be read is determined according to the time slot size, and the number of the read burst data is obtained by accumulating the number of the burst data read each time.

In a second aspect, the present invention provides a control device, including a processor and a storage device, where the storage device is adapted to store a plurality of program codes, where the program codes are adapted to be loaded and executed by the processor to perform the method according to any one of the above technical solutions of the satellite communication reverse burst data receiving method.

In a third aspect, the present invention provides a reverse receiver, which at least comprises a baseband processing module, an external memory, and the control device.

In one technical scheme of the reverse receiver, the baseband processing module adopts a multipath parallel demodulation structure consisting of a channel processing module, a synchronous processing module and a decoding module; in the multi-path parallel demodulation structure, the number of the channel processing modules, the number of the synchronous processing modules and the number of the decoding modules are configured according to the bandwidth.

In one technical scheme of the reverse receiver, the channel processing module and the synchronous processing module interact through an arbitration management module;

And the arbitration management module is used for determining the corresponding relation between each channel processing module and each synchronous processing module.

Further, the specific implementation manner of the arbitration management module is as follows: the arbitration management module detects the frame effective marks of all channels and the number of idle bytes of the storage space of the current synchronous processing module, and when the frame effective marks of a certain channel are effective and the number of idle bytes of the storage space meets the length of a data packet transmitted by the current channel, the I/Q data transmitted by the current channel and frame parameters are distributed and output to the synchronous processing module.

In one technical scheme of the reverse receiver, the reverse receiver further comprises a data caching module and a packet arbitration module; the decoding module and the data caching module adopt a multi-path parallel structure;

the data buffer module is used for buffering the multipath decoding result output by the decoding module; the decoding result includes: a start mark, an end mark, parameters and data;

and the packet arbitration module is used for polling and detecting the decoding results cached in each data caching module, and when the complete data packet output is determined according to the decoding results, the packet is formed on the data in the data caching module corresponding to the decoding results and is output.

The technical scheme provided by the invention has at least one or more of the following beneficial effects:

in the technical scheme of implementing the invention, when channel data is received, data to be written and accompanying parameters are obtained according to the channel data, and the data to be written is written into an external memory according to the accompanying parameters; by utilizing DDR (double data rate) caching, a large amount of parallel channel data received by an air interface can be cached into the DDR rapidly, and the processing bandwidth and the reliability are effectively improved. And then the burst data can be correctly positioned to the accurate position of the burst data according to the bandwidth allocation instruction packet, the burst data is read from the DDR and is transmitted to the baseband processing module, the baseband processing of each burst data is independently processed, and the front and back of each burst data are not adhered.

In the technical scheme of the invention, in the baseband processing module part of the reverse receiver, the decoding module can properly increase and decrease the number of modules through the arbitration module according to the bandwidth and the rate requirement, so that the bandwidth can be increased and decreased very flexibly and conveniently; the arbitration management module is responsible for the arbitration management of the data interaction of the multipath channel processing module and the multipath synchronous processing module, and can appropriately increase or decrease the number of the channel processing and synchronous processing modules according to actual conditions, thereby being convenient and flexible; the packet arbitration module can configure the number of the input and output channels through configuration parameters, and simple and convenient multichannel parallel-serial conversion is realized.

Drawings

The present disclosure will become more readily understood with reference to the accompanying drawings. As will be readily appreciated by those skilled in the art: the drawings are for illustrative purposes only and are not intended to limit the scope of the present invention. Moreover, like numerals in the figures are used to designate like parts, wherein:

fig. 1 is a schematic structural diagram of a reverse satellite communication system according to an embodiment of the present application;

fig. 2 is a schematic diagram of a receiver capable of implementing a satellite communication reverse burst data receiving method according to an embodiment of the present application;

fig. 3 is a schematic diagram of a superframe structure with an exemplary 40ms frame period according to an embodiment of the present application;

fig. 4 is a flowchart of steps of a satellite communication reverse burst data receiving method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a burst taken from a 40ms frame according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a DDR read/write operation implementation designed based on the receiver architecture of FIG. 2;

FIG. 7 is a schematic diagram of a specific implementation of the DDR read and write operation section of FIG. 6;

FIG. 8 is a timing diagram of a DDR write operation interface provided in an embodiment of the present application;

Fig. 9 is a block diagram of a reverse receiver according to an embodiment of the present application;

fig. 10 is a timing diagram of a baseband input interface according to an embodiment of the present application;

fig. 11 is a schematic diagram of an implementation of a baseband processing module according to an embodiment of the present application;

FIG. 12 is a schematic diagram illustrating operation of an arbitration management module according to an embodiment of the present application;

FIG. 13 is a block diagram of an implementation of the DATA channel baseband processing provided based on FIGS. 11 and 12;

fig. 14 is a specific implementation structure diagram of processing output data of a decoding module adopting a 4-way parallel structure through a data caching module and a packet arbitration module according to an embodiment of the present application;

fig. 15 is a state control diagram of a state machine for controlling data reading and grouping in a data buffer module according to an embodiment of the present application.

Detailed Description

Some embodiments of the invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are merely for explaining the technical principles of the present invention, and are not intended to limit the scope of the present invention.

In the description of the present invention, a "module," "processor" may include hardware, software, or a combination of both. A module may comprise hardware circuitry, various suitable sensors, communication ports, memory, or software components, such as program code, or a combination of software and hardware. The processor may be a central processor, a microprocessor, an image processor, a digital signal processor, or any other suitable processor. The processor has data and/or signal processing functions. The processor may be implemented in software, hardware, or a combination of both. The term "a and/or B" means all possible combinations of a and B, such as a alone, B alone or a and B. The term "at least one A or B" or "at least one of A and B" has a meaning similar to "A and/or B" and may include A alone, B alone or A and B. The singular forms "a", "an" and "the" include plural referents.

Aiming at the high-speed data transmission of the multi-user frequency division and the time division multiplexing of the satellite communication system, the hardware control logic and the system which are reasonable in structure, flexible in configuration and resource optimization are designed and realized. The system is based on the timing sending and timing receiving Data under the system closed-loop time synchronization condition, different users set different frequency points, after channelizing, the baseband Data of different channels are output in parallel, then the Data of different channels are stored into an external storage unit (Double Data Rate SDRAM, DDR) by combining the frame head position, corresponding burst Data (burst) are intercepted according to the instruction indication of bandwidth allocation (Bandwidth Allocation Packet, BAP) at fixed time points, namely when the BAP instruction is received, because the scheme is not a blind search processing mechanism, the Data flow mode is not required to be ensured, only each burst needs to be extracted, the burst Data of different Data channels (also called frequency points) can be placed into a channel processing module for serial processing, thus the channel processing amount can be reduced, and the resource occupation Rate of an FPGA or a chip is reduced.

Fig. 1 is a schematic diagram of a reverse satellite communication system to which the present invention is applied. Taking MF-TDMA communication system as an example, on the reverse link of the system, a plurality of end users, i.e. the terminals 1 to N shown in the figure, independently transmit reverse data signals on different channels, and these reverse data signal waveforms are combined on the air interface to form air interface data, and received by the gateway side, and the signals are converted to intermediate frequency by the radio frequency unit on the gateway side. And then, the demodulation data is transmitted to the gateway upper layer through the local network after baseband receiving demodulation processing.

In an example of an application scenario of the present invention, the method for receiving reverse burst data of satellite communication provided in the embodiment of the present invention is applied to a receiver as shown in fig. 2, and as shown in fig. 2, the working principle of the receiver is as follows: at the transmitter side, it is known by the BAP instruction when and how much bandwidth data is transmitted by the multiple users, while at the receiver it is known by the BAP instruction when to receive the data and to aggregate the data to different users. The transmitter forms reverse DATA signals of all channels into air interface DATA and sends the air interface DATA to the receiver, the receiver recovers the reverse DATA signals from the received air interface DATA and processes the reverse DATA signals into channel DATA of all channels through channelizing, the channel DATA are written into the DDR cache after frame synchronization and preprocessing, and the DATA stream processing module is used for realizing the reading and writing operation of the DDR cache DATA as shown in the figure. According to the difference of the channel numbers, different storage spaces are divided in the DDR, data from different channels are correspondingly cached respectively, and the channel numbers are used as the data of the different channels to be stored in the base address of the DDR. And then, according to the BAP instruction from the DATA link layer (L2), finding the corresponding address from the DDR, reading the stored burst DATA, and sending the burst DATA to a baseband transmission module in the DATA demodulator for processing. It will be appreciated that the functions implemented for the DATA stream processing module may be implemented by programming in an FPGA or chip.

The channel data extracted from the reverse data signal in the present application adopts a periodic TDMA frame structure, and an exemplary superframe structure with a 40ms frame period is shown in fig. 3. Wherein, a super frame comprises 8 single frames, the time length is 8×40=320 ms, a single frame period is 40ms, a single frame comprises a plurality of bursts, and the number of bursts in a single frame is related to the data type of transmission.

In the application, the L2 configures a BAP instruction packet, and issues the format configuration of the BAP instruction packet in an ethernet (medium acess control, abbreviated as MAC) data packet to a physical layer, where the message format of the BAP instruction packet configured by L2 is specifically as follows:

as can be seen from the above table, the Slot Size field defined in the BAP packet specifies the Size of each Burst occupied Slot, and the burst_count field defined specifies the number of bursts, so that all bursts in one frame of data can be intercepted from the channel data in the structure shown in fig. 3 according to the BAP packet.

A detailed description will be given below of a method for receiving satellite communication reverse data according to an embodiment of the present application with reference to fig. 4, where, as shown in fig. 4, the method includes the following steps:

Step S101: when channel data is received, obtaining data to be written and accompanying parameters according to the channel data, and writing the data to be written into an external memory according to the accompanying parameters;

in this embodiment, specifically, the accompanying parameters include: frame number, write length per time, subchannel number and frame start address;

the step of writing the data to be written into an external memory according to the accompanying parameters and storing written frame numbers specifically comprises the following steps: and determining a data writing position according to the sub-channel number, the frame starting address and the writing length, writing the data to be written into the external memory according to the data writing position and the writing length, and storing the frame number in the accompanying parameter as a writing frame number.

It can be understood that the channel data includes information such as transmitted data and parameters.

In one embodiment, before writing the channel data into an external memory (DDR), the channel data may be output after undergoing DDR preprocessing by a preprocessing module to obtain data to be written and an accompanying command queue, where parameters stored in the accompanying command queue include: frame number, write-per-length, subchannel number, and frame start address. It can be understood that the channel data input to the preprocessing module for DDR preprocessing is channel data subjected to frame synchronization, in this step, the writing of the channel data into the DDR may be performed according to the accompanying command queue in specific implementation, and before the writing operation is performed, it may be determined whether the accompanying command queue is not empty, where the non-empty represents that there is data ready, and the data to be written may be obtained and written into the space corresponding to the DDR.

In this embodiment, the determining the data writing position according to the sub-channel number, the frame start address, and the length per writing, and writing the data to be written into the external memory according to the data writing position and the length per writing may specifically include: when writing for the first time, determining an initial writing position according to the sub-channel number and the frame starting address, or directly acquiring the set initial writing position from the RAM, writing the data to be written into the external memory based on the initial writing position and each writing length, and determining a current offset address according to the initial writing address and each writing length; and when the writing is not performed for the first time, determining a base address according to the sub-channel number, determining a writing position according to the base address and the current offset address, writing the data to be written into the external memory based on the writing position and the writing length each time, and updating the current offset address.

Step S102: and acquiring a bandwidth allocation instruction packet, analyzing the bandwidth allocation instruction packet to obtain an analysis result, determining a data reading position according to the analysis result, reading burst data from the external memory according to the data reading position, and transmitting the read burst data to a baseband processing module.

Specifically, in this embodiment, the data link layer may be preset to automatically issue the BAP command packet 40ms to 80ms before transmitting the channel data, so that when the physical layer receives the channel data, the BAP command packet may be obtained, and data may be read from the DDR based on the BAP command packet.

In this embodiment, the parsing the bandwidth allocation instruction packet to obtain the parsing result may specifically include:

firstly, based on the message format of the BAP instruction packet provided in the embodiment of the present application, analyzing the bandwidth allocation instruction packet may obtain a frame number, a sub-channel number, the number of burst data to be read, and a user identifier and a time slot size corresponding to each burst data; and determining a data type identifier according to the user identifier, wherein the time slot size is the burst data length to be read, and determining the time slot offset according to the time slot size. For example, if the value of the assignment_id field used for indicating the user identifier in the BAP instruction packet is greater than or equal to 1024, the data type is determined to be the data type, otherwise, the data type is determined to be the rach type, and the data type of the channel data received in the embodiment of the present application is determined to be the data type.

In addition, parameters such as an MAC address, a protocol type, a message type and the like can also be obtained by analyzing the bandwidth allocation instruction packet, and after filtering the target MAC address, whether the packet meets the type of the instruction to be processed is judged according to the protocol type and the message type.

Secondly, the frame number, the sub-channel number, the number of burst data to be read, the user identification, the time slot size, the time slot offset and the data type identification corresponding to each burst data are used as the obtained analysis result; and storing the user identification, the time slot size, the time slot offset and the data type identification corresponding to each burst data into a bandwidth allocation table.

Specifically, in this embodiment, determining the data reading position according to the analysis result, and reading the burst data from the external memory according to the data reading position may specifically be:

firstly, determining a base address according to the subchannel number in the analysis result;

then, the data reading position and the length of the burst data to be read are determined in combination with the bandwidth allocation table. Specifically: and determining a data reading position according to the base address and the time slot offset stored in the bandwidth allocation table, and determining the length of burst data to be read according to the time slot size stored in the bandwidth allocation table.

Finally, reading the burst data from the external memory according to the length of the burst data to be read and the data reading position; and storing the read burst data into a data burst frame buffer.

In a specific embodiment, each time before reading the burst data, the method further comprises: judging whether a data reading condition is met, if yes, executing the reading burst data, otherwise, not executing the reading burst data; specifically, satisfying the data reading condition means that the following conditions are simultaneously satisfied:

firstly, the residual space of a data burst frame buffer is larger than the length of burst data to be read;

specifically, the data burst frame buffer is used for storing the read burst data, so before each burst data reading, it is determined whether the burst data frame buffer has enough remaining space to store the read burst data.

The length of the burst data to be read is determined according to the time slot size, after the burst data is read each time and stored in the data burst frame buffer, the residual space of the corresponding data burst frame buffer is updated by subtracting the occupied space size of the stored burst data, so that the data in the buffer can be prevented from overflowing by design.

Second, the external memory stores the complete burst data;

generally, read-write control is performed on data read-write operation in combination with a read/write pointer table, and each read-write operation can determine a read-write position based on the content in the read/write pointer table, and according to the read/write pointer table, whether a complete burst has been written in the DDR can be judged, where the read/write pointer table is stored in a RAM (random access memory), and the DDR read/write pointer table stores a read-write address in each read-write operation, and is updated in each read-write operation, so that whether to allow the DDR to be read-written when the data is read next.

Thirdly, the number of the read burst data is smaller than the number of the burst data to be read;

in the specific implementation, the read burst number is updated every time the operation of reading the burst data is executed, the read burst number is obtained by accumulating the read burst data every time, the read burst data is compared with the burst data to be read, and when the read burst data is smaller than the burst data to be read, the fact that unread burst exists is indicated, and then the read burst data is continuously executed.

Fourth, the frame number obtained by analyzing the bandwidth allocation instruction is matched with the written frame number;

when the method is concretely implemented, writing frame numbers are stored simultaneously when data is written into DDR, after a BAP instruction packet issued by L2 is received, the BAP instruction packet is continuously stored into 3 local BAP tables through analysis, the frame numbers obtained by analyzing the BAP instruction packet each time correspond to the stored BAP tables, the frame numbers obtained by analysis are compared with the writing frame numbers, and burst data can be read from the DDR according to the corresponding BAP tables as long as matching occurs.

In a preferred implementation manner, in order to prevent incomplete burst of reading, two configurable parameters may be preset, which are respectively used to indicate the number of samples that are read multiple times at the starting position and the number of samples that are read multiple times at the ending position, for example, when burst is read each time, 16 samples are read multiple times at the starting position, 16 samples are read multiple times at the ending position, and the number of samples that are read multiple times may be configured as required. Illustratively, as shown in fig. 5, a Burst is taken from a 40ms frame, where N bursts are included in the frame, where Burst1, burst2, burst3, burst4 are Burst lengths (minimum units are Slots) specified by BAP, and Burst lengths for preventing Burst incomplete taking are taken as B1, B2, B3, B4, … …, BN.

Based on the above steps S101 to S102, it can be seen that writing data to the DDR and reading data from the DDR according to the BAP command packet in the embodiment of the present application are main contents of the present application, and the following details will be described in detail with reference to fig. 6, 7 and 8, which are specifically as follows:

as shown in fig. 6, a schematic diagram of a DDR read/write operation designed based on the receiver architecture shown in fig. 2 is shown, and as shown in fig. 6, after the multi-user channel data is channelized, frame synchronized and DDR preprocessed, the data to be written and the accompanying parameters can be obtained and stored in UB Buffer and accompanying command queues shown in the figure, respectively. And then the obtained data to be written is written into the DDR for caching according to the control logic in the DDR read-write operation part. In the embodiment of the present application, a DDR read-write operation is described as a main content, where a plurality of storage spaces are divided in the DDR, such as 2M combined DDR, 4M combined DDR, 8M combined DDR, 16M combined DDR and 32M combined DDR, each storage space corresponds to a plurality of base addresses for caching data divided according to a channel number CH ID, the DDR data is stored in units of 16-sample data blocks (UB) or frames (frames), after data to be written is written into each storage space in the DDR for caching, when a BAP instruction packet issued by L2 is acquired, the BAP instruction packet is configured as a MAC packet, parameters required for unpacking the BAP instruction packet are stored in a local BAP Buffer, and Burst data is read from the DDR according to the BAP Buffer and stored in the Burst Buffer. It can be appreciated that the Burst Buffer flow control is specifically: reading Burst data from the DDR, sequentially writing the Burst buffers, and stopping writing the Burst data from the DDR into the buffer if the Burst buffer is full, temporarily storing the data in the DDR; if Burst buffer available, reading continues from the stop point on the BAP buffer.

Further, fig. 7 is a schematic diagram showing a specific implementation manner of the DDR read/write operation part in fig. 6, and it can be seen from fig. 7 that the DDR write operation entry is data from the DDR preprocessing output in fig. 4 and an accompanying command queue, where parameters included in the accompanying command queue are: the Frame number frame_number, the write DDR length Len, the subchannel number Channeld and the Frame start address frame_start, the base address of the write DDR can be determined according to the subchannel number, and the offset address range can store data of 40ms of the whole Frame. The write enable conditions: firstly judging whether the accompanying command queue is not empty, wherein the non-empty represents that data is ready, the data can be read from the FIFO for storing the data, then the data is written into the space corresponding to the DDR, the writing length depends on a writing length parameter Len in the accompanying command queue, each writing position depends on a frame starting address and a writing address pointer value of the DDR reading/writing pointer table, and a writing pointer in the reading/writing pointer table can be updated in real time along with each writing operation. The frame number can be stored at the same time during writing operation, so that the DDR can be conveniently read and matched with the frame number indicated by the BAP. It can be understood that the DDR read-write operation part needs to be matched with a main state machine, a DDR space division table and a read/write pointer table to realize read-write control operation.

Fig. 8 is a timing diagram of a DDR write operation interface, in which Data is written into the DDR according to the timing diagram shown in fig. 8, the Data written into the DDR includes a Data portion Data and a parameter portion Cmd, wherein the parameters include a sub-channel number, a frame number, a write length per time, and a frame start address, and it can be determined which channel of Data is read according to the sub-channel number.

Further, the invention also provides a control device. In one control device embodiment according to the present invention, the control device includes a processor and a storage device, the storage device may be configured to store a program for executing the satellite communication reverse burst data receiving method of the above-described method embodiment, and the processor may be configured to execute the program in the storage device, including, but not limited to, the program for executing the satellite communication reverse burst data receiving method of the above-described method embodiment. For convenience of explanation, only those portions of the embodiments of the present invention that are relevant to the embodiments of the present invention are shown, and specific technical details are not disclosed, please refer to the method portions of the embodiments of the present invention. The control device may be a control device formed of various electronic devices.

Furthermore, the invention also provides a reverse receiver, which at least comprises the control device, a baseband processing module and an external memory DDR, and in the embodiment, the specific implementation form of the control device can be an FPGA or a chip. Based on the above method embodiment, it may be understood that the implementation of the receiver may specifically include a channelizing module, a frame synchronization module, a DDR preprocessing module, a Data stream processing module, and a baseband processing module, where the Data stream processing module includes a DDR and the control device, and a block diagram of a reverse receiver provided in this embodiment is shown in fig. 9.

The Data stream processing module is configured to write channel Data into the DDR when the channel Data is received, parse the bandwidth allocation instruction packet to obtain a parsing result when the bandwidth allocation instruction packet is acquired, determine a Data reading position according to the parsing result, read burst Data from the external memory according to the Data reading position, and transmit the read burst Data to the baseband processing module.

In this embodiment, the burst data is transmitted to the baseband processing module according to the baseband input interface timing sequence as shown in fig. 10 for processing, and one sample of data is transmitted in each period, where the transmission data includes I/Q data, a data start flag, and a data packet corresponding parameter para, and the parameters include: frame number, subchannel number, user identification, data type identification, slot size and slot offset, which are passed along with the data to L2 after processing by the baseband processing module.

In a specific implementation manner, the baseband processing module adopts a multi-channel parallel demodulation structure formed by a channel processing module, a synchronous processing module and a decoding module, wherein the number of the channel processing modules, the number of the synchronous processing modules and the number of the decoding modules are configured according to the bandwidth. Fig. 11 is a schematic diagram of an exemplary implementation of the baseband processing module provided in this embodiment, where the implementation is implemented in parallel by 4-way channel processing, in parallel by 2-way synchronous processing, and in parallel by 4-way decoding, as shown in the drawing. The whole link adopts the clock frequency of N (MHz) (generally N=200), the input baseband data is 2 times of sampling data, the maximum can support the symbol rate of N/2 (MHz), and the received data is buffered and multiplexed in the channel processing module and synchronously calculated for a plurality of times, so that the data has larger delay in the processing process, and therefore, under the condition of the clock frequency of N (MHz), the symbol rate of N/2 (MHz) can be met by a multichannel parallel processing structure.

In this embodiment of the present application, multiple accesses and synchronization computation are not required for synchronization processing data, but samples or derived samples are absorbed in the synchronization processing process, that is, a data stream that is not completely processed continuously, so that the current structure designs 2 paths of synchronization processing supporting (N/2) M symbol rates, after the synchronization processing is completed, single sampled data after downsampling is output, and the single sampled data is parallel-serial converted and combined into one path for performing subsequent processing, and when combined, the data output by each synchronization processing is stored in a buffer memory, then the data in the 2 paths of buffers are integrated into one path, and then the data is output to the 4 paths of decoding modules by adopting a polling detection method. The structure shown in fig. 11 adopts 4-way decoders to realize decoding, and can support maximum (N/2) M symbol rate, because each way of decoder has iterative computation in the decoding process, a large processing delay can be generated in the iterative computation process, and the decoding module part designs parallel 4-way decoders to realize in consideration of the maximum symbol rate to be supported.

The design structure shown in fig. 11 can also support any bandwidth smaller than the (N/2) M symbol rate, and by calculating the number of channel processing modules, the number of synchronous processing modules and the number of decoding modules required by the bandwidth, the parallel number of each processing module can be changed arbitrarily in the concrete implementation, and only equivalent modules need to be deleted or added in parallel in the changing process.

Based on the structure of the baseband processing module provided in the embodiments of the present application, in a specific implementation manner, interaction is performed between the channel processing module and the synchronization processing module through an arbitration management module; referring to fig. 12, the working principle of the arbitration management module provided in this embodiment is shown, based on the structure of the baseband processing module shown in fig. 11, as the arbitration management module shown in fig. 12, for determining the correspondence between each channel processing module and each synchronization processing module, where the channel processing module 1 and the channel processing module 3 apply for transmitting data to the synchronization processing module 1, the channel processing module 2 and the channel processing module 4 apply for transmitting data to the synchronization processing module 2, and the shown arbitration management module may be used to implement the application of each channel processing module, and transmit the data of each channel processing module to the synchronization processing module corresponding to the application. The specific implementation manner of the arbitration management module for realizing the functions is as follows: the arbitration management module detects the frame effective mark of each channel and the number of idle bytes of a storage space (FIFO) of the current synchronous processing module, and when the frame effective mark of a certain channel is effective and the number of the idle bytes of the FIFO meets the length of a data packet transmitted by the current channel, the I/Q data transmitted by the current channel and frame parameters are distributed and output to the synchronous processing module for subsequent processing. Taking the channel processing module 1 and the channel processing module 3 as an example for applying transmission, detecting the frame effective marks of the channel 1 and the channel 3 and the FIFO idle byte number of the current synchronous processing module, when a certain channel frame effective mark is effective and the FIFO idle byte number meets the length of a data packet of the current channel, distributing and outputting the transmission data corresponding to the frame effective mark to the synchronous processing module for subsequent processing, and when the channel 1 and the channel 3 meet simultaneously, preferentially transmitting the data of the channel processing module 1 to the synchronous processing module 1. It can be appreciated that, based on the design architecture of the baseband processing module provided in fig. 11 and fig. 12, the embodiment of the present application may obtain a DATA channel baseband processing implementation block diagram as shown in fig. 13.

In a specific implementation manner, the receiver provided in the embodiment of the present application further includes a data buffering module and a packet arbitration module, where an output of a decoding module in the baseband processing module is connected to the data buffering module, and correspondingly, the decoding module and the data buffering module adopt a multipath parallel structure. Fig. 14 is a specific implementation structure diagram of processing output data of a decoding module with a 4-way parallel structure through a data buffer module and a packet arbitration module, wherein the processing of the data by the 1-way decoding module and the output decoding result correspond to a decoding 1 and an output Burst start flag 1, a Burst end flag 1, a Burst corresponding parameter 1 and a Burst corresponding bit data 1 shown in the figure, and the like to obtain the output of the 4-way decoding module, then the output of the 4-way decoding module is respectively transmitted to the 4 data buffer modules to perform data buffer 1 to data buffer 4, and then the packet arbitration module performs packet grouping and arbitration combination on the 4-way data buffer to obtain one-way output data. As can be seen from the structure shown in fig. 14, the multiple decoding results outputted by the multiple decoding modules are first data buffered by the multiple data buffering modules, and then packed by the packing arbitration module to combine the multiple decoding results into one path for output. Specific:

The data buffer module is used for buffering the multipath decoding result output by the decoding module; the decoding result includes: start flag, end flag, parameter, data

And the packet arbitration module is used for polling and detecting the decoding results cached in each data caching module, and when the complete data packet output is determined according to the decoding results, the packet is formed on the data in the data caching module corresponding to the decoding results and is output.

The method comprises the steps of respectively caching an end mark, parameters and data of a data packet in a data caching module, caching the end mark by using a 1bit FIFO of 1024depth (depth), caching the parameters by using an 8bit FIFO of 512depth, caching the data by using an 8bit FIFO of 4096depth, then polling and detecting the data in each data caching module by a packet arbitration module, and when a certain path of data packet is detected to be required to be output, performing MAC packet on the cached corresponding data and outputting the data to an optical port.

The input and output of the packet arbitration module can be configured through configuration parameters, and the data reading and packet grouping can be controlled through a state machine according to the process of polling and detecting each data buffer module and reading out the buffered data by the configuration packet arbitration module. In a specific implementation, the state machine is provided with six states, specifically as follows:

IDLE, initializing.

Rd_end: and the read end mark is 1bit, and when the data packet end mark exists in the data buffer module, the read end mark indicates that a complete burst is stored, and data can be read from the buffer for packing.

Rd_parameter: the read parameters, the read length is fixed. Because the parameter length of each packet is fixed bytes.

RD_DATA: and reading the data packet, and knowing the length of the data packet to be read according to the modulation mode parameter information corresponding to the data packet.

Rd_fcs: corresponding check bits, 4 bytes, may be padded, or full F may be padded.

HOLD, set wait for several clock counts, then jump to IDLE state, in order to protect the integrity of the data packet.

The state control implemented based on the state machine described above is shown in fig. 15. The state machine is in an IDLE state initially, then the empty signals corresponding to the DATA packet END marks stored in the four DATA buffer modules are judged in a polling mode, if the empty signals are not empty, the state machine jumps to an RD_END state, the 1-bit DATA packet END mark is read, then the state machine jumps to an RD_PARAMETER state reading PARAMETER, when the PARAMETER corresponding to one DATA packet is read, the state machine jumps to an RD_DATA state, when a complete DATA packet is read, the state machine jumps to an RD_FCS state, when filling of FCS check bits is completed, the state machine jumps to a HOLD waiting state, and when the waiting state is reset, the state machine jumps to an IDLE state.

It will be appreciated by those skilled in the art that the present invention may implement all or part of the above-described methods according to the above-described embodiments, or may be implemented by means of a computer program for instructing relevant hardware, where the computer program may be stored in a computer readable storage medium, and where the computer program may implement the steps of the above-described embodiments of the method when executed by a processor. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable storage medium may include: any entity or device, medium, usb disk, removable hard disk, magnetic disk, optical disk, computer memory, read-only memory, random access memory, electrical carrier wave signals, telecommunications signals, software distribution media, and the like capable of carrying the computer program code. It should be noted that the computer readable storage medium may include content that is subject to appropriate increases and decreases as required by jurisdictions and by jurisdictions in which such computer readable storage medium does not include electrical carrier signals and telecommunications signals.

Further, it should be understood that, since the respective modules are merely set to illustrate the functional units of the apparatus of the present invention, the physical devices corresponding to the modules may be the processor itself, or a part of software in the processor, a part of hardware, or a part of a combination of software and hardware. Accordingly, the number of individual modules in the figures is merely illustrative.

Those skilled in the art will appreciate that the various modules in the apparatus may be adaptively split or combined. Such splitting or combining of specific modules does not cause the technical solution to deviate from the principle of the present invention, and therefore, the technical solution after splitting or combining falls within the protection scope of the present invention.

Thus far, the technical solution of the present invention has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present invention is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present invention, and such modifications and substitutions will fall within the scope of the present invention.

Claims (10)

1. A satellite communication reverse burst data receiving method is applied to a reverse receiver, and is characterized in that: the reverse receiver comprises a baseband processing module and an external memory; the method comprises the following steps:

when channel data is received, obtaining data to be written and accompanying parameters according to the channel data, and writing the data to be written into an external memory according to the accompanying parameters;

and acquiring a bandwidth allocation instruction packet, analyzing the bandwidth allocation instruction packet to obtain an analysis result, determining a data reading position according to the analysis result, reading burst data from the external memory according to the data reading position, and transmitting the read burst data to a baseband processing module.

2. The method of claim 1, wherein the companion parameters include: frame number, write length per time, subchannel number and frame start address;

the writing the data to be written into the external memory according to the accompanying parameters specifically comprises: and determining a data writing position according to the sub-channel number, the frame starting address and the writing length, writing the data to be written into the external memory according to the data writing position and the writing length, and storing the frame number in the accompanying parameter as a writing frame number.

3. The method according to claim 1, wherein the parsing the bandwidth allocation instruction packet to obtain a parsing result specifically includes:

analyzing the bandwidth allocation instruction packet according to the message format of the bandwidth allocation instruction packet to obtain a frame number, a sub-channel number, the number of burst data to be read, and a user identifier and a time slot size corresponding to each burst data; determining a data type identifier according to the user identifier, and determining a time slot offset according to the time slot size;

the frame number, the sub-channel number, the number of burst data to be read, the user identification corresponding to each burst data, the time slot size, the time slot offset and the data type identification are used as the obtained analysis result; and storing the user identification, the time slot size, the time slot offset and the data type identification corresponding to each burst data into a bandwidth allocation table.

4. The method according to claim 3, wherein the determining a data reading position according to the analysis result, and the reading burst data from the external memory according to the data reading position is specifically:

determining a base address according to the sub-channel number in the analysis result, determining a data reading position according to the base address and the time slot offset stored in the bandwidth allocation table, and determining the length of burst data to be read according to the time slot size stored in the bandwidth allocation table;

And reading the burst data from the external memory according to the length of the burst data to be read and the data reading position, and storing the read burst data into a data burst frame buffer area.

5. The method of claim 4, wherein writing the data to be written to an external memory further comprises storing a write frame number; the method further comprises the following steps: judging whether a data reading condition is met, if yes, executing the reading burst data, otherwise, not executing the reading burst data;

the data reading conditions are specifically as follows: the frame number obtained by analyzing the bandwidth allocation instruction packet is matched with the stored written frame number; the residual space of the data burst frame buffer area is larger than the length of burst data to be read; and the external memory stores complete burst data; the number of the read burst data is smaller than the number of the burst data to be read;

and determining the length of the burst data to be read according to the time slot size, wherein the number of the read burst data is obtained by accumulating the number of the burst data read each time.

6. A control device comprising a processor and a storage device, the storage device being adapted to store a plurality of program codes, characterized in that the program codes are adapted to be loaded and executed by the processor to perform the satellite communication reverse burst data reception method of any one of claims 1 to 5.

7. A reverse receiver, characterized by: the reverse receiver comprises at least a baseband processing module, an external memory and the control device of claim 6.

8. The receiver according to claim 7, wherein the baseband processing module adopts a multi-channel parallel demodulation structure consisting of a channel processing module, a synchronous processing module and a decoding module;

in the multi-path parallel demodulation structure, the number of the channel processing modules, the number of the synchronous processing modules and the number of the decoding modules are configured according to the bandwidth.

9. The reverse receiver of claim 8 wherein the channel processing module and the synchronization processing module interact with each other through an arbitration management module;

and the arbitration management module is used for determining the corresponding relation between each channel processing module and each synchronous processing module.

10. The reverse receiver of claim 8 further comprising a data buffering module and a packet arbitration module; the decoding module and the data caching module adopt a multi-path parallel structure;

the data buffer module is used for buffering the multipath decoding result output by the decoding module;

And the packet arbitration module is used for polling and detecting the decoding results cached in each data caching module, and when the complete data packet output is determined according to the decoding results, the packet is formed on the data in the data caching module corresponding to the decoding results and is output.