KR101385439B1 - Method for transferring between fpga and dsp connected with srio interface - Google Patents

Abstract

The present invention relates to a method for transmitting data between FPGA and DSP which are connected through an SRIO interface, wherein the method enables a stable and efficient transmission of data from FPGA and DSP using mix of a scheduling method and an interrupt method in a system where FPGA and DSP are connected through the SRIO interface. In the method for transmitting data of the present invention, the transmission of data between FPGA and DSP which are connected through an SRIO interface is performed by FPGA. And the method comprises step (a) of receiving an event table, which includes a data transmission schedule, from the DSP and storing the event table; step (b) of executing each event recorded in the event table and transmitting the data of the event to the DSP; step (c) of transmitting a doorbell message which includes information on types of the data transmitted to the event after executing each event in step (b); step (d) of receiving decoded data from an internal decoding block and delivering the decoded data to the DSP when a writing interrupt is occurred by the internal decoding block; and step (e) of transmitting the doorbell message, which includes information on types of the decoded data, to the DSP. [Reference numerals] (AA) Start; (BB) End; (S30) Event table received?; (S32) Updating and storing the event table; (S34) Executing the event table; (S36) Symbol interruption generated?; (S38) Data to be transmitted exists?; (S40) At least 256 byte?; (S42) Separating into 256 byte; (S44) Transmitting in 256 byte-unit; (S46) The event ended?; (S48,S56) Transmitting a doorbell; (S50) The Event of the symbol ended?; (S52) Writing operation interruption generated?; (S54) Transmitting the data; (S58) Executing the entire event table?

Description

Method for transferring between FPGA and DSP connected with SRIO interface

The present invention relates to a method of transferring data between an FPGA and a DSP connected through an SRIO interface. In particular, the present invention relates to a method of transferring data from an FPGA to a DSP stably and efficiently by using a scheduling method and an interrupt method in a system in which an FPGA and a DSP are connected through an SRIO. It is about data transfer between FPGA and DSP connected by one SRIO interface.

Recently, new standards have been proposed as part of the ongoing evolution of radio access technologies for improved spectrum efficiency, service enhancements and cost savings, one of which is the long-term evolution from 3GPP, which seeks to strengthen UMTS wireless networks. Long Term Evolution (LTE) standard. Currently, the LTE technology is widely commercialized in Korea, and the rapid introduction of LTE-A (Advanced), which is higher than LTE, is being considered.

On the other hand, in order to develop a mobile terminal or base station equipment according to the above-mentioned standard, various test equipment or measurement equipment for testing its performance is required. One kind of test equipment includes a base station emulator. The base station emulator refers to test equipment that operates as a base station between mobile terminals and transmits a downlink signal to the mobile terminal and receives an uplink signal from the mobile terminal to perform various types of analysis. Such a base station emulator includes a baseband processing apparatus for generating a baseband signal for a downlink signal and performing baseband signal analysis for an uplink signal, and typically, one or more field programmable gate arrays (FPGAs). And a plurality of digital signal processors (DSPs) for high speed computation. FPGAs and DSPs are typically connected to Serial RapidIO IP (SRIO), a serial high-speed IO interface provided by Xilinx.

As is well known, SRIO's Intellectual Property (IP) core consists of a Physical Layer, a Buffer, and a RapidIO Logical Layer, of which the RapidIO Logical Layer is an Initiator Request, Initiator Response, Target. It includes four ports (interfaces) consisting of Request and Target Response.

Through these four ports, SRIO performs various operations such as Read (NREAD), Write (NWRITE), Streaming Write (SWRITE), Write with Response (NWRITE_R), Data Messaging, and Doorbell. The DSP reads the FPGA's data using the NREAD operation.

1 is a diagram illustrating a flow of NREAD operation in a base station emulator having an FPGA and a DSP connected to a conventional SRIO. As shown in FIG. 1, the conventional DSP 10 uses an FPGA (PGA) through its SRIO endpoint 12 to process desired data, for example, a physical uplink control channel (PUCCH) under self-directed control. After the NREAD is transmitted to the 20), it waits for reception without any other work. The FPGA 20 reads the corresponding data from the memory of the user setting area 24 and then the DSP 10 through the SRIO endpoint 22. Will be sent).

FIG. 2 is a graph illustrating a time elapsed until a conventional DSP receives a response (RESP) after transmitting an NREAD to an FPGA. As shown in FIG. 2, it takes approximately 3 ms until the NREAD for the desired data from the conventional DSP 10 reaches the FPGA 20, and then the response (RESP) from the FPGA 20 is sent to the DSP 10. It takes approximately 3.5 ms to be received.

As a result, it takes approximately 6.5 ms for the DSP 10 to request and receive the desired data from the FPGA 20, during which the DSP 10 remains idle without performing any other operations, resulting in faster transfer rates. There was a problem that can not easily meet the requirements of the LTE-A support.

FIG. 3 is a diagram for describing a process of transmitting a large amount of data to a DSP by a conventional FPGA using a WRITE operation. As shown in FIG. 3, it may be considered that the FPGA 20 transmits a large amount of data to the DSP 10 at once using the WRITE operation without any scheduling in order to reduce processing latency of the DSP. There is a problem in that the DSP cannot perform normal operation due to resource limitations such as DSP internal memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the SRIO interface enables a stable and efficient data transmission from the FPGA to the DSP by using a scheduling method and an interrupt method in a system in which the FPGA and the DSP are connected through the SRIO. It aims to provide a data transfer method between FPGAs and DSPs.

The data transmission method of the present invention for achieving the above object is performed by the FPGA in transmitting data between the FPGA and the DSP connected to the SRIO interface, and receives and stores an event table containing the data transmission schedule from the DSP (a) step; (B) executing each event recorded in the event table and transmitting data of the corresponding event to the DSP; (C) transmitting a doorbell message containing information on the type of data transmitted to the corresponding event after executing each event in step (b); When a write operation interrupt is generated by an internal decoding block, a doorbell message including type information of the decoded data is received after the steps (d) and (d) of receiving the decoded data from the decoding block. (E) delivering the DSP to the DSP.

In the above configuration, step (a) is characterized in that it is performed for each subframe of the LTE system.

In the step (b), when the length of data to be transmitted in each event is 256 bytes or more, the data is divided and transmitted in units of 256 bytes.

The data may be transmitted to the DSP in synchronization with a symbol interrupt generated for every symbol.

When the data request interrupt is received from the DSP through the GPIO interface, the corresponding data is transmitted through the SRIO interface.

According to the data transmission method between the FPGA and the DSP connected to the SRIO interface of the present invention, the DSP and the DSP are connected to each other through the SRIO interface by using a scheduling scheme and an interrupt scheme to transfer the data stably and efficiently from the FPGA to the DSP. It is possible to shorten the processing latency of up to 53%, thereby fully supporting the base station emulator function of LTE_A having a higher transmission rate.

1 is a diagram illustrating a flow of NREAD operations in a base station emulator having an FPGA and a DSP connected to a conventional SRIO.
2 is a graph illustrating the time elapsed until a conventional DSP receives a response (RESP) after transmitting an NREAD request to an FPGA.
3 is a diagram illustrating a process in which a conventional FPGA transmits a large amount of data to a DSP using a WRITE operation.
4 illustrates a communication interface between a DSP and an FPGA in a base station emulator in which the method of the present invention may be implemented.
Figure 5 is a flow chart illustrating the operation of the DSP in the data transfer method between the FPGA and DSP connected to the SRIO interface of the present invention.
Figure 6 is a flow chart illustrating the operation of the FPGA in the data transfer method between the FPGA and DSP connected to the SRIO interface of the present invention.
7 is a state machine diagram for explaining the operation of the FPGA in the data transfer method between the FPGA and DSP connected to the SRIO interface of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of a data transmission method between the FPGA and the DSP connected to the SRIO interface of the present invention.

In the current LTE standard, one radio frame is 10 ms and one radio frame is composed of 10 subframes, and one subframe is composed of two slots of 0.5 ms. One slot can contain seven symbols (in the case of the Cyclic Prefic) or six symbols (in the case of the Extended CP) on the time axis, so that one subframe can contain a total of 14 or 12 symbols. do.

4 illustrates a communication interface between a DSP and an FPGA in a base station emulator in which the method of the present invention may be implemented. As shown in FIG. 4, the base station emulator in which the method of the present invention can be implemented has a general purpose input & output (GPIO) while the DSP 10 'and the FPGA 20' are connected to the SRIO interface as described above. In this connection, interrupt signals can be transferred between the DSP 10 'and the FPGA 20' through the GPIO. The transmission processing block of the FPGA 20 'for carrying out the method of the present invention may be largely comprised of an event table, a data separator, and a state machine, which will be described later.

FIG. 5 is a flowchart illustrating an operation of a DSP in a data transmission method between an FPGA and a DSP connected to an SRIO interface of the present invention, and may be repeatedly performed in every subframe. As shown in FIG. 5, according to the data transmission method between the FPGA and the DSP connected to the SRIO interface of the present invention, the periodically generated data is the data at the nth LTE symbol number determined according to the scheduling set by the DSP 10 ′. In addition to the non-periodic data or other data can be transmitted by the interrupt method through the FPGA (20 ') or GPIO.

To this end, the DSP 10 'generates an event table for data transmission every subframe. Table 1 below is based on the event table generated by the DSP 10' and transmitted to the FPGA 20 '. As an example of an event table for data transmission set in (20 '), the event table includes an event number (Event #), a start address (Start add.) Of a memory storing data to be transmitted, and a length (Length (byte)) of the corresponding data. Symbol number (Symbol #) of the corresponding data.

PUCCH, SR (Scheduling Request), Channel Quality Indicator / Physical Uplink Shared Channel (CQI / PUSCH), HI (High Interference Indicator), Rank Indication (RI), Sounding Reference Symbol (SRS) And a PRACH (Physical Random Access Channel) may be data that is fixed in length and periodically generated, and a PUSCH (Physical Uplink Shared Channel) may be data that is generated aperiodically because its length is variable. In the example of Table 1, the FPGA 20 'is composed of "4800" bytes and transmits a SRS (Sounding Reference Signal) to the DSP 10' for the sixth event.

5 again, in step S12 the DSP 10 'transfers the table generated in step S10 to the FPGA 20' via SRIO before the start of every subframe, and in step S14 another task, for example, the next subframe. Performs tasks such as scheduling and creating various parameters. Of course, if there is data received from the FPGA 20 'in this process, it is stored in its SRIO buffer.

Next, in step S16, it is checked whether a doorbell message is received from the FPGA 20 '. Doorbell messages are used to convey a small amount of information on the SRIO interface. These doorbell message packets consist of a small amount of 16 bits of data and do not contain a data payload, so Doorbell messages will be included directly. When the doorbell message is used, the SRIO core of the DSP 10 'is interrupted to inform the DSP 10' that the doorbell message has been transmitted from the FPGA 20 '. Transmits the data of a specific event and transmits the data type information, for example, the event number, to the DSP 10 'in a doorbell message so that the DSP 10' can check and perform a corresponding operation. Will be.

As a result of the check in step S16, if the doorbell message interrupt has not occurred, the process returns to step S14, whereas in case of occurrence, the process proceeds to step S18 to process the data received immediately before.

Next, in step S20, a GPIO interrupt is generated to check whether a request for transfer of any data previously promised with the FPGA is requested. As such, when the DSP 10 'wants to receive other data not included in the event table from the FPGA 20', the DSP 10 'requests the other data from the FPGA 20' in an interrupt manner through a GPIO interface. In S22, after the request, the data is received and processed from the FPGA 20 '.

In step S24, it is checked whether or not the current subframe has ended. If not, the process returns to step S14. In case of completion, the step S10 or less is repeated for the next subframe.

FIG. 6 is a flowchart illustrating an operation of the FPGA in the data transmission method between the FPGA and the DSP connected to the SRIO interface of the present invention, and may be repeatedly performed in every subframe. As shown in FIG. 6, first, in step S30, it is checked whether an event table has been received from the DSP 10 '. If it is not received, step S30 is repeated, whereas in step S30, the process proceeds to step S32. Update and save the event table as described.

Next, in step S34, the stored event table is executed. In step S36, it is checked whether a symbol interrupt has occurred.

7 is a state machine diagram for explaining the operation of the FPGA in the data transfer method between the FPGA and the DSP connected to the SRIO interface of the present invention. As shown in Fig. 7, the state machine according to the method of the present invention has five states, namely, initial state (0), symbol interrupt state (1) and its write state (2) and write operation interrupt state (3). And its write state (4).

In the above-described configuration, it is waiting (00) for the generation of an interrupt in the initial state (0), and then proceeds to the symbol interrupt state (1), for example, when a rising edge of the symbol synchronization signal is detected. Done.

Next, in the symbol interrupt state (1), if there is no event corresponding to the current symbol number, for example, if the current symbol number in Table 1 is 0, 1, 3, 4, 6, 7, or 9, the initial state is reset. If returning to (0) (10) while there is an event corresponding to the current symbol number, for example, if the current symbol number is 5 in Table 1, the write operation of the corresponding event is executed (12). . In this process, when the length of the corresponding data is more than 256 bytes, it is divided into 256 byte lengths, that is, divided into 256 byte length packet units and transmitted. This is because the maximum length of data that SRIO can transmit in one packet is 256 bytes.

On the other hand, while writing is in progress in the write state (2), the write completion interrupt signal is waited (22), and when the write completion interrupt signal is generated, that is, when the write operation of the current event is completed, the symbol number and the current symbol number of the next event are completed. Checks for a match. As a result of the check, if it does not match, it returns to the initial state (0) (20) to process the next symbol, while if there is a match, for example, it is assigned to symbol 5 of event 4 immediately before in Table 1 If it is necessary to process the HI data and further process the RI and SRS data allocated to the same symbol # 5, the process returns to the symbol interrupt state 1 again to continue processing the data for the current symbol number. As described above, according to the method of the present invention, a symbol interrupt may be generated in symbol units.

On the other hand, in the case of the PUSCH in which the symbol number allocated to the data length varies, the decoding block (not shown) of the FPGA 20 'generates an interrupt, that is, a write operation interrupt, in the transmission processing block when the decoding ends. 03). Thus, a state transition is made from the initial state (0) to the write operation interrupt (3). Then, in the write operation interrupt state (0), the state transition is made to the write state (4) by transmitting 34 the data received from the decoding block to the DSP 10 '. Return to state (0) (40).

Referring to FIG. 6, in step S36 of FIG. 6, it is checked whether a symbol interrupt has occurred. If it does not occur, step S36 is repeatedly performed. Check if it exists. As a result of the check in step S38, if there is data to be transmitted, step S40 is performed again to check whether the data is 256 bytes or more.

As a result of the check in step S40, if the data to be transmitted is 256 bytes or more, steps S42 and S44 are performed to separate the data by 256 bytes for transmission. Next, in step S46, it is checked whether the corresponding event has ended. If the process ends, the process proceeds to step S48, and when the doorbell message is transmitted, the process returns to step S40.

Next, in step S50, it is checked whether all the events of the symbol are finished. If all of the events of the symbol are not finished, the process returns to step S40. If all of the symbols are terminated, the process returns to step S52. Check if it occurred. As a result of the check in step S52, if a write operation interrupt has occurred, go to step S54 to transmit the corresponding data, and immediately after the transfer is completed, proceed to step S56 to send the doorbell message and then proceed to step S58 while writing If no operation interrupt has occurred, the flow proceeds directly to step S58 to check whether the event table is fully executed. Of course, if the data to be transmitted in step S54 exceeds 256 bytes, 256 bytes are separated and transmitted as described above.

As a result of the check in step S58, when all the event tables are not executed, the process returns to step S36, whereas when all of the event tables are executed, step S30 is repeatedly performed for the next subframe.

As described above, according to the data transmission method between the FPGA and the DSP connected to the SRIO interface of the present invention, the waiting time generated whenever the DSP 10 'reads data from the FPGA 20' can be reduced, and the FPGA 20 ' Interrupts can be interrupted and processed as soon as the data processed by) is significantly reduced, significantly reducing the processing time required to read data from the FPGA through the SRIO interface.

In the above, preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, which are merely exemplary and various modifications and changes are possible within the scope of the technical idea of the present invention. Therefore, the scope of the present invention will be defined by the description of the claims below.

10, 10 ': DSP, 20, 20': FPGA

Claims (5)

Performed by the FPGA in transferring data between the FPGA and the DSP connected via the SRIO interface,
(A) receiving and storing an event table containing a data transmission schedule from a DSP;
(B) executing each event recorded in the event table and transmitting data of the corresponding event to the DSP;
(C) transmitting a doorbell message containing information on the type of data transmitted to the corresponding event after executing each event in step (b);
(D) receiving the decoded data from the decoding block and transmitting the decoded data to the DSP when a write operation interrupt is generated by an internal decoding block; and
And (e) transferring a doorbell message containing the type information of the decoded data to a DSP after the step (d). The method according to claim 1,
The step (a) is performed for each subframe of the LTE system, the data transmission method between the FPGA and the DSP connected to the SRIO interface. 3. The method of claim 2,
If the length of the data to be transmitted to each event in step (b) is more than 256 bytes, the data transmission method between the FPGA and the DSP connected to the SRIO interface, characterized in that for transmitting in 256 bytes. 3. The method of claim 2,
And transmitting the data to a DSP in synchronization with a symbol interrupt generated for each symbol. 5. The method according to any one of claims 2 to 4,
A method of transferring data between an FPGA and a DSP connected to an SRIO interface, in which the corresponding data is transmitted through SRIO when an interrupt request for arbitrary data is received from the DSP through the GPIO interface.

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