CN117525142A - Logic transistor and memory - Google Patents

Logic transistor and memory Download PDF

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Publication number
CN117525142A
CN117525142A CN202311387915.8A CN202311387915A CN117525142A CN 117525142 A CN117525142 A CN 117525142A CN 202311387915 A CN202311387915 A CN 202311387915A CN 117525142 A CN117525142 A CN 117525142A
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gate
logic
logic transistor
electrode
channel control
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戴明志
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Ningbo Institute of Material Technology and Engineering of CAS
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Ningbo Institute of Material Technology and Engineering of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Abstract

The present disclosure provides a logic transistor and a memory, wherein the logic transistor includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; at least one first trench partially within the semiconductor layer, and at least one second trench extending into the semiconductor layer; a gate stack located within the first trench; the gate stack comprises a gate dielectric layer covering the bottom and the side walls of the first trench and a gate conductor wrapped by the gate dielectric layer; an isolation layer between the gate conductor and the semiconductor layer, the isolation layer comprising a material having a memory effect; a channel control electrode located inside the second trench and in contact with the semiconductor layer to extract local electrical properties of the channel as an output electrode; the part of the semiconductor layer between the first groove and the second groove is formed into a channel region of the logic transistor, the gate conductor is an input end of the logic transistor, and the channel control electrode is an output end of the logic transistor.

Description

Logic transistor and memory
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a logic transistor and a memory.
Background
Transistors, which are solid state semiconductor devices, can be used for detection, rectification, amplification, switching, voltage regulation, signal modulation, and many other functions. The transistor is used as a variable switch, and the current flowing out is controlled based on the input voltage, so the transistor can be used as a switch of the current, and the difference between the transistor and a common mechanical switch is that the transistor is controlled by an electric signal, the switching speed can be very fast, and the switching speed in a laboratory can reach more than 100 GHz.
However, in the prior art, as shown in fig. 1, the window of the threshold voltage generated by the transistor is small, which results in low reading accuracy when the transistor is used as a memory cell. And the memory state is not multi-state, and 0 and 1 correspond to a single current-voltage curve respectively. At present, a single structure can only have one logic function under the same set of voltage conditions under the same storage state.
Disclosure of Invention
The present disclosure provides a logic transistor and a memory to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, there is provided a logic transistor comprising:
a semiconductor substrate;
a semiconductor layer on the semiconductor substrate;
At least one first trench partially within the semiconductor layer, and at least one second trench extending into the semiconductor layer;
a gate stack located within the first trench; the gate stack comprises a gate dielectric layer covering the bottom and the side walls of the first trench and a gate conductor wrapped by the gate dielectric layer;
an isolation layer between the gate conductor and the semiconductor layer, the isolation layer comprising a material having a memory effect;
a channel control electrode located inside the second trench and in contact with the semiconductor layer to extract local electrical properties of the channel as an output electrode; wherein,
the portion of the semiconductor layer between the first trench and the second trench is formed as a channel region of the logic transistor, the gate conductor is an input terminal of the logic transistor, and the channel control electrode is an output terminal of the logic transistor.
In an embodiment, the isolation layer is located between the gate conductor and the semiconductor layer, comprising: the isolation layer is located between the gate conductor and the gate dielectric layer, and/or the isolation layer is located inside the gate dielectric layer, and/or the isolation layer is located between the gate dielectric layer and the semiconductor layer.
In an embodiment, the material of the isolation layer includes at least one of ferroelectric material, phase change material, magneto-electric material, quantum effect material, resistive effect material, memory material, semiconductor material, superconducting material, conductor material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, silicide.
In one embodiment, the logic transistor further includes:
a conductor region in the semiconductor layer; wherein,
the semiconductor substrate and the conductor region are formed as a source region and a drain region of the logic transistor, respectively.
In one embodiment, the logic transistor further includes:
a first insulating layer covering the channel control electrode and located at an upper portion of the second trench; wherein,
the top surface of the channel control electrode is lower than the bottom surface of the drain region, and the first insulating layer isolates the channel control electrode from the drain region.
In one embodiment, the logic transistor further includes:
a second insulating layer on the conductor region;
a drain electrode, a gate electrode, and a control gate electrode on the second insulating layer, and a source electrode on a surface of the semiconductor substrate remote from the semiconductor layer; wherein,
The drain electrode is electrically connected with the drain region, the gate electrode is electrically connected with the gate conductor, the control gate electrode is electrically connected with the channel control electrode, and the source electrode is electrically connected with the source region.
In one embodiment, the gate conductor is an input terminal of the logic transistor, the channel control electrode is an output terminal of the logic transistor, and the method includes:
the gate connected to the gate conductor is an input electrode of the logic transistor, and the control gate connected to the channel control electrode is an output electrode of the logic transistor.
In an embodiment, the channel control electrode is located inside the second trench, and includes: the channel control electrode is located at a lower portion of the second trench.
In one embodiment, the gate stack includes one gate stack, and the logic transistor is operated as a not gate structure according to a result of performing a logic operation on a signal of an input terminal of the one gate stack.
In one embodiment, the gate stack includes a plurality of gate stacks, and the logic transistor is selectively operated as any one of a dual input logic gate, a multiple input logic gate, a dual output logic gate, and a multiple output logic gate structure according to a result of performing a logic operation on signals of input terminals of the plurality of gate stacks.
In an embodiment, the logic transistor is selectively operated as any one of a dual input logic gate, a multiple input logic gate, a dual output logic gate, and a multiple output logic gate structure, including: and enabling the logic transistor to realize any one of NOR, NAND, OR, AND, OR and XOR logic functions.
In an embodiment, the at least one portion is located in a first trench in the semiconductor layer, including:
the first trench extends through the semiconductor layer and into the semiconductor substrate, or,
the first trench extends into the semiconductor layer.
In one embodiment, the channel control region electrode comprises one channel control electrode at least partially surrounding the gate stack to obtain a predetermined junction area.
In an embodiment, the channel control electrode includes a plurality of channel control electrodes spaced around the gate stack and respectively contacting the semiconductor layer to form a plurality of junction capacitances.
In an embodiment, the at least one channel control electrode is comprised of any stack selected from a conductor, a semiconductor, or a conductor and a semiconductor.
In an embodiment, the channel control electrode is formed by doping, deposition, epitaxy, self-assembly, spin-coating, self-assembly, roll-to-Roll, hydrothermal, embossing, rolling, printing, or evaporation.
According to a second aspect of the present disclosure, there is provided a memory comprising a logic transistor as in any of the above embodiments.
According to the logic transistor and the memory, the isolation layer is arranged between the gate conductor and the semiconductor layer, the isolation layer is made of a material with a memory effect, the material with the memory effect is added into the device, and the device is different from the new 0 and 1 memory states before the channel control electrode is not added in the prior art by combining with the channel control electrode. Therefore, by adding the memory effect material and adding the channel control electrode, multi-state memory can be realized, namely a plurality of currents are generated under the same working voltage, on the basis, because the output of the logic AND gate and the logic OR gate is in direct proportion to the channel current, a plurality of logic functions of a single structure can be realized under the premise of not changing the voltage and the structure by adding the memory effect material and adding the channel control electrode, namely the same structure, when the memory state is 0, the input and the output are in AND gate characteristics, and when the memory state is 1, the input and the output are in OR gate characteristics.
And the gate conductor is used as an input end, the channel control electrode is used as an output end, the carrier density of the channel region is changed by changing the voltage of the input end, so that the output state of the output end is changed, and various logic outputs are realized through one transistor, namely, the same transistor is enabled to realize a plurality of logic circuit functions, such as an AND gate, an OR gate, a NAND gate and the like, the number of transistors in the logic circuit can be reduced, the preparation method of the logic circuit is simple, and the device area is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a graph of a memory window of a prior art logic transistor;
Fig. 2 is a schematic structural diagram of a logic transistor according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a logic transistor according to another embodiment of the disclosure;
FIG. 4 is a graph of memory windows of logic transistors provided by embodiments of the present disclosure;
fig. 5a is a schematic diagram of a logic transistor according to another embodiment of the disclosure;
fig. 5b is a schematic diagram III of a logic transistor according to another embodiment of the present disclosure;
FIG. 6 is a circuit diagram of a prior art NOT circuit structure;
FIG. 7 is a circuit diagram of a single input gate structure provided by an embodiment of the present disclosure;
FIG. 8 is a diagram of exemplary logic characteristics of a single transistor NOT device structure;
fig. 9 is a schematic diagram of a logic transistor according to another embodiment of the disclosure;
FIG. 10 is a circuit diagram of a dual input gate structure provided by an embodiment of the present disclosure;
fig. 11 is a schematic diagram of a logic transistor according to another embodiment of the disclosure;
fig. 12 is a schematic diagram of a logic transistor according to another embodiment of the disclosure;
fig. 13 is a schematic diagram of a logic transistor according to another embodiment of the disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
The embodiment of the disclosure provides a logic transistor, and fig. 2 is a schematic structural diagram of the logic transistor according to the embodiment of the disclosure.
As shown in fig. 2, the logic transistor includes:
a semiconductor substrate 101;
a semiconductor layer 102 on the semiconductor substrate 101;
at least one first trench 151 partially within the semiconductor layer 102, and at least one second trench 152 extending into the semiconductor layer 102;
a gate stack located within the first trench 151; the gate stack includes a gate dielectric layer 104 covering the bottom and sidewalls of the first trench 151 and a gate conductor 105 surrounded by the gate dielectric layer 104;
an isolation layer 130 between the gate conductor 105 and the semiconductor layer 102, the isolation layer 130 comprising a material having a memory effect;
a channel control electrode 106 located inside the second trench 152 and in contact with the semiconductor layer 102 to extract the local electrical properties of the channel as an output electrode; wherein,
the portion of the semiconductor layer 102 between the first trench 151 and the second trench 152 is formed as a channel region of the logic transistor, the gate conductor 105 is an input terminal of the logic transistor, and the channel control electrode 106 is an output terminal of the logic transistor.
In an embodiment, the at least one first trench 151 partially located in the semiconductor layer 102 includes: the first trench 151 penetrates the semiconductor layer 102 and extends into the semiconductor substrate 101, or the first trench 151 extends into the semiconductor layer 102.
Specifically, in some embodiments, as shown in fig. 2, the first trench 151 penetrates the semiconductor layer 102 and extends into the semiconductor substrate 101.
In other embodiments, as shown in fig. 3, the first trench 151 extends into the semiconductor layer 102 and does not penetrate through the semiconductor layer 102. Although the first trench does not penetrate the semiconductor layer, the gate stack formed in the first trench may control the entire channel.
In an embodiment, the logic transistor further comprises: a conductor region 103 located in the semiconductor layer 102; wherein the semiconductor substrate 101 and the conductor region 103 are formed as a source region and a drain region of the logic transistor, respectively.
In this embodiment, a logic transistor will be described in detail by taking an N-channel transistor as an example. The semiconductor substrate 101 is, for example, an N-type doped single crystal silicon substrate, and can be used as a source region of a logic transistor, and the conductor region 103 is, for example, an N-type doped region, and can be used as a drain region of the logic transistor 100. The semiconductor layer 102 is, for example, a P-type doped epitaxial layer. However, the present disclosure is not limited thereto, and the logic transistor may be any one of an N-channel transistor and a P-channel transistor, and layers and conductor regions in the logic transistor have respective doping types according to channel types.
In one embodiment, a gate stack comprised of gate dielectric layer 104 and gate conductor 105 is formed in first trench 151. A gate dielectric layer 104 is located on the bottom and sidewalls of the first trench 151, the gate conductor 105 fills the first trench 151, and the gate dielectric layer 104 separates the gate conductor 105 from the semiconductor substrate 101, the semiconductor layer 102 and the conductor region 103. In the on state of the logic transistor, a channel region extending substantially vertically from one surface to the other surface of the semiconductor layer 102 is formed in the semiconductor layer 102 along the sidewall of the first trench 151 by a voltage applied to the gate conductor 105.
In the present embodiment, the gate dielectric layer 104 of the logic transistor is composed of, for example, silicon oxide, and the gate conductor 105 is composed of, for example, doped polysilicon, however, the present disclosure is not limited thereto, and the gate dielectric layer and the gate conductor may be composed of materials well known to those skilled in the art.
In an embodiment, an isolation layer 130 may also be formed between the semiconductor layer 102 and the gate conductor 105.
The isolation layer 130 is located between the gate conductor 105 and the semiconductor layer 102, and includes: the isolation layer 130 is located between the gate conductor 105 and the gate dielectric layer 104 and/or the isolation layer 130 is located inside the gate dielectric layer 104 and/or the isolation layer 130 is located between the gate dielectric layer 104 and the semiconductor layer 102.
In some embodiments, the isolation layer 130 is located between the semiconductor layer 102 and the gate dielectric layer 104, as shown in fig. 2.
In other embodiments, the spacer 130 may also be located within the gate dielectric layer 104 (not shown) or between the gate dielectric layer 104 and the gate conductor 105 (not shown).
The material of the isolation layer comprises at least one of ferroelectric material, phase change material, magnetoelectric material, quantum effect material, resistive effect material, storage material, semiconductor material, superconducting material, conductor material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride and silicide.
Optionally, the ferroelectric material is H 3 S、NbN、LaH 10 、BaTiO 3 、PbZr x Ti 1-x O 3 、BiFeO 3、 CIPS(CuIn x P (3-x) S y For example CuInP 2 S 6 )、HZO(HfZrO x )、MoTe 2 、ZrTiO 4 、PbTiO 3 、Ba(Zr,Ti)O 3 、SrTiO 3 、BaWO 4 、BaFe 12 O 19 、YBCO(YBa 2 Cu 3 O 7-x For example YBa 2 Cu 3 O 7 )，BFMO(BiFe 1-x MnxO 3 For example BiFe 0.9 Mn 0.1 O 3 )，PCMO(Pr 1-x CaxMnO 3 For example Pr 0.7 Ca 0.3 MnO)，LBCO(La 2-x BaxCuO 4 For example La 1.9 Ba 0.1 CuO 4 )，SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 )，CaK(Fe 1-x Mx) 4 As 4 (e.g. CaKFE 4 As 4 )，NdFe 1-x MxAsO 0.85 (e.g. NdFeAsO) 0.85 ) Etc.
Optionally, the phase change material is VO 2、 Ge 15 Sb 85、 Ga 36 Sb 64、 Fe 3 O 4、 NbO 2、 PEG((C 2 H 4 O) n), an alloy of indium (In) and tin (Sn), C 60 、C 70 Etc.; RMS (Re) x Mo 1-x S 2 )、GST((GeTe) x (Sb 2 Te 3 ) y ，AIST((Ag 1-x In x )(Sb 1- x Te x ) 2 For example Ag 5 In 5 Sb 60 Te 30 ) GSST (e.g. Ge 2 Sb 2 Se 1 Te 4 ,Ge 2 Sb 2 Se 4 Te 1 )，Gd 5 (Si 1 Ge 1-X ) 4 (e.g. Gd 5 Si 2 Ge 2 )，LaFe 13-x Si x (e.g. LaFe 12 Si)，La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (e.g. La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (e.g. Ge 2 Sb 2 Te 5 )、Sb 2 Te 3 、GSB((GeSn) x (Sb) y (e.g., geSnSb), AST ((AlSb) 2 ) x (Te) y For example Al 1.5 Sb 3 Te)、TASG(Ti 48 As 30 Si 12 Ge 10 ) One or more of them.
Optionally, the magneto-electric material is ZrTiO 4 、Fe 2 O 3 、Fe 3 O 4 、SrBaTiO 3 、Sr 1-x Ba x TiO 3 、Bi 4 Ge 3 O 12 、BaTiO 3 、Ba 0.8 Sr 0.2 TiO 3 、NiO、NiZnFe 2 O 4 、LiNbO 3 、BTO-PZT、BaFe 12 O 19 、Cr 2 O 3 、BiFeO 3 、BiMnO 3 And LuFe 2 O 4 、FCSB(Fe 90 Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1/3 Nb 2/3 )O 3 ) 1-x -(Pb(Zr 1-y Ti y )O 3 ) x For example Pb (Mg) x Nb 1-x )O 3 -PbZrO 3 -PbTiO 3 )、PMN-PT((Pb(Mg 1/3 Nb 2/3 )O 3 ) 1-x -(PbTiO 3 ) x For example Pb (Mg) 1/3 Nb 2/3 )O 3 -PbTiO 3 ) One or more of them.
Optionally, the quantum effect material is YBCO, pbLaTiO 3 CdSe, gaAs, pbSe, BBO, PPLN and lead, zinc and tin alloys. Cold atomic gas (such as rubidium, lithium, sodium), magnetic materials such as iron, nickel, cobalt, etc.
Optionally, the resistive effect material is ZrO 2 、TiO、Ta 2 O 5 、BiFeO 3 、SrRuO、SrZrO、Fe 3 O 4 、ZnFe 2 O 4 、BaTiO 3 、Pb(Mg 1/3 Nb 2/3 )O 3 -PbTiO 3 、Ba(Sr 0.7 Ba 0.3 )TiO 3 、In 2 O 3 -SnO 2 、Cu 2 ZnSnSe 4 Polystyrene (PS), la1-xSrxMnO 3 、(Pb,Fe)NbO 3 CuO x (e.g. CuO 0.5 )、MoS 2-x O4 (e.g. MoS) 2 O 4 )、HfO x (e.g. HfO) 2 )、WO X (e.g. WO 2 )、PCMO(Pr 1-x Ca x MnO3, e.g. Pr 0.7 Ca 0.3 MnO3)、LSMO(La x Sr 1-x MnO3, e.g. La 0.5 Sr 0.5 MnO 3 )、LCMO(La x Ca 1-x MnO3, e.g. La 0.7 Ca 0.3 MnO 3 ) Etc.
Optionally, the storage material is Fe 3 O 4 、Fe 2 O 3 CoFe (cobalt-iron alloy), feCo, feAlSi, fePt, mnFe, feNi, coPt, coFeB, sbI 3 Polycarbonate, si 3 N 4 、SiO 2 、SiO x N y 、Se、BaFe 12 O 19 、NiFe、AgCl、AgBr、Ge 2 Sb 2 Te 5 、GeSbTe、Al 2 O 3 /Fe、FeAlO x Polyaniline (PANI).
Optionally, the superconducting material is H 2 S、CeCu 2 Si、CeTIn 5 、CePt 3 Si、Ba 0.6 K 0.4 Fe 2 As 2 、LaNiC 2 、LaNiGa 2 、CaPtAs、Y 3 Fe 5 O 12 /Al、2H-MX 2 (M＝transition metals；X＝chalcogenides)、2H-NbSe 2 、(magic-angle twisted trilayer graphene)(MATTG)、2H-WS 2 、2HeTaS 2 、1Td-MoTe 2 、W 2 N 3 、1T-PdTe 2 、Pb 10-x Cu x (PO 4 ) 6 、(Li,Fe)OHFeSe、CuInCo 2 Te 4 、YBa 2 Cu 3 O 7 (yttrium alloy copper oxide), ba (Fe 1-x)Cox) 2 As 2 、Pb、MgB 2 、CuInSe 2 、LaFeAsO、Ba(Fe,Co) 2 As 2 、BSCCO、GdBCO、IBi 2 Sr 2 Ca 2 Cu 3 O 10 (BSCCO)、T l2 Ba 2 CuO 6 、YBa 2 Fe 3 Se 5 Etc.
Optionally, the semiconductor effect material is Si, in 2 Se 3 、GaAs、GaP、CdSe、ZnSe、PbSe、BN、ZnS、PbS、InP、GaN、Al 2 Se 3 AlAs, inAs, siGe, cdSe, etc.
Optionally, the perovskite material is CsPbBr 3 、MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti x O 9 For example SrBiTiO 9 )、BLT(Bi 4-x La x Ti 3 O 12 For example Bi 3.5 La 0.5 Ti 3 O 12 )、PZT(PbZr 1-x T ix O 3 . For example PbZr 0.7 Ti 0.3 O 3 )、Cs 1-x FA x PbBr 3 For example Cs 0.8 FA 0.2 PbBr3、CH 3 NH 3 PbX 3 (e.g. CH 3 NH 3 PbBr3、CH 3 NH 3 PbI3)。
Optionally, the two-dimensional material is GaS, h-BN, as 2 Te 3 、Bi 2 S 3 、2H-WS 2 、GaSe、GeS、GeSe、HfS 2 、HfSe 2 、In 2 Se 3 、MoS 2 、2H-MoS 2 、MoTe 2 、MoSe 2 、MoSSe、MoWS 2 、MoWSe 2 、ReS 2 、ReSe 2 、Sb 2 Te 3 、SnS 2 、SnSe 2 、1T-TaS 2 、WSe 2 、ZrSe 2 、ZrSe 3 ACS, etc.
Ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistance change effect materials, memory materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, silicides, and other materials having a memory effect may also be used as an insulating layer additive layer, an insulating layer material, an insulating layer additive material, a semiconductor layer material, a semiconductor channel material, or a channel electrode material. Logic polymorphism and memory polymorphism can be realized.
Due to the material with the memory effect, the transistor can realize that the memory state 0 corresponds to different current-voltage curves, and can also realize that a single structure can have more than one logic function under the same set of voltage conditions.
Since the material with the memory effect is added, the material of the device has the memory effect, so that the channel control electrode can output different logic states when the device is in the 0 and 1 states. As shown in fig. 4, the device adds a material with a memory effect, and in combination with the addition of the channel control electrode, the device assumes a new memory state of 0 and 1, which is different from that before the original channel control electrode was not added. Therefore, by adding the memory effect material and adding the channel control electrode, multi-state memory can be realized, namely a plurality of currents are generated under the same working voltage, on the basis, because the output of the logic AND gate and the logic OR gate is in direct proportion to the channel current, a plurality of logic functions of a single structure can be realized under the premise of not changing the voltage and the structure by adding the memory effect material and adding the channel control electrode, namely the same structure, when the memory state is 0, the input and the output are in AND gate characteristics, and when the memory state is 1, the input and the output are in OR gate characteristics.
In short, the states before and after the storage are regulated and controlled by the channel control electrode are different, the states before and after the storage are also different when the transistor with the storage effect material is added, and the two storage modes are organically combined, so that more logic states and storage states can be caused.
By adding the material with the memory effect and organically combining the channel control electrode to regulate the memory state of the transistor, the method can realize that the material with the memory effect is added only than the original material, but the channel control electrode is not added; or only the channel control electrode, but devices that do not incorporate a material with a memory effect have more multi-state memory.
In an embodiment, as shown in fig. 4, when the material of the isolation layer is at least one of ferroelectric material, phase change material, and magneto-electric material, the memory window of the logic transistor becomes large, so that the reading accuracy is improved.
In one embodiment, the channel control electrode 106 is located inside the second trench 152, and includes: the channel control electrode 106 is located at a lower portion of the second trench 152.
In other embodiments, the channel control electrode 106 may also be located in the middle of the second trench 152.
In an embodiment, the logic transistor further comprises: a first insulating layer 107 covering the channel control electrode 106 and located on the upper portion of the second trench 152; wherein the top surface of the channel control electrode 106 is lower than the bottom surface of the drain region (conductor region) 103, and the first insulating layer 107 isolates the channel control electrode 106 from the drain region 103.
A channel control electrode 106 and a first insulating layer 107 are formed at the lower and upper portions of the second trench 152, respectively, the top surface of the channel control electrode 106 being lower than the bottom surface of the conductor region 103, the first insulating layer 107 isolating the two from each other. In the logic transistor, the channel control electrode 106 is in direct contact with the semiconductor layer 102, the channel control electrode 106 is composed of a conductive material, for example, a metal, the semiconductor layer 102 is composed of a P-type semiconductor, and a junction capacitance is formed between the channel control electrode 106 and the semiconductor layer 102.
In an embodiment, the at least one channel control electrode 106 is comprised of any stack selected from a conductor, a semiconductor, or a conductor and a semiconductor. Preferably, the conductor comprises at least one selected from the group consisting of metal, alloy, ITO, doped silicon, doped polysilicon, metal nitride, and metal silicide. Preferably, the metal comprises at least one selected from Pt, pd, au, ni, ag, cu, al, mo, in, ti. For example, the channel control electrode 106 is composed of Pt. The material of the first insulating layer 107 includes an insulating material.
The channel control electrode is formed by doping process, deposition process, epitaxy process, self-assembly process, spin-coating process, self-assembly process, roll-to-Roll process, hydrothermal process, embossing process, rolling process, printing process, and vapor deposition process.
In some embodiments, the channel control electrode comprises one channel control electrode at least partially surrounding the gate stack to obtain a predetermined junction area.
In other embodiments, the channel control electrode includes a plurality of channel control electrodes spaced around the gate stack and respectively in contact with the semiconductor layer to form a plurality of junction capacitances.
In an embodiment, the logic transistor further comprises: a second insulating layer 110 on the conductor region 103; a drain electrode 121, a gate electrode 123, and a control gate electrode 124 on the second insulating layer 110, and a source electrode 122 on a surface of the semiconductor substrate 101 remote from the semiconductor layer 102; wherein the drain 121 is electrically connected to the drain 103, the gate 123 is electrically connected to the gate conductor 105, the control gate 124 is electrically connected to the channel control electrode 106, and the source 122 is electrically connected to the source region 101.
The second insulating layer 110 covers the surface of the conductor region 103 as an interlayer dielectric layer. The drain electrode 121 is connected to the conductor region (i.e., drain region) 103 via a first conductive via (conductive via) 111 penetrating the second insulating layer 110. The gate 123 is connected to the gate conductor 105 via a second conductive via 113 through the second insulating layer 110. The control gate 124 is connected to the channel control electrode 106 via a third conductive via 114 that extends through the second insulating layer 110 and the first insulating layer 107.
In one embodiment, the gate conductor 105 is an input terminal of the logic transistor, the channel control electrode 106 is an output terminal of the logic transistor, and the method includes: the gate electrode 123 connected to the gate conductor 105 is an input electrode of the logic transistor, and the control gate electrode 124 connected to the channel control electrode 106 is an output electrode of the logic transistor.
In this embodiment, the channel control electrode 106 of the logic transistor is adjacent to one side surface of the gate conductor 105, and the channel control electrode 106 and the gate conductor 105 respectively extend substantially vertically in the semiconductor layer 102. A gate dielectric layer 104 is sandwiched between the gate conductor 105 and the semiconductor layer 102, and a gate voltage applied to the gate conductor 105 acts on an adjacent region of the semiconductor layer 102 in a write operation and a read operation, thereby forming a substantially vertically extending channel extending from one surface to the other surface of the semiconductor layer 102 between the gate conductor 105 and the channel control electrode 106. The channel control electrode 106 is in direct contact with the semiconductor layer 102 to form a junction capacitance.
In a write operation, a control region voltage applied across the channel control electrode 106 stores charge on the junction capacitance or discharges charge from the junction capacitance into the channel. The storage state of the logic transistor is related to the charge state of the junction capacitance, and is obtained by detecting a change in the drain current (i.e., channel current) of the logic transistor in a read operation.
The logic transistor is a vertical structure transistor, as compared to a planar logic transistor, in which the source and drain regions of the logic transistor are located on opposite surfaces of the semiconductor layer 102, respectively. Not only can the total chip area of the source and drain regions be reduced, but also the gate length limitations, the wiring is more flexible, and the total wiring area of the source and drain can be reduced as compared to planar transistors. Therefore, the cell size of the logic transistor can be reduced for each memory cell, thereby improving the storage density of the memory. Further, the semiconductor substrate 101 of the logic transistor serves as a source region, and for the memory array, a "common source structure" of a plurality of logic transistors may be formed using the semiconductor substrate 101. Therefore, the use of the "common source structure" for a plurality of memory cells can reduce the number of wirings and the wiring area of the source.
In this embodiment, the source electrode 122 is formed on the back surface of the semiconductor substrate 101. In an alternative embodiment, the source electrode 122 may be formed on the surface of the second insulating layer 110. In this case, for example, the source electrode 122 is patterned from the same metal layer as the drain electrode 121, and the source electrode 122 is connected to the semiconductor substrate 101 via a conductive path. For multiple memory cells, a "common source structure" is employed, and the logic transistors of the multiple memory cells may share a common source 122. The use of the "common source structure" can reduce the number of wirings and the wiring area of the source electrode, whether the source electrode 122 is located on the front surface or the back surface of the semiconductor substrate 101, further reducing the overall size of the memory array, thereby improving the memory density of the memory.
The logic transistor is a vertical structure transistor, compared to a planar logic transistor, in which the gate conductor 105 and the channel control electrode 106 are located in the first trench 151 and the second trench 152, respectively. In contrast to the planar transistor, the channel control electrode 106 of the logic transistor 100 fills only a lower portion of the second trench, and the control gate 124 is connected to the channel control electrode 106 via the third conductive channel 114. With the first insulating layer 107 and the second insulating layer 110, the channel control electrode 106 is isolated from the conductor region 103 of the logic transistor and the electrode wiring, and thus parasitic capacitance associated with the channel control electrode 106 can be reduced to improve the read-write speed of the memory device.
In an embodiment, as shown in fig. 5a, the logic transistor further comprises: a first insulator 108, the first insulator 108 penetrating the semiconductor substrate (source region) 101 and the source electrode 122. The first insulator 108 may be located on a side of the channel control electrode 106 remote from the gate conductor 105 and/or between the channel control electrode 106 and the gate conductor 105 and/or on a side of the gate conductor 105 remote from the channel control electrode 106.
In an embodiment, as shown in fig. 5b, the logic transistor further comprises: a second insulator 109, said second insulator 109 extending through the entire logic transistor, i.e. from the drain of the top layer to the source of the bottom layer.
In this embodiment, by adding the first insulator and the second insulator, the source regions, the semiconductor layers, the channel regions, the drain regions, and the drain regions of the respective transistors can be isolated from each other, thereby reducing leakage current therebetween.
In one embodiment, as shown in fig. 2, the gate stack includes one gate stack, and the logic transistor is operated as an inverter circuit structure according to a result of performing a logic operation on a signal of an input terminal of the one gate stack.
Fig. 6 is a circuit diagram of a prior art not gate structure, as shown in fig. 6, two transistors of different types are required, so that more area is occupied, the manufacturing process is more complex, and the manufacturing cost is higher.
Fig. 7 is a circuit diagram of a single input gate structure provided by an embodiment of the present disclosure, on the basis of which a non-gate structure can be implemented.
Fig. 8 is a typical logic characteristic diagram of a single transistor NOT gate device structure that, in the single transistor NOT gate device structure embodiment of the present disclosure, was experimentally measured to be able to successfully implement a NOT logic gate. The logic not gate truth table shown in table 1, inputs and outputs are logically inverted. As shown in fig. 8, the actually measured data can effectively realize a NOT logic gate by adopting a single transistor device structure, and the drain voltage and the source voltage are kept stable and unchanged. In this table, the drain voltage VDS is equal to or less than 1V, and the source voltage vss=0v.
Table 1:
input device Output of
0 1
1 0
In one embodiment, as shown in fig. 9, the gate stack includes a plurality of gate stacks, and the logic transistor is selectively operated as any one of a dual input logic gate, a multiple input logic gate, a dual output logic gate, and a multiple output logic gate structure according to a result of performing a logic operation on signals of input terminals of the plurality of gate stacks.
The logic transistor selectively operates as any one of a dual input logic gate, a multiple input logic gate, a dual output logic gate, a multiple output logic gate structure, comprising: and enabling the logic transistor to realize any one of NOR, NAND, OR, AND, OR and XOR logic functions.
The logic transistor can realize one input and two outputs, two inputs and two outputs, three inputs and two outputs and multiple inputs and multiple outputs. The input and output can be voltage or current.
In a write operation, a control region voltage applied to the channel control electrode stores charge on the junction capacitance or discharges charge from the junction capacitance into the channel.
In a read operation, the memory state of the logic transistor is obtained by detecting a change in the leakage current of the logic transistor.
The following description will take an example in which a logic transistor includes two inputs and one output. Fig. 10 is a circuit diagram of a dual input gate structure provided in an embodiment of the present disclosure, and structures such as an and gate structure, an or gate structure, a nand gate structure, and a nor gate structure may be implemented based on the dual input gate structure in the present disclosure. As shown in fig. 9, the logic states of the inputs may be different or the same when two or more inputs are provided to the two gate conductors 105. The channel control electrode 106 is the output.
Table 2 is a truth table for a single transistor dual input NAND gate device structure. In the single-transistor dual-input NAND gate device structure embodiment of the present disclosure, the single-transistor dual-input gate device structure was able to successfully implement a NAND logic gate through experimental measurements. By introducing an additional logic gate as a second input. The logic NAND gate truth table shown in table 1, the output is logic 0 only if both input 1 and input 2 are logic 1. The actual measurement data are shown in table 3, and the NAND logic gate can be effectively realized by adopting the single transistor double-input gate device structure, and the drain voltage and the source voltage are kept stable. In this table, the drain voltage vds=0.8v and the source voltage vss=0v.
Table 2:
input 1 Input 2 Output of
0 0 1
1 0 1
0 1 1
1 1 0
Table 3:
input 1 Input 2 Output of
0V 0V 1.6906V
1.2V 0V 1.4983V
0V 1.4V 1.1340V
1.2V 1.4V 0.3451V
Table 4 is a truth table for a single transistor dual input AND gate device structure. In the presently disclosed single-transistor dual-input gate AND device structure embodiments, the single-transistor dual-input gate device structure was found to be successful in implementing an AND logic gate through experimental measurements. By introducing an additional logic gate as a second input. The logic AND gate truth table shown in Table 4, the output is a logic 1 only if both input 1 AND input 2 are logic 1. The actual measurement data are shown in table 5, AND the AND logic gate can be effectively realized by adopting the single transistor double-input gate device structure, AND the drain voltage AND the source voltage are kept stable. In this table, the drain voltage vds=6v and the source voltage vss=0v.
Table 4:
input 1 Input 2 Output of
0 0 0
1 0 0
0 1 0
1 1 1
Table 5:
input 1 Input 2 Output of
0V 0V 0.187V
1.4V 0V 0.506V
0V 10V 0.262V
1.4V 10V 1.399V
Table 6 is a truth table for a single transistor dual input OR gate device structure. In the presently disclosed embodiments of a single-transistor dual-input gate OR device structure, the single-transistor dual-input gate device structure was found to be capable of successfully implementing an OR logic gate through experimental measurements. By introducing an additional logic gate as a second input. The logic OR gate truth table shown in table 6, the output is logic 0 only if both input 1 and input 2 are logic 0. The actual measurement data are shown in table 7, and the OR logic gate can be effectively realized by adopting the single transistor double-input gate device structure, and the drain voltage and the source voltage are kept stable and unchanged. In this table, the drain voltage vds=6v and the source voltage vss=0v.
Table 6:
input 1 Input 2 Output of
0 0 0
1 0 1
0 1 1
1 1 1
Table 7:
input 1 Input 2 Output of
0V 0V 0.161V
1.4V 0V 1.031V
0V 12V 1.019V
1.4V 12V 1.185V
In one embodiment, as shown in fig. 11, the logic transistor includes one input and two outputs, where the distances between the two outputs and the input may be equal or unequal.
The output is a logical not gate or a buffer depending on the position of the channel control electrode (output electrode) in one of the second trenches. If the output electrode is closer to the drain electrode, the output signal is logically opposite to the input signal and is output as a logic NOT gate; if the output electrode is closer to the source, the output signal is logically the same as the input signal, and the output is a buffer.
The output and logic may be determined by adjusting the position of the channel control electrode (output electrode) in one of the second trenches, the distance between the second trench and the first trench, the structure, the process, the voltage, etc., for example, depending on the position of the output electrode in one of the second trenches, whether the output is a logic and gate (output electrode is closer to the source) or a nand gate (output electrode is closer to the drain), and increasing the drain voltage may cause the and gate to become an or gate.
In one embodiment, as shown in FIG. 12, the logic transistor includes two inputs, two outputs.
The output and logic may be determined by adjusting the position of the channel control electrode (output electrode) in one of the second trenches, the distance between the second trench and the first trench, the structure, the process, the voltage, etc., for example, depending on the position of the output electrode in one of the second trenches, whether the output is a logic and gate (output electrode is closer to the source) or a nand gate (output electrode is closer to the drain), and increasing the drain voltage may cause the and gate to become an or gate.
In one embodiment, as shown in FIG. 13, the logic transistor includes three inputs, two outputs.
In some embodiments, the middle input of the three inputs is the common input of the two-side inputs, and the position of the output electrode in one of the second trenches, the distance between the second trench and the first trench, the structure, the process, the voltage, and the like can be adjusted to determine what output, what logic, for example, whether the logic and gate (the output electrode is closer to the source) or the nand gate (the output electrode is closer to the drain), and the increase of the drain voltage can change the and gate into the or gate.
In other embodiments, the middle input is not a common input for both side inputs, and the and gate may be changed to an or gate by adjusting the position of the output electrode in one of the second trenches, the distance between the second trench and the first trench, the structure, the process, the voltage, etc., to determine what output, what logic, e.g., whether the logic and gate (output electrode is closer to the source) or the nand gate (output electrode is closer to the drain) depending on the position of the output electrode in one of the second trenches.
In an embodiment, the input may be a voltage, and the output may be a voltage or a current.
In the embodiment of the disclosure, the gate conductor is used as the input end, the channel control electrode is used as the output end, and the carrier density of the channel region is changed by changing the voltage of the input end so as to change the output state of the output end, so that multiple logic outputs are realized through one transistor, namely, the same transistor is enabled to realize multiple logic circuit functions, such as an AND gate, an OR gate, a NAND gate, a NOR gate and the like, the number of transistors in the logic circuit can be reduced, the preparation method of the logic circuit is simple, and the device area is reduced.
Embodiments of the present disclosure also provide a memory comprising a logic transistor as in any of the above embodiments.
It should be appreciated that the disclosed structures may be implemented with existing process lines, or may be implemented with adjustments based on existing process steps, and that the channel control electrode, control region material may be a semiconductor material, a conductor material, or a combination of materials. The actual manufacturing process may vary depending on factors such as manufacturer, device size, and process technology.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (18)

1. A logic transistor, comprising:
a semiconductor substrate;
a semiconductor layer on the semiconductor substrate;
at least one first trench partially within the semiconductor layer, and at least one second trench extending into the semiconductor layer;
a gate stack located within the first trench; the gate stack comprises a gate dielectric layer covering the bottom and the side walls of the first trench and a gate conductor wrapped by the gate dielectric layer;
An isolation layer between the gate conductor and the semiconductor layer, the isolation layer comprising a material having a memory effect;
a channel control electrode located inside the second trench and in contact with the semiconductor layer to extract local electrical properties of the channel as an output electrode; wherein,
the portion of the semiconductor layer between the first trench and the second trench is formed as a channel region of the logic transistor, the gate conductor is an input terminal of the logic transistor, and the channel control electrode is an output terminal of the logic transistor.
2. The logic transistor according to claim 1, wherein,
the isolation layer is located between the gate conductor and the semiconductor layer, comprising: the isolation layer is located between the gate conductor and the gate dielectric layer, and/or the isolation layer is located inside the gate dielectric layer, and/or the isolation layer is located between the gate dielectric layer and the semiconductor layer.
3. The logic transistor according to claim 1, wherein,
the material of the isolation layer comprises at least one of ferroelectric material, phase change material, magnetoelectric material, quantum effect material, resistive effect material, storage material, semiconductor material, superconducting material, conductor material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride and silicide.
4. The logic transistor of claim 1, wherein the logic transistor further comprises:
a conductor region in the semiconductor layer; wherein,
the semiconductor substrate and the conductor region are formed as a source region and a drain region of the logic transistor, respectively.
5. The logic transistor according to claim 4, wherein the logic transistor further comprises:
a first insulating layer covering the channel control electrode and located at an upper portion of the second trench; wherein,
the top surface of the channel control electrode is lower than the bottom surface of the drain region, and the first insulating layer isolates the channel control electrode from the drain region.
6. The logic transistor of claim 5, wherein the logic transistor further comprises:
a second insulating layer on the conductor region;
a drain electrode, a gate electrode, and a control gate electrode on the second insulating layer, and a source electrode on a surface of the semiconductor substrate remote from the semiconductor layer; wherein,
the drain electrode is electrically connected with the drain region, the gate electrode is electrically connected with the gate conductor, the control gate electrode is electrically connected with the channel control electrode, and the source electrode is electrically connected with the source region.
7. The logic transistor of claim 6 wherein,
the gate conductor is an input terminal of the logic transistor, the channel control electrode is an output terminal of the logic transistor, and the method comprises the following steps:
the gate connected to the gate conductor is an input electrode of the logic transistor, and the control gate connected to the channel control electrode is an output electrode of the logic transistor.
8. The logic transistor according to claim 1, wherein,
the channel control electrode is located inside the second trench, and includes: the channel control electrode is located at a lower portion of the second trench.
9. The logic transistor according to claim 1, wherein,
the gate stack includes one gate stack, and the logic transistor is operated in a NOT circuit structure according to a result of performing a logic operation on a signal of an input terminal of the one gate stack.
10. The logic transistor according to claim 1, wherein,
the gate stack includes a plurality of gate stacks, and the logic transistor is selectively operated as any one of a dual-input logic gate, a multi-input logic gate, a dual-output logic gate, and a multi-output logic gate structure according to a result of performing a logic operation on signals of input ends of the plurality of gate stacks.
11. The logic transistor according to claim 10, wherein,
the logic transistor selectively operates as any one of a dual input logic gate, a multiple input logic gate, a dual output logic gate, a multiple output logic gate structure, comprising: and enabling the logic transistor to realize any one of NOR, NAND, OR, AND, OR and XOR logic functions.
12. The logic transistor according to claim 1, wherein,
the at least one first trench partially within the semiconductor layer, comprising:
the first trench extends through the semiconductor layer and into the semiconductor substrate, or,
the first trench extends into the semiconductor layer.
13. The logic transistor according to claim 1, wherein,
the channel control electrode includes a channel control electrode at least partially surrounding the gate stack to obtain a predetermined junction area.
14. The logic transistor according to claim 1, wherein,
the channel control electrode comprises a plurality of channel control electrodes which are arranged around the gate stack at intervals and are respectively contacted with the semiconductor layer to form a plurality of junction capacitances.
15. The logic transistor according to claim 1, wherein,
the at least one channel control electrode is comprised of any stack selected from a conductor, a semiconductor, or a conductor and a semiconductor.
16. The logic transistor according to claim 1, wherein,
the channel control electrode is formed by doping process, deposition process, epitaxy process, self-assembly process, spin-coating process, self-assembly process, roll-to-Roll process, hydrothermal process, embossing process, rolling process, printing process, and vapor deposition process.
17. The logic transistor according to claim 1, wherein,
ferroelectric material, magneto-electric material, phase change material, quantum effect material, resistive effect material, memory material, semiconductor material, superconducting material, conductor material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, silicide also serves as an insulating layer additive layer, insulating layer material, insulating layer additive material, semiconductor layer material, semiconductor channel material, or channel electrode material.
18. A memory comprising a logic transistor as claimed in any one of claims 1 to 17.
CN202311387915.8A 2023-10-24 2023-10-24 Logic transistor and memory Pending CN117525142A (en)

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