JP5075863B2 - Spin transistor, reconfigurable logic circuit including the spin transistor, and magnetic memory - Google Patents

Description

  The present invention relates to a spin transistor, a reconfigurable logic circuit including the spin transistor, and a magnetic memory.

In recent years, research on new devices that simultaneously utilize the charge and spin properties of electrons has become active. One of them, a spin transistor, uses a magnetic material for a source electrode and a drain electrode, and controls output characteristics by changing the relative magnetization directions of the source electrode and the drain electrode (for example, see Non-Patent Document 1). ). That is, the drain current I _D when the drain current I _D ^P when the relative magnetization directions of the source electrode and the drain electrode is substantially parallel is increased, the relative magnetization directions are anti-parallel (substantially backward) ^Take advantage of less ^AP .

When this spin transistor is used in a memory or a reconfigurable logic circuit, it is necessary to increase the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel. There is.

S. Sugahara and M. Tanaka, Appl. Phys. Lett. 84 (2004) 2307

However, as will be described later, in the conventional spin transistor, due to the interaction between electrons and holes, the current I _D ^P when the magnetization direction is substantially parallel, and the current I _D ^AP when the magnetization direction is substantially anti-parallel, There is a problem that the absolute value of the difference between the two decreases.

The present invention has been made in consideration of the above circumstances, and is a current I _D ^P when the magnetization direction is substantially parallel and a current when the magnetization direction is substantially anti-parallel due to the interaction between electrons and holes. It is an object of the present invention to provide a spin transistor that can suppress a decrease in the absolute value of a difference from I _D ^AP , a reconfigurable logic circuit including the spin transistor, and a magnetic memory.

  A spin transistor according to a first aspect of the present invention includes a semiconductor substrate having an n-type semiconductor region provided on a surface thereof, and a source electrode and a drain electrode provided on the semiconductor region so as to be spaced apart from each other, wherein the drain electrode Is provided on the semiconductor region, has a band gap larger than that of the semiconductor in the semiconductor region and has a valence band edge having energy lower than that of the semiconductor in the semiconductor region; and A first ferromagnetic layer provided on the semiconductor layer, and the source electrode has a second ferromagnetic layer provided on the semiconductor region, the source electrode and the drain electrode, the source electrode and the drain A gate electrode provided in the semiconductor region between the first electrode and the second electrode, wherein one of the first and second ferromagnetic layers has an invariable magnetization direction, and the other is magnetized. Direction is characterized in that it is a variable.

  The spin transistor according to the second aspect of the present invention includes a semiconductor substrate having a p-type semiconductor region provided on a surface thereof, and a source electrode and a drain electrode provided on the semiconductor region so as to be spaced apart from each other. An electrode is provided on the semiconductor region and has an n-type first electrode having a band gap larger than that of the semiconductor in the semiconductor region and having an energy lower than that of the valence band edge of the inversion layer formed in the semiconductor region. A source electrode and a drain electrode having a first semiconductor layer and a first ferromagnetic layer provided on the first semiconductor layer, the source electrode having a second ferromagnetic layer provided on the semiconductor region And a gate electrode provided in the semiconductor region between the source electrode and the drain electrode, wherein one of the first and second ferromagnetic layers has a non-magnetization direction. , And the other is characterized in that the magnetization direction is variable.

  A spin transistor according to a third aspect of the present invention includes a semiconductor substrate having a p-type semiconductor region provided on a surface thereof, and a source electrode and a drain electrode provided separately on the semiconductor region, A drain electrode provided on the semiconductor region, having a band gap larger than that of the semiconductor in the semiconductor region and having a conduction band edge higher than a conduction band edge of the semiconductor in the semiconductor region; a p-type first semiconductor layer; A first ferromagnetic layer provided on the first semiconductor layer, the source electrode having a second ferromagnetic layer provided on the semiconductor region, and a source electrode and a drain electrode, and the source electrode A gate electrode provided in the semiconductor region between the first electrode and the drain electrode, wherein one of the first and second ferromagnetic layers has a magnetization direction unchanged, and the other It is characterized in that the magnetization direction is variable.

  A spin transistor according to a fourth aspect of the present invention includes a semiconductor substrate having an n-type semiconductor region provided on a surface thereof, and a source electrode and a drain electrode provided separately on the semiconductor region, The drain electrode is provided on the semiconductor region, has a band gap larger than that of the semiconductor of the semiconductor region, and has a p-type first having a conduction band edge higher than the conduction band edge of the inversion layer formed in the semiconductor region. A source layer and a drain electrode having a semiconductor layer and a first ferromagnetic layer provided on the first semiconductor layer, the source electrode having a second ferromagnetic layer provided on the semiconductor region; A gate electrode provided in the semiconductor region between the source electrode and the drain electrode, wherein one of the first and second ferromagnetic layers has an invariable magnetization direction. There, the other is characterized in that the magnetization direction is variable.

  The reconfigurable logic circuit according to the fifth aspect of the present invention includes two field effect transistors, and at least one of the two field effect transistors is the spin transistor according to any one of the first to fourth aspects. In addition, the two field effect transistors are provided with a common floating gate.

  According to a sixth aspect of the present invention, there is provided a magnetic memory comprising: the spin transistor according to any one of the first and second aspects; a first bit line electrically connected to the first ferromagnetic layer; And a second bit line electrically connected to the two ferromagnetic layers and a word line electrically connected to the gate electrode.

According to the present invention, the absolute value of the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes is reduced. Can be suppressed.

Sectional drawing of a spin transistor. The figure explaining the problem of a spin transistor. FIG. 3 is an energy band diagram of an n-channel spin transistor according to an embodiment of the present invention. FIG. 3 is an energy band diagram of a p-channel spin transistor according to an embodiment of the present invention. Sectional drawing of the spin transistor by 1st Embodiment. Sectional drawing of the spin transistor by the modification of 1st Embodiment. The energy band figure of the spin transistor of a modification. Sectional drawing of the spin transistor by 2nd Embodiment. The energy band figure of the spin transistor of 2nd Embodiment. Sectional drawing of the spin transistor by 3rd Embodiment. Sectional drawing of the spin transistor by 4th Embodiment. Sectional drawing of the spin transistor by 5th Embodiment. Sectional drawing of the spin transistor by 6th Embodiment. Sectional drawing of the spin transistor by 7th Embodiment. Sectional drawing of the spin transistor by 8th Embodiment. A circuit diagram showing a logic circuit by a 9th embodiment. The figure which shows the floating gate voltage dependence of the output of the logic circuit of 9th Embodiment. The figure which shows a logic table in case the logic circuit of 9th Embodiment functions as an AND circuit. The figure which shows a logic table in case the logic circuit of 9th Embodiment functions as an OR circuit. The figure which shows the logic circuit by the 1st modification of 9th Embodiment. The figure which shows the logic circuit by the 2nd modification of 9th Embodiment. The circuit diagram of the principal part of MRAM of 10th Embodiment. FIG. 3 is an energy band diagram of an n-channel spin transistor according to an embodiment of the present invention. FIG. 3 is an energy band diagram of a p-channel spin transistor according to an embodiment of the present invention.

  Before explaining the embodiments of the present invention, the background to the present invention will be described.

First, in the spin transistor shown in FIG. 1, due to the interaction between electrons and holes, the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel. The reason why the absolute value decreases will be explained. As shown in FIG. 1, the spin transistor is formed in a semiconductor region that becomes a channel region 12 provided on the surface portion of the semiconductor substrate 10. A gate electrode 212 is provided on the semiconductor region to be the channel region 12 so as to sandwich the gate insulating film 210. On one region (source side region) of the semiconductor region sandwiching the gate electrode 212, a ferromagnetic source electrode 204a is provided so as to sandwich the tunnel barrier layer 202a. A drain electrode 204b made of a ferromagnetic material is provided on the other region (region on the drain side) so as to sandwich the tunnel barrier layer 202b. In the spin transistor shown in FIG. 1, the magnetization direction of the source electrode 204a made of a ferromagnetic material is fixed, and the magnetization direction of the drain electrode 204b made of a ferromagnetic material is variable.

FIG. 2 shows an energy band diagram when a bias voltage is applied between the source electrode 204a and the drain electrode 204b of the spin transistor. As can be seen from FIG. 2, in the vicinity of the source electrode 204a and the drain electrode 204b, a so-called MIS diode made of ferromagnetic material / tunnel barrier layer / semiconductor (channel region) is formed. Since this MIS diode is formed, when a bias is applied between the source electrode 204a and the drain electrode 204b, electrons are not only injected from the source electrode 204a into the channel region 12, but also from the drain electrode 204b to the channel region. Holes are injected into 12. That is, two types of carriers of electrons and holes travel in the channel region 12. In general, when electrons and holes are present in the channel region 12 at the same time, these electrons and holes interact to cause spin relaxation, reducing the magnetoresistance ratio, that is, the current when the magnetization directions are substantially parallel. It is known as a BAP (Bir, Aronov, Pikus) mechanism that the absolute value of the difference between I _D ^P and the current I _D ^AP when the magnetization direction is substantially antiparallel.

Therefore, the present inventors need to suppress the injection of minority carriers out of electrons and holes in order to suppress the spin relaxation and increase the absolute value of the difference between I _D ^P and I _D ^AP . In order to suppress minority carrier injection, it was considered that a semiconductor layer having a larger band gap (than the semiconductor in the semiconductor region) may be inserted between the tunnel barrier layer and the semiconductor region to be a channel region. As an example, n ⁻ type GaAs is used for the channel region, and n ⁺ type AlGaAs is used for the semiconductor layer to be inserted. Depletion type, that is, the semiconductor region to be the channel region and the semiconductor layer to be inserted have the same conductivity type. FIG. 3 shows an energy band diagram in the case of the type spin transistor. FIG. 3 is an energy band diagram when the depletion type n-type spin transistor is in an ON state, that is, when no voltage is applied to the gate. Since AlGaAs in the semiconductor layer to be inserted is highly doped, the barrier against electrons is low. However, since the band gap is larger than the band gap of GaAs in the semiconductor region, it becomes a barrier against holes. In the transistor thus configured, injection of holes into the channel region is suppressed, so that spin relaxation due to interaction between electrons and holes is suppressed. That is, the absolute value of the difference between I _D ^P and I _D ^AP can be increased.

  As can be seen from the above description and FIG. 3, when the semiconductor region serving as the channel region is formed of an n-type semiconductor, the band gap is larger than the semiconductor in the semiconductor region and the valence band edge of the semiconductor in the semiconductor region is If a semiconductor layer having energy lower than that of the edge is inserted between the drain-side channel region (semiconductor region) and the tunnel barrier layer, injection of holes that are minority carriers into the channel region can be suppressed. .

On the other hand, when the semiconductor region to be the channel region is made of a p-type semiconductor, for example, when p ⁻ type GaAs is used for the channel region and p ⁺ type AlGaAs is used for the semiconductor layer to be inserted, the energy of the depletion type p type spin transistor A band diagram is shown in FIG. FIG. 4 is an energy band diagram when the depletion type p-type spin transistor is in the ON state, that is, when no voltage is applied to the gate, as in FIG. In this case, AlGaAs in the semiconductor layer to be inserted is heavily doped, so the barrier to holes is low, but its band gap is larger than the band gap of GaAs in the channel region, so it becomes a barrier to electrons. . In this case, as in the case where the semiconductor region serving as the channel region is formed of an n-type semiconductor, the band gap is larger than that of the semiconductor in the channel region and the conduction band edge is higher than the conduction band edge of the semiconductor in the channel region. By inserting a semiconductor layer having N between the channel region on the drain side and the tunnel barrier layer, injection of electrons that are minority carriers into the channel region can be suppressed.

  In the above description, the spin transistor is a depletion type. However, even if the spin transistor is an enhancement type, that is, the channel region and the semiconductor layer to be inserted are of different conductivity types, the semiconductor layer to be inserted is a semiconductor layer having the same characteristics as the depletion type, Injection of minority carriers into the channel region can be suppressed. That is, when the semiconductor region to be the channel region is made of a p-type semiconductor, as shown in FIG. 23, the semiconductor in the semiconductor region having a band gap larger than that of the semiconductor in the semiconductor region and having the valence band edge turned on (ie, the gate). Is applied to the n-type semiconductor layer having energy lower than the valence band edge of the inversion layer (n-type) generated in the semiconductor region, and the drain-side channel region (semiconductor region) and the tunnel barrier layer If inserted between them, injection of holes, which are minority carriers, into the channel region can be suppressed.

  Further, when the semiconductor region to be the channel region is made of an n-type semiconductor, as shown in FIG. 24, the semiconductor in the semiconductor region having a band gap larger than that of the semiconductor in the semiconductor region and having the conduction band edge turned on (that is, in the gate). A p-type semiconductor layer having a higher energy than the conduction band edge of the inversion layer (p-type) generated in the channel region is applied between the drain-side channel region (semiconductor region) and the tunnel barrier layer. If inserted, injection of electrons, which are minority carriers, into the channel region can be suppressed.

  In the above description, an example is shown in which GaAs and AlGaAs are used for the channel region and the semiconductor layer to be inserted, respectively, but other combinations can also be applied. For example, a combination of SiGe and Si, a combination of Ge and SiGe, or the like. In addition, the present invention can also be applied to combinations of III-V semiconductors, III-V semiconductors, and IV semiconductors. For example, a combination of InGaAs and GaAs, a combination of InP and GaAs, or the like.

  The present invention has been made based on the above findings of the present inventors, and will be described below as an embodiment with reference to the drawings.

(First embodiment)
FIG. 5 shows a cross section of the spin transistor according to the first embodiment of the present invention. As shown in FIG. 5, the spin transistor of this embodiment is formed in a semiconductor region that becomes a channel region 12 provided on the surface portion of the semiconductor substrate 10. The semiconductor region may be a partial region of the semiconductor substrate or a well region formed in the semiconductor substrate. Further, it may be an SOI layer of an SOI (Silicon On Insulator) substrate. A gate structure 20 is provided on the semiconductor region to be the channel region 12. The gate structure 20 includes a gate insulating film 22 formed on the channel region 12, a gate electrode 24 formed on the gate insulating film 22, and a connection electrode 26 formed on the gate electrode 24. ing.

  Further, a source electrode 30a is provided on one region (source side region) of the semiconductor region sandwiching the gate structure 20, and a drain electrode 30b is provided on the other region (drain side region). The source electrode 30a includes a semiconductor layer 31a formed on the semiconductor region, a tunnel barrier layer 33a formed on the semiconductor layer 31a, a ferromagnetic layer 34a formed on the tunnel barrier layer 33a, And a connection electrode 38a formed on the magnetic layer 34a. The drain electrode 30b includes a semiconductor layer 31b formed on the semiconductor region, a tunnel barrier layer 33b formed on the semiconductor layer 31b, a ferromagnetic layer 34b formed on the tunnel barrier layer 33b, A nonmagnetic layer 35b formed on the ferromagnetic layer 34b, a ferromagnetic layer 36b formed on the nonmagnetic layer 35b, and a connection electrode 38b formed on the ferromagnetic layer 36b are provided. . Note that the drain electrode 30b may have a configuration in which the nonmagnetic layer 35b and the ferromagnetic layer 36b are omitted.

  When the semiconductor region to be the channel region 12 is an n-type semiconductor, the semiconductor layers 31a and 31b are n-type, have a band gap larger than the semiconductor band gap of the semiconductor region (channel region), and have a valence band. Has a lower energy than the upper end of the semiconductor valence band of the semiconductor region (channel region). In this case, even if the semiconductor layer 31b is provided in the drain electrode 30b and the semiconductor layer 31a of the source electrode 30a is deleted, injection of holes that are minority carriers into the channel region 12 can be suppressed.

  When the semiconductor region to be the channel region 12 is a p-type semiconductor, the semiconductor layers 31a and 31b are p-type, have a band gap larger than the semiconductor band gap of the semiconductor region (channel region) and are conductive. The lower end of the band has higher energy than the lower end of the semiconductor conduction band of the semiconductor region (channel region). In this case, even if the semiconductor layer 31b is provided in the drain electrode 30b and the semiconductor layer 31a of the source electrode 30a is deleted, injection of electrons that are minority carriers into the channel region 12 can be suppressed.

  By providing the tunnel barrier layers 33a and 33b on the source electrode 30a and the drain electrode 30b, reactions that may occur between the surface of the semiconductor substrate 10 and the ferromagnetic layer 34a, and the surface of the semiconductor substrate 10 and the ferromagnetic layer 34b Each plays a role in preventing reactions that may occur. Therefore, the junction between the ferromagnetic layer 34a and the surface of the semiconductor substrate 10 and the junction between the ferromagnetic layer 34b and the surface of the semiconductor substrate 10 can be well formed, and the manufacturing yield of the transistor is improved. It is possible. Further, by providing the tunnel barrier layers 33a and 33b, carriers can be injected into the channel region 12 with a high spin polarization. As a result, a large change in conductance accompanying a change in the magnetization direction of the ferromagnetic layer 34a or the ferromagnetic layer 34b can be obtained. Note that a tunnel barrier layer is formed only on one of the surface of the semiconductor substrate 10 and the ferromagnetic layer 34a and between the surface of the semiconductor substrate 10 and the ferromagnetic layer 34b in accordance with the required transistor performance and the like. It is also possible to adopt a structure.

  The magnetization direction of the ferromagnetic layer 34a of the source electrode 30a is fixed (invariable), and the magnetization direction of the ferromagnetic layer 34b of the drain electrode 30b is variable. In addition, the magnetization direction of the ferromagnetic layer 36b of the drain electrode 30b is fixed (invariable) and is substantially parallel to the magnetization direction of the ferromagnetic layer 34a. In the drain electrode 30b, the magnetization direction of the ferromagnetic layer 34b is reversed by the spin injection current because the magnetization direction of the ferromagnetic layer 36b is fixed so as to be substantially parallel to the magnetization direction of the ferromagnetic layer 34a. At this time, the spin torque acting on the magnetization of the ferromagnetic layer 34b can be increased as compared with the case where the ferromagnetic layer 36b is not provided. The connection electrodes 26, 38a, and 38b also serve as a protective layer.

In the spin transistor of this embodiment, the current when a voltage is applied between the connection electrode 38a of the source electrode 30a and the connection electrode 38b of the drain electrode 30b is the voltage applied to the connection electrode 26 of the gate structure 20. And the relative magnetization direction of the ferromagnetic layer 34a and the ferromagnetic layer 34b. That is, when the gate voltage is applied to the gate structure 20, if the relative magnetization directions of the ferromagnetic layer 34a and the ferromagnetic layer 34b are substantially parallel, a large current I _D ^P flows and is substantially antiparallel. small current _I ^{D AP} flows, if any. It should be noted that by changing the configuration of the semiconductor or magnetic material, a small current I _D ^P flows if the relative magnetization directions of the ferromagnetic layer 34a and the ferromagnetic layer 34b are substantially parallel, and large if they are approximately antiparallel. It can also be configured such that current I _D ^AP flows.

The larger the absolute value of the difference between the current in the case of being substantially parallel and the current in the case of being substantially antiparallel, the higher the performance as a spin transistor. This current difference depends on the spin polarization rate of the ferromagnetic layer, the spin injection efficiency from the ferromagnetic layer to the channel region, and the spin relaxation in the channel region. Further, when the bias voltage applied between the connection electrode 38a of the source electrode 30a and the connection electrode 38b of the drain electrode 30b is changed, the current I _D ^P when the magnetization directions are substantially parallel and the magnetization direction are substantially opposite. also it changes the difference between the current I _D ^AP when parallel.

  Next, a method for manufacturing the spin transistor of this embodiment shown in FIG. 5 will be described. First, a semiconductor region to be the channel region 12 is formed by introducing impurities into the semiconductor substrate 10 and annealing. Thereafter, using MBE (Molecular Beam Epitaxy), CVD (Chemical Vapor Deposition), etc., semiconductor layers 31a and 31b are formed on the semiconductor region, and then the semiconductor layer as a gate is removed by etching to form a channel region. The semiconductor region to be 12 is exposed. Subsequently, a gate insulating film 22 and a gate electrode 24 are formed on the exposed semiconductor region. Next, tunnel barrier layers 33a and 33b and ferromagnetic layers 34a and 34b are sequentially formed. Thereafter, a nonmagnetic layer 35b and a ferromagnetic layer 36b are formed on the drain electrode side. Subsequently, connection electrodes 38a, 26, and 38b that also serve as a protective film are formed on the ferromagnetic layer 34a, the gate electrode 24, and the ferromagnetic layer 36b, respectively. Finally, annealing is performed at 270 ° C. for 1 hour in a magnetic field in order to impart magnetic anisotropy to the ferromagnetic layer 34a, the ferromagnetic layer 34b, and the ferromagnetic layer 36b.

As described above, in the spin transistor of this embodiment, the semiconductor layers 31a and 31b are provided between the semiconductor region (channel region) 12 and the tunnel barrier layer. When the semiconductor region (channel region) 12 is an n-type semiconductor, these n-type semiconductor layers 31a and 31 have a band gap larger than that of the semiconductor of the semiconductor region (channel region) 12 and have a valence band. Since the upper end has energy lower than the upper end of the semiconductor valence band of the semiconductor region (channel region), it is possible to suppress the injection of holes serving as minority carriers into the channel region. For this reason, the decrease in the absolute value of the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes is suppressed. be able to.

When the semiconductor region (channel region) 12 is a p-type semiconductor, the p-type semiconductor layers 31a and 31b have a larger band gap than the semiconductor band gap of the semiconductor region (channel region) and have a conduction band. Has a higher energy than the lower end of the semiconductor conduction band of the semiconductor region (channel region). For this reason, the absolute value of the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially anti-parallel due to the interaction between the holes and the electrons serving as minority carriers. Reduction can be suppressed.

  In the present embodiment, the electrode 30a is used as the source electrode and the electrode 30b is used as the drain electrode. However, the electrode 30a may be used as the drain electrode and the electrode 30b may be used as the source electrode.

(Modification)
Next, FIG. 6 shows a cross section of a spin transistor according to a modification of the present embodiment. The spin transistor of this modification has a configuration in which the tunnel barrier layers 31a and 31b of the source electrode 30a and the drain electrode 30b are omitted from the spin transistor of the first embodiment shown in FIG.

FIG. 7 shows an energy band diagram in the case where n ⁻ type GaAs is used for the channel region and n ⁺ type AlGaAs is used for the semiconductor layers 31a and 31b in the spin transistor of this modification. Since AlGaAs in the semiconductor layers 31a and 31b is highly doped, the barrier against electrons is low, but the band gap is larger than the band gap of GaAs in the channel region, and the upper end of the valence band is the semiconductor region. Since it has energy lower than the upper end of the valence band of the semiconductor in the (channel region), it becomes a barrier against holes. Therefore, in this case, since the injection of holes into the channel region is suppressed, spin relaxation due to the interaction between electrons and holes is suppressed. That is, the absolute value of the difference between I _D ^P and I _D ^AP can be increased.

Similarly to the first embodiment, this modification also has a current I _D ^P when the magnetization direction is substantially parallel and a current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes. A decrease in the absolute value of the difference between the two can be suppressed.

(Second Embodiment)
Next, FIG. 8 shows a cross section of a spin transistor according to a second embodiment of the present invention. The spin transistor of this embodiment is the same as the spin transistor of the first embodiment shown in FIG. 5, except that a semiconductor layer 32a is provided between the semiconductor layer 31a of the source electrode 30a and the tunnel barrier layer 33a, and a semiconductor layer of the drain electrode 30b. A semiconductor layer 32b is provided between 31b and the tunnel barrier layer 33b. These semiconductor layers 32a and 32b are semiconductors doped with impurities of the same conductivity type as the semiconductor layers 31a and 31b at a high concentration, but have a narrower band gap than the semiconductor layers 31a and 31b. That is, the energy band diagram in the vicinity of the source electrode 30a in this embodiment is as shown in FIG.

  In the spin transistor of this embodiment, since the semiconductor layers 32a and 32b having a small band gap are inserted, even in the case where Fermi level pinning due to an interface state exists, the magnetic material / tunnel barrier layer / semiconductor Junction resistance can be reduced. Similarly to the first embodiment, the semiconductor layers 31a and 31b having a larger band gap than the semiconductor region serving as the channel region can suppress the injection of minority carriers into the channel region. Spin relaxation due to action can be suppressed.

  In the present embodiment, the semiconductor layers 32a and 32b are semiconductors having a narrower band gap than the semiconductor layers 31a and 31b. However, the semiconductor layers 32a and 32b are semiconductors doped with impurities at a high concentration and the channel regions. A semiconductor having a narrower band gap than the semiconductor in the semiconductor region to be formed may be used. In this case, the junction resistance can be further reduced as compared with the present embodiment.

As described above, according to the present embodiment, the junction resistance of the magnetic substance / tunnel barrier layer / semiconductor can be reduced while suppressing spin relaxation due to the interaction between electrons and holes. Therefore, it is possible to suppress a decrease in the absolute value of the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes. In addition, the junction resistance of the magnetic body / tunnel barrier layer / semiconductor can be reduced.

  As in the modification of the first embodiment, the source electrode 30a and the drain electrode 30b may be configured without the tunnel barrier layer. In this case, the semiconductor layer 32a is provided between the ferromagnetic layer 34a and the semiconductor layer 31a, and the semiconductor layer 32b is provided between the ferromagnetic layer 34b and the semiconductor layer 31b.

(Third embodiment)
Next, FIG. 10 shows a cross section of a spin transistor according to a third embodiment of the present invention. The spin transistor of this embodiment has a configuration in which the gate insulating film 22 of the gate structure 20 is omitted from the spin transistor of the first embodiment shown in FIG. That is, the spin transistor of this embodiment has a MESFET structure.

Similarly to the first embodiment, in the present embodiment, the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes A decrease in the absolute value of the difference between the two can be suppressed.

  As in the modification of the first embodiment, the source electrode 30a and the drain electrode 30b may be configured without the tunnel barrier layer.

(Fourth embodiment)
Next, FIG. 11 shows a cross section of a spin transistor according to a fourth embodiment of the present invention. The spin transistor of this embodiment has a configuration in which the gate insulating film 22 of the gate structure 20 is omitted from the spin transistor of the second embodiment shown in FIG. That is, the spin transistor of this embodiment has a MESFET structure.

Similarly to the second embodiment, this embodiment can also reduce the junction resistance of the magnetic material / tunnel barrier layer / semiconductor while suppressing spin relaxation due to the interaction between electrons and holes. Therefore, it is possible to suppress a decrease in the absolute value of the difference between the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes. In addition, the junction resistance of the magnetic body / tunnel barrier layer / semiconductor can be reduced.

  As in the modification of the first embodiment, the source electrode 30a and the drain electrode 30b may be configured without the tunnel barrier layer. In this case, the semiconductor layer 32a is provided between the ferromagnetic layer 34a and the semiconductor layer 31a, and the semiconductor layer 32b is provided between the ferromagnetic layer 34b and the semiconductor layer 31b.

(Fifth embodiment)
Next, FIG. 12 shows a cross section of a spin transistor according to a fifth embodiment of the present invention. The spin transistor of this embodiment is the same as the spin transistor of the first embodiment shown in FIG. 5, except that the magnetization direction of the ferromagnetic layer 34a is fixed between the ferromagnetic layer 34a of the source electrode 30a and the connection electrode 38a. A ferromagnetic layer 37a is provided, and an antiferromagnetic layer 37b for fixing the magnetization direction of the ferromagnetic layer 36b is provided between the ferromagnetic layer 36b of the drain electrode 30b and the connection electrode 38b.

  Thus, by providing the antiferromagnetic layer 37a on the ferromagnetic layer 34a and the antiferromagnetic layer 37b on the ferromagnetic layer 36b, the magnetization stability of the ferromagnetic layer 34a and the ferromagnetic layer 36b can be obtained. And stable operation can be realized.

The present embodiment also, similarly to the first embodiment, due to the interaction of electrons and holes, and the current I _D ^P when the magnetization direction is substantially parallel, the current I _D when the magnetization direction is substantially anti-parallel A decrease in the absolute value of the difference from the ^AP can be suppressed.

  As in the modification of the first embodiment, the source electrode 30a and the drain electrode 30b may be configured without the tunnel barrier layer. In this case, the semiconductor layer 32a is provided between the ferromagnetic layer 34a and the semiconductor layer 31a, and the semiconductor layer 32b is provided between the ferromagnetic layer 34b and the semiconductor layer 31b.

(Sixth embodiment)
Next, FIG. 13 shows a cross section of a spin transistor according to a sixth embodiment of the present invention. The spin transistor of this embodiment is the same as the spin transistor of the second embodiment shown in FIG. 8, except that the magnetization direction of the ferromagnetic layer 34a is fixed between the ferromagnetic layer 34a of the source electrode 30a and the connection electrode 38a. A ferromagnetic layer 37a is provided, and an antiferromagnetic layer 37b for fixing the magnetization direction of the ferromagnetic layer 36b is provided between the ferromagnetic layer 36b of the drain electrode 30b and the connection electrode 38b.

  By providing the antiferromagnetic layer 37a on the ferromagnetic layer 34a and the antiferromagnetic layer 37b on the ferromagnetic layer 36b as described above, the magnetization stability of the ferromagnetic layer 34a and the ferromagnetic layer 36b can be obtained. And stable operation can be realized.

The present embodiment also, similarly to the second embodiment, due to the interaction of electrons and holes, and the current I _D ^P when the magnetization direction is substantially parallel, the current I _D when the magnetization direction is substantially anti-parallel A decrease in the absolute value of the difference from ^AP can be suppressed, and the junction resistance of the magnetic substance / tunnel barrier layer / semiconductor can be reduced.

  As in the modification of the first embodiment, the source electrode 30a and the drain electrode 30b may be configured without the tunnel barrier layer. In this case, the semiconductor layer 32a is provided between the ferromagnetic layer 34a and the semiconductor layer 31a, and the semiconductor layer 32b is provided between the ferromagnetic layer 34b and the semiconductor layer 31b.

(Seventh embodiment)
Next, FIG. 14 shows a cross section of a spin transistor according to a seventh embodiment of the present invention. The spin transistor of this embodiment is a junction field effect spin transistor, and has a configuration in which the gate structure 20 is replaced with a gate structure 20A in the spin transistor of the first embodiment shown in FIG. The gate structure 20A includes a gate electrode 23 made of a semiconductor having a conductivity opposite to that of the semiconductor region on the semiconductor region to be the channel region 12, and a connection electrode 26 formed on the gate electrode 23. For example, when the channel region 12 is an n-type semiconductor, the gate electrode 23 is formed of a p-type semiconductor, and a pn junction is formed by the channel region and the gate electrode 23. The gate electrode 23 made of a semiconductor may be formed so as to be embedded in the inner surface portion of the channel region 12. 14 shows an n-channel spin transistor, a p-channel spin transistor may be used. In this case, the channel region is formed from a p-type semiconductor, and the gate electrode is formed from an n-type semiconductor.

As in the first embodiment of the present embodiment, the current I _D ^P when the magnetization direction is substantially parallel and the current I _D ^AP when the magnetization direction is substantially antiparallel due to the interaction of electrons and holes. A decrease in the absolute value of the difference can be suppressed.

  As in the modification of the first embodiment, the source electrode 30a and the drain electrode 30b may be configured without the tunnel barrier layer.

  Further, the gate structure 20 in the spin transistor of the second embodiment shown in FIG. 8 and the fifth embodiment shown in FIG. 12 may be replaced with the gate structure 20A of the seventh embodiment to form a junction field effect spin transistor.

(Eighth embodiment)
Next, a spin transistor according to an eighth embodiment of the present invention is shown in FIG. In the first to seventh embodiments described above, the spin transistor is a depletion type. The spin transistor of this embodiment is an enhancement type, and has a configuration in which the source electrode 30a and the drain electrode 30b are replaced with the source electrode 30Aa and the drain electrode 30Ab in the spin transistor of the first embodiment shown in FIG. Note that it is desirable that a part of the gate electrode 20 in the enhancement type is formed so as to overlap a part of the source electrode 30Aa and the drain electrode 30Ab, but the end portions thereof are the end portions of the source electrode 30Aa and the drain electrode 30Ab. You may form so that it may correspond.

  The source electrode 30Aa and the drain electrode 30Ab of the present embodiment have a configuration in which the semiconductor layer 31a and the semiconductor layer 31b of the source electrode 30a and the drain electrode 30b shown in FIG. 5 are replaced with the semiconductor layer 31Aa and the semiconductor layer 31Ab, respectively. The semiconductor layer 31 </ b> Aa and the semiconductor layer 31 </ b> Ab have different conductivity types from the semiconductor region that becomes the channel region 12 provided in the surface region of the semiconductor substrate 10.

  When the semiconductor region to be the channel region 12 is a p-type semiconductor, as shown in FIG. 23, the n-type semiconductor layers 31Aa and 31Ab have a band gap larger than the semiconductor band gap of the semiconductor region 12 and have valence electrons. The upper end of the band has lower energy than the upper end of the valence band of the semiconductor of the semiconductor region 12 in the on state (that is, a voltage is applied to the gate and the inversion layer (n-type) formed in the semiconductor region). . In this case, even if the semiconductor layer 31Ab is provided in the drain electrode 30Ab and the semiconductor layer 31Aa of the source electrode 30Aa is deleted, injection of holes that are minority carriers into the channel region 12 can be suppressed.

  When the semiconductor region to be the channel region 12 is an n-type semiconductor, the p-type semiconductor layers 31Aa and 31Ab have a band gap larger than the semiconductor band gap of the semiconductor region 12 as shown in FIG. The lower end of the conduction band has higher energy than the lower end of the conduction band of the semiconductor in the semiconductor region in the on state (that is, a voltage is applied to the gate and the inversion layer (p-type) formed in the semiconductor region 12). . In this case, even if the semiconductor layer 31Ab is provided on the drain electrode 30Ab and the semiconductor layer 31Aa of the source electrode 30Aa is deleted, injection of electrons, which are minority carriers, into the channel region 12 can be suppressed.

For this reason, also in the enhancement type spin transistor of this embodiment, as in the depletion type spin transistor of the first embodiment, the current I _D ^P when the magnetization directions are substantially parallel due to the interaction of electrons and holes, it is possible to suppress a decrease in the absolute value of the difference between the current I _D ^AP when the magnetization direction is substantially anti-parallel.

Similarly to the eighth embodiment, in the depletion type spin transistors of the second to seventh embodiments and the modifications thereof, the semiconductor layer of the source electrode and the drain electrode is made of a semiconductor having a conductivity type different from that of the semiconductor region to be the channel region 12. A structure replaced with a layer, that is, an enhancement type spin transistor may be employed. In this case, similarly to the depletion type spin transistor of the second to seventh embodiments and its modification, by interaction of electrons and holes, and the current I _D ^P when the magnetization direction is substantially parallel to the magnetization direction a decrease in the absolute value of substantially the difference between the current I _D ^AP when antiparallel can be suppressed.

  In the first to eighth embodiments described above, the magnetization directions of the ferromagnetic layers 34a, 34b, and 36b are substantially parallel to the film surface, but may be substantially perpendicular to the film surface. Here, the “film surface” means the upper surface of each layer.

  In the first to eighth embodiments described above, the ferromagnetic layer 36b may be omitted.

In the first to eighth embodiments described above, the following materials can be employed. First, in the above embodiment, an n-type or p-type silicon substrate can be used as the semiconductor substrate 10, and further, Ge, Si _x Ge _1-x (0 <x <1), III-V group, II A -VI group or II-VI group compound semiconductor, a group IV semiconductor (for example, graphite such as diamond, SiC, carbon nanotube, or graphene), a magnetic semiconductor, or the like can also be used.

The ferromagnetic layer 34a and the ferromagnetic layer 36b desirably have unidirectional anisotropy, and the ferromagnetic layer 34b desirably has uniaxial anisotropy. The thickness of each ferromagnetic layer is preferably from 0.1 nm to 100 nm. Furthermore, the film thickness of these ferromagnetic layers needs to be a thickness that does not become superparamagnetic, and is more preferably 0.4 nm or more. As the material, a Heusler alloy such as Co ₂ FeAl _1-x Si _x or Co ₂ Mn _1-x Fe _x Si can be used. Also, Co, Fe, Ni or alloys thereof, Co—Pt, Co—Fe—Pt, Fe—Pt, Co—Fe—Cr—Pt, C0—Cr—Pt, NiMnSb, Co ₂ MnGe, Co ₂ MnAl , Co ₂ MnSi, CoCrFeAl and other alloys, GeMn, SiCNi, SiCMn, SiCFe, ZnMnTe, ZnCrTe, BeMnTe, ZnVO, ZnMnO, ZnCoO, GaMnAs, InMnAs, InMnAb, GaMnP, GaMnN, GaCrN, AlCrN, BiCrTe, BiCrTe, BiCrTe, BiFeTe Selected from the group consisting of magnetic semiconductors, such as GeMnTe, CdMnGeP, ZnSiNMn, ZnGeSiNMn, BeTiFeO, CdMnTe, ZnMnS, TiCoO, SiMn, SiGeMn It may be used. In addition, Ag (silver), Cu (copper), Au (gold), Al (aluminum), Ru (ruthenium), Os (osnium), Re (rhenium), Ta (tantalum), B (boron) ), C (carbon), O (oxygen), N (nitrogen), Pd (palladium), Pt (platinum), Zr (zirconium), Ir (iridium), W (tungsten), Mo (molybdenum), Nb (niobium) ) And other nonmagnetic elements can be added to adjust the magnetic properties and various physical properties such as crystallinity, mechanical properties, and chemical properties.

As the antiferromagnetic layer, Fe-Mn (iron-manganese), Pt-Mn (platinum-manganese), Pt-Cr-Mn (platinum-chromium-manganese), Ni-Mn (nickel-manganese), Ir-Mn (Iridium-manganese), NiO (nickel oxide), Fe ₂ O ₃ (iron oxide), or the like can be used.

  As the tunnel barrier layers 33a and 33b, oxides or nitrides such as Si, Ge, Al, Ga, Mg, and Ti, SrTiO, NdGaO, and the like can be used.

The nonmagnetic layer 35b includes at least one element selected from Cu, Cr, Au, Ag, Hf, Zr, Rh, Pt, Ir, and Al, or an alloy thereof, or Si , Ge, Al, Ga, Mg, Ti and other oxides or nitrides, SrTiO, NdGaO, Si _x Ge _1-x (0 <x <1), III-V group and II-VI group A compound semiconductor or a magnetic semiconductor can be used. Further, oxides or nitrides such as Si, Ge, Al, Ga, Mg, Ti, SrTiO, NdGaO, or the like may be used.

  Each of the ferromagnetic layer 34a, the ferromagnetic layer 34b, and the ferromagnetic layer 36b has a nonmagnetic film sandwiched between a plurality of ferromagnetic films, and these ferromagnetic films are ferromagnetically coupled through the nonmagnetic film. You may have a laminated film (synthetic ferromagnetic coupling laminated film) or an antiferromagnetic coupling laminated film (synthetic antiferromagnetic coupling laminated film). For example, a laminated film of a first ferromagnetic film / nonmagnetic film / second ferromagnetic film, in which the first ferromagnetic film and the second ferromagnetic film are ferromagnetically coupled or antiferromagnetically coupled through the nonmagnetic film. It may be a membrane. Also, a laminated film of the first ferromagnetic film / first nonmagnetic film / second ferromagnetic film / second nonmagnetic film / third ferromagnetic film, or first ferromagnetic film / first nonmagnetic film / second film. A laminated film of ferromagnetic film / second nonmagnetic film / third ferromagnetic film / third nonmagnetic film / fourth ferromagnetic film may be used. In the case of having such a laminated film, the resistance to thermal disturbance can be increased even if the spin transistor is miniaturized.

  The spin transistors according to the first to eighth embodiments and the modifications thereof have been described in detail with reference to the drawings. However, the drawings are schematic, and the size of each part and the ratio of the sizes between the parts. Etc. are different from the real ones. Moreover, even in the case where the same part is inserted between the drawings, there is a part where the dimensions and ratios are different from each other.

(Ninth embodiment)
Next, a reconfigurable logic circuit according to a ninth embodiment of the invention will be described. The reconfigurable logic circuit according to this embodiment includes a depletion type spin transistor according to any one of the first, second, fifth, sixth embodiments and the modifications thereof, or an enhancement corresponding to these depletion type spin transistors. This is a logic circuit configured using a type spin transistor.

  First, a simple circuit configuration when actually used in a reconfigurable logic circuit will be described. When actually configuring a reconfigurable logic circuit using a MOS type spin transistor, it is preferable that the two MOSFETs (MOSFET 1 and MOSFET 2) have a common floating gate.

  If the AND and OR circuits can be manufactured, all circuits such as a NOR circuit and an exclusive OR circuit can be manufactured. Therefore, only the AND circuit and the OR circuit are shown in FIG. As shown in the figure, the reconfigurable logic circuit of this embodiment basically includes the gate insulation of the spin transistor of any of the first, second, fifth, and sixth embodiments and their modifications. Two spin MOSFETs 50 and 52 in which a floating gate (not shown) and an interelectrode insulating film are provided between the film 22 and the gate electrode 24 are used. The spin MOSFET 50 is a p-type MOSFET, that is, a MOSFET provided in an n-type well region (not shown) of a p-type semiconductor substrate, and the spin MOSFET 52 is an n-type MOSFET, ie, a p-type semiconductor region of a p-type semiconductor substrate. It is a provided MOSFET. The floating gates of the MOSFETs 50 and 52 are connected in common, the source of the MOSFET 50 is connected to the power source Vinp, and the source of the MOSFET 52 is grounded. Then, the drain of the MOSFET 50 and the drain of the MOSFET 52 are connected. The output V1 from the commonly connected node is input to the inverter 60, and the output of the inverter 60 is used as the output Vout of the logic circuit of this embodiment.

  Thereby, an AND circuit and an OR circuit can be formed. As shown in FIG. 17, when the floating gate voltage Vfg is ½ of the sum of the gate input A of the MOSFET 50 and the gate input B of the MOSFET 52, the spin moments of the ferromagnetic layers close to the drain and source semiconductor substrate 2 are parallel. The output voltage Y at (P) or antiparallel (AP) changes to “1” or “0”. In the present embodiment, the spin moment of the MOSFET 50 is always parallel.

  In the logic circuit of this embodiment, the MOSFETs 50 and 52 when the spin moment of the ferromagnetic layers 34a and 34b of the source electrode 30a and the drain electrode 30b of the MOSFET 52 close to the semiconductor substrate, that is, the ferromagnetic layers 34a and 34b are in the AP (antiparallel) state. FIG. 18 shows the values of the potential Vfg of the floating gate, the potential V1 of the common connection node of the MOSFETs 50 and 52, and the output Vout of the logic circuit corresponding to the values of the inputs A and B of the gate electrode. In addition, when the spin moment of the ferromagnetic layers near the semiconductor substrate of the source electrode 30a and the drain electrode 30b of the MOSFET 52, that is, the ferromagnetic layers 34a and 34b is set to the P (parallel) state, the input A of the gate electrodes of the MOSFETs 50 and 52, The values of the floating gate potential Vfg, the common connection node potential V1 of the MOSFETs 50 and 52, and the output Vout of the logic circuit corresponding to the value B are shown in FIG. As shown in FIGS. 18 and 19, an AND circuit is formed when the spin moment of the ferromagnetic layer near the semiconductor substrate 2 of the drain electrode and the source electrode of the MOSFET 52 is antiparallel, and an OR circuit when the spin moment is parallel. For this reason, by changing the spin moment of the ferromagnetic layer 34b of the drain electrode 30b and reprogramming, it is possible to configure without re-creating the logic circuit, that is, to obtain a reconfigurable logic circuit.

  In the case of an AND circuit and an OR circuit, all the transistors may be spin MOSFETs, but some normal MOSFETs may be used. As shown in FIG. 20, one of the two transistors (eg, MOSFET 52) is one of the spin MOSFETs of the first, second, fifth, and sixth embodiments and their modifications, and the other is normally used. Even when the pMOSFET 54 not using the magnetic material is used, by controlling the spin moment of the ferromagnetic layer close to the semiconductor substrate of the source electrode 30a and the drain electrode 30b of one spin MOS FTE 52 to be parallel and antiparallel, the same result is obtained. Can be obtained.

  In addition, as shown in FIG. 21, by switching the connection of the n-type MOSFET 52 and the p-type MOSFET 50 without using the inverter 60, the spin moment of the ferromagnetic layer close to the semiconductor substrate of the source and drain electrodes of the p-type MOSFET 50 can be obtained. The same effect can be obtained by controlling parallel and antiparallel.

  When used as the logic circuit, it further includes a gate voltage control circuit for reading information of the spin transistor, a sense current control element circuit for controlling the sense current, a write current control circuit, a driver, and a sinker.

  The reconfigurable logic circuit shown in the present embodiment is a specific example, and the depletion type spin transistor of any of the first, second, fifth, sixth embodiments and their modifications, or these The reconfigurable logic circuit that can be formed using the enhancement type spin transistor corresponding to the depletion type spin transistor is not limited to the reconfigurable logic circuit of this embodiment.

  It goes without saying that an integrated circuit such as a logic circuit can be configured using any of the spin transistors of the first to eighth embodiments.

  In order to realize a logic circuit using a large number of spin transistors, it is necessary to use a synthetic antiferromagnetic laminated film or a magnetic layer whose magnetization direction is perpendicular to the film surface.

Ferromagnetic films (magnetic materials) used for the synthetic antiferromagnetic multilayer film are Ni-Fe, Co-Fe, Co-Fe-Ni alloys, (Co, Fe, Ni)-(B), (Co, Fe, Ni)-(B)-(P, Al, Mo, Nb, Mn) -based or amorphous materials such as Co- (Zr, Hf, Nb, Ta, Ti) films, and Co-based full Heusler materials are selected. It is preferably composed of at least one thin film or a multilayer film thereof. Here, the Co-based full Heusler material is a material expressed as Co ₂ AB, in which A includes at least one element of Cr, Mn, Fe, V, and Ti, and B is Al. , Si, Ge, Ga, Sb, and Fe. In addition, when B contains Fe, A does not contain Fe.

  Examples of the ferromagnetic layer whose magnetization direction is perpendicular to the film surface are Fe—Pd, Fe—Pt, Fe—Pd—Pt, Co / Ni laminated film, Fe / Pd laminated film, and Fe / Pt laminated film. Ni—Fe, Co—Fe, Co—Fe—Ni alloy, or (Co, Fe, Ni) — (B), (Co, Fe, Ni) — (B), which is a film that increases the magnetoresistive effect. -Amorphous material such as (P, Al, Mo, Nb, Mn) or Co- (Zr, Hf, Nb, Ta, Ti) film, Co-based full Heusler material on the nonmagnetic layer (including tunnel barrier) side It is used by laminating. The symbol “-” indicates an alloy, the symbol “/” indicates a laminated structure, and (,) means that at least one element in parentheses is included.

The material of the nonmagnetic layer is preferably a metal element such as Cu, Ag, or Au or an alloy thereof, or an oxide such as aluminum oxide (AlO _x ), magnesium oxide (MgO), or silicon oxide (SiO _x ).

  The material of the nonmagnetic layer used for the synthetic antiferromagnetic laminated film is preferably Ru, Rh, Ir, or an alloy thereof.

  As the antiferromagnetic layer, PtMn, Ir—Mn, FeMn, Pt—Cr—Mn, or Ni—Mn is preferably used.

(10th Embodiment)
Next, a spin injection writing type magnetic memory (hereinafter also referred to as MRAM) according to a tenth embodiment of the present invention will be explained. The MRAM of this embodiment has a plurality of memory cells, and each memory cell includes the spin transistor Tr of the first to eighth embodiments as a memory element.

  In the MRAM of this embodiment, a memory cell array of MRAM is formed by providing a plurality of memory cells, for example, in a matrix. FIG. 22 is a circuit diagram showing the main part of the MRAM of this embodiment.

  As shown in FIG. 22, a plurality of memory cells 103 each having a spin transistor Tr are arranged in a matrix. One end of the memory cells 103 belonging to the same column is connected to the same bit line 82, and the other end is connected to the same bit line 92. The gate electrodes (word lines) 89 of the memory cells 103 belonging to the same row are connected to each other and further connected to the row decoder 101.

  The bit line 82 is connected to the current source / sink circuit 105 via a switch circuit 104 such as a transistor. The bit line 92 is connected to a current source / sink circuit 107 via a switch circuit 106 such as a transistor. The current source / sink circuits 105 and 107 supply a write current (inverted current) to the connected bit lines 82 and 92, and pull out from the connected bit lines 82 and 92.

  The bit line 92 is also connected to the read circuit 102. The read circuit 102 may be connected to the bit line 82. The read circuit 102 includes a read current circuit, a sense amplifier, and the like.

  At the time of writing, the switch circuits 104 and 106 connected to the memory cell to be written and the spin transistor Tr are turned on, thereby forming a current path through the target memory cell. One of the current source / sink circuits 105 and 107 functions as a current source and the other functions as a current sink according to information to be written. As a result, a write current flows in a direction corresponding to information to be written.

  As the writing speed, it is possible to perform spin injection writing with a current having a pulse width of several nanoseconds to several microseconds.

  At the time of reading, a read current that is small enough not to cause magnetization reversal by the read current circuit is supplied to the ferromagnetic layer 34b of the spin transistor Tr specified in the same manner as the write. Then, the readout circuit 102 determines the resistance state by comparing the current value or voltage value resulting from the resistance value according to the state of magnetization of the ferromagnetic layers 34a and 34b of the spin transistor Tr with a reference value.

  Note that it is desirable that the current pulse width is shorter at the time of reading than at the time of writing. As a result, erroneous writing due to current during reading is reduced. This is based on the fact that the absolute value of the write current value increases as the pulse width of the write current is shorter.

  In the MRAM of this embodiment, the magnetization directions of the ferromagnetic layer 34a of the source electrode 30a and the ferromagnetic layer 36b of the drain electrode 30b and the magnetization direction of the ferromagnetic layer 34b of the drain electrode 30b are substantially parallel or substantially. It was antiparallel.

  However, the first antiferromagnetic layer, the magnetization pinned layer, the tunnel barrier layer, the magnetization free layer, and the second antiferromagnetic layer having a thickness smaller than that of the first antiferromagnetic layer are stacked in this order. In the MRAM having the magnetoresistive effect element as a memory element, the magnetization direction of the magnetization free layer is tilted with respect to the magnetization direction of the magnetization fixed layer, thereby increasing the spin injection efficiency at the time of spin injection writing and increasing the write current density. It is known that it can be reduced (for example, JP 2007-299931 A). In this case, the first antiferromagnetic layer imparts unidirectional anisotropy to the magnetization of the pinned layer so that the magnetization direction of the pinned layer is parallel to the easy axis of magnetization of the pinned layer, and the second antiferromagnetic layer Uniaxial anisotropy is given to the magnetization of the magnetization free layer, and the magnetization direction of the magnetization free layer is tilted with respect to the magnetization easy axis of the magnetization pinned layer. It is known that the inclination angle is preferably in an angle range of greater than 0 degree and less than or equal to 45 degrees, or preferably in an angle range of not less than 135 degrees and less than 180 degrees.

  Therefore, also in the MRAM of the present embodiment, the magnetization direction of the drain electrode 30b and the ferromagnetic layer 34b is inclined with respect to the magnetization direction of the ferromagnetic layer 34a of the source electrode 30a and the ferromagnetic layer 36b of the drain electrode 30b. By doing so, the spin injection efficiency at the time of spin injection writing is increased, and the write current density can be reduced. In this case, as shown in FIG. 12, the magnetizations of the ferromagnetic layer 34a and the ferromagnetic layer 36b are given unidirectional anisotropy by the antiferromagnetic layers 37a and 37b, respectively, and the ferromagnetic layer 34b and the nonmagnetic layer 35b. Between the antiferromagnetic layers 37a and 37b, an antiferromagnetic layer (not shown) thinner than the antiferromagnetic layers 37a and 37b is inserted to give uniaxial anisotropy to the magnetization of the ferromagnetic layer 34b. The magnetization direction of the drain electrode 30b with the ferromagnetic layer 34b can be inclined with respect to the magnetization direction of the ferromagnetic layer 34a of 30a and the ferromagnetic layer 36b of the drain electrode 30b. The inclination angle at this time is in the angle range of greater than 0 degree and less than 45 degrees, or in the range of angle less than 135 degrees and less than 180 degrees, as in the MRAM described in Japanese Patent Application Laid-Open No. 2007-299931. It is preferable. The inclination angle may be clockwise or counterclockwise.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

Example 1
As this example, a spin transistor having the structure shown in FIG. 13 is manufactured. First, an element isolation region (not shown) is formed on the silicon germanium substrate 10 using a normal CMOS process. Thereafter, impurities are implanted to form a semiconductor region to be the channel region 12. Subsequently, a first semiconductor layer made of silicon and a second semiconductor layer made of silicon germanium are sequentially formed by CVD.

  Next, the first semiconductor layer and the second semiconductor layer in the gate formation region are removed using RIE (Reactive Ion Etching), and the semiconductor layer 31a and the semiconductor 31b made of the first semiconductor layer are formed on the source region and the drain region. The semiconductor layer 32a and the semiconductor layer 32b made of the second semiconductor layer are left on the semiconductor layer 31a and the semiconductor layer 31b.

Next, a silicon oxide film to be the gate insulating film 22 is grown in the gate formation region by thermal oxidation. Subsequently, polysilicon serving as the gate electrode 24 is deposited on the gate insulating film 22. Impurities are implanted into the polysilicon, and after annealing, the polysilicon is patterned using photolithography or etching to form the gate electrode 24. Thereafter, sidewalls (not shown) made of SiO ₂ are formed on the side portions of the gate electrode 24 by using a self-alignment process.

Next, using the gate electrode 24 and the side wall as a mask, the gate insulating film over the source region and the drain region is removed by RIE to expose the upper surface of the semiconductor substrate that becomes the source region and the drain region. A SiO ₂ layer to be the tunnel barrier layers 33a and 33b is formed on the exposed upper surface of the semiconductor substrate. Thereafter, a (Co ₅₀ Fe ₅₀ ) ₈₀ B ₂₀ layer having a thickness of 3 nm is formed as the ferromagnetic layer 34a and the ferromagnetic layer 34b. Subsequently, the MgO layer is formed as the nonmagnetic layer 35b, and the film thickness is formed as the ferromagnetic layer 36b. A Co ₉₀ Fe ₁₀ layer having a thickness of 3 nm is formed, and a PtMn layer having a thickness of 20 nm is deposited as the antiferromagnetic layer 37a and the antiferromagnetic layer 37b. Further, an Al layer to be the connection electrodes 26, 38a, 38b is deposited.

  After patterning each layer, an interlayer insulating film is deposited on the entire surface, contact holes are formed in the interlayer insulating film, and an Al layer serving as a contact and an Al wiring serving as a measurement electrode are formed. Finally, annealing is performed in a magnetic field at 270 ° C. for 1 hour to give magnetic anisotropy to the ferromagnetic layers 34a, 34b, and 36b.

Vd (drain voltage) dependence of I _D ^P and I _D ^AP is measured for the spin transistor of this example manufactured by the above procedure. The measurement procedure is as follows. First, by applying a threshold voltage V _th or more voltage to the electrode 126, followed by sweeping the magnetic field, the relative magnetization directions of the ferromagnetic layer 34a and the ferromagnetic layer 34b and substantially parallel, Vd dependence of I _D ^P Measure. Next, the relative magnetization directions of the ferromagnetic layer 34a and the ferromagnetic layer 34b and the _{anti-parallel,} measures the Vd dependence of ^{I D AP.}

Next, as a reference sample, the same measurement is performed on a sample in which the semiconductor layers 31a and 31b are not formed (not inserted). When the two are compared, the spin transistor in which the semiconductor layers 31a and 31b are formed has a larger absolute value of the difference between I _D ^P and I _D ^AP. It can be seen that is suppressed.

  In addition, this invention is not limited to the said embodiment and Example. For example, the channel type is not limited to the enhancement type, and a depletion type can be used. As a channel manufacturing method, not only ion implantation but also a heterointerface growth process using modulation doping may be used.

  In addition, an integrated circuit may be configured using the field effect transistors of the above-described embodiments and examples. You may comprise the memory provided with the field effect transistor and memory element of the said embodiment and an Example in a memory cell. For example, DRAM (Dynamic Random Access Memory) when combined with a dielectric capacitor, FRAM (Ferroelectric Random Access Memory) when combined with a ferroelectric capacitor, and MRAM (Magnetic Random Access Memory) when combined with a magnetoresistive element. Can be configured. Furthermore, the field effect transistors of the above embodiments and examples can be applied to the transistors of EEPROM (programmable read-only memory for electrically writing and erasing data).

  Furthermore, the drain electrode having the ferromagnetic layer 34b of the spin transistor of the above-described embodiment and examples is used as a storage portion, the data is stored as the magnetization direction of the electrode, the source electrode having the ferromagnetic layer 34a, and the drain electrode It is also possible to provide a memory that reads out the data by utilizing the magnetoresistive effect generated therebetween.

  In addition, the present invention is not limited to the above-described embodiments and examples as they are, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments and examples. For example, you may delete some components from all the components shown by embodiment and an Example. Furthermore, you may combine suitably the component covering different embodiment and an Example.

10 semiconductor substrate 12 channel region 20 gate structure 20A gate structure 22 gate insulating film 23 gate electrode 24 gate electrode 26 connection electrode 30a source electrode 30b drain electrode 31a semiconductor layer 31b semiconductor layer 32a semiconductor layer 32b semiconductor layer 33a tunnel barrier layer 33b tunnel barrier Layer 34a Ferromagnetic layer 34b Ferromagnetic layer 35b Nonmagnetic layer 36b Ferromagnetic layer 37a Antiferromagnetic layer 37b Antiferromagnetic layer 38a Connection electrode 38b Connection electrode

Claims (8)

A semiconductor substrate provided with an n-type semiconductor region on the surface;
A source electrode and a drain electrode provided on the semiconductor region, the drain electrode being provided on the semiconductor region and having a band gap larger than that of the semiconductor of the semiconductor region, and a valence band edge being the semiconductor An n-type first semiconductor layer having energy lower than a valence band edge of a semiconductor in the region; a first ferromagnetic layer provided on the first semiconductor layer; and the source electrode serving as the semiconductor region An n-type second semiconductor layer that is provided on the semiconductor region and has a band gap larger than that of the semiconductor in the semiconductor region and has an energy lower than that of the semiconductor in the semiconductor region; and the second semiconductor and a second ferromagnetic layer formed on the layer, a source electrode and a drain electrode,
A gate electrode provided in the semiconductor region between the source electrode and the drain electrode;
A spin transistor characterized in that one of the first and second ferromagnetic layers has an invariable magnetization direction and the other has a variable magnetization direction. A semiconductor substrate provided with a p-type semiconductor region on the surface;
A source electrode and a drain electrode provided apart from each other on the semiconductor region,
The drain electrode is provided on the semiconductor region, has a band gap larger than that of the semiconductor in the semiconductor region, and has an energy lower than that of the valence band edge of the inversion layer formed in the semiconductor region. The first semiconductor layer and a first ferromagnetic layer provided on the first semiconductor layer, wherein the source electrode is provided on the semiconductor region and has a larger band gap than the semiconductor of the semiconductor region; a second semiconductor layer of n-type valence electron band edge has a lower energy than the valence band edge of the inversion layer formed in the semiconductor region, and a second ferromagnetic layer formed on the second semiconductor layer A source electrode and a drain electrode,
A gate electrode provided in the semiconductor region between the source electrode and the drain electrode;
A spin transistor characterized in that one of the first and second ferromagnetic layers has an invariable magnetization direction and the other has a variable magnetization direction. A semiconductor substrate provided with a p-type semiconductor region on the surface;
A source electrode and a drain electrode provided apart from each other on the semiconductor region,
The drain electrode is provided on the semiconductor region and has a p-type first semiconductor layer having a band gap larger than that of the semiconductor in the semiconductor region and having a conduction band edge higher than the conduction band edge of the semiconductor in the semiconductor region; A first ferromagnetic layer provided on the first semiconductor layer, and the source electrode has a second ferromagnetic layer provided on the semiconductor region, and a source electrode and a drain electrode,
A gate electrode provided in the semiconductor region between the source electrode and the drain electrode;
A spin transistor characterized in that one of the first and second ferromagnetic layers has an invariable magnetization direction and the other has a variable magnetization direction. The source electrode has a band gap larger than that of the semiconductor in the semiconductor region between the semiconductor region and the second ferromagnetic layer, and has a conduction band edge higher than the conduction band edge of the semiconductor in the semiconductor region. 4. The spin transistor according to claim 3, further comprising a p-type second semiconductor layer. A semiconductor substrate provided with an n-type semiconductor region on the surface;
A source electrode and a drain electrode provided apart from each other on the semiconductor region,
The drain electrode is provided on the semiconductor region, has a band gap larger than that of the semiconductor of the semiconductor region, and has a p-type first electrode having a conduction band edge higher than that of an inversion layer formed in the semiconductor region. A source electrode and a drain electrode having a first semiconductor layer and a first ferromagnetic layer provided on the first semiconductor layer, the source electrode having a second ferromagnetic layer provided on the semiconductor region When,
A gate electrode provided in the semiconductor region between the source electrode and the drain electrode;
A spin transistor characterized in that one of the first and second ferromagnetic layers has an invariable magnetization direction and the other has a variable magnetization direction. The source electrode has a band gap larger than that of the semiconductor in the semiconductor region between the semiconductor region and the second ferromagnetic layer, and a conduction band edge of the source electrode is larger than a conduction band edge of the inversion layer formed in the semiconductor region. 6. The spin transistor according to claim 5, further comprising a p-type second semiconductor layer having high energy. It comprises two field-effect transistors, at least one of the two field effect transistors are spin transistor according to any one of claims 1 to 6, the common floating gate is provided in the two field effect transistors A reconfigurable logic circuit characterized by comprising: A spin transistor according to any one of claims 1 to 6 ;
A first bit line electrically connected to the first ferromagnetic layer;
A second bit line electrically connected to the second ferromagnetic layer;
A magnetic memory comprising: a word line electrically connected to the gate electrode.

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