CN117410339A

CN117410339A - Memory transistor, preparation method thereof, memory array and data operation method thereof

Info

Publication number: CN117410339A
Application number: CN202311385502.6A
Authority: CN
Inventors: 戴明志; 薛志彪
Original assignee: Ningbo Institute of Material Technology and Engineering of CAS
Current assignee: Ningbo Institute of Material Technology and Engineering of CAS
Priority date: 2023-10-24
Filing date: 2023-10-24
Publication date: 2024-01-16

Abstract

The present disclosure provides a memory transistor and a method of manufacturing the same, a memory array and a method of operating data thereof, wherein the memory transistor includes: a semiconductor substrate having a first surface and a second surface opposite to each other; a semiconductor layer located on a first surface of the semiconductor substrate; at least one first trench partially within the semiconductor layer, and at least one second trench extending into the semiconductor layer; a gate stack located within the first trench; the gate stack comprises a gate dielectric layer covering the bottom and the side walls of the first trench and a gate conductor wrapped by the gate dielectric layer; and a channel control region located inside the second trench and in contact with the semiconductor layer to form a junction capacitance for storing charges.

Description

Memory transistor, preparation method thereof, memory array and data operation method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a memory transistor, a preparation method thereof, a memory array and a data operation method thereof.

Background

Field effect transistors have been widely used in memory cells of memories. Common memories include Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), and FLASH memory (FLASH). The SRAM cell can maintain the logic level of the internal node in the power-up state by utilizing an interlocking structure formed by the inverters, thereby storing data. The DRAM cell charges and discharges the storage capacitor using a single transistor, thereby storing data using the storage capacitor, which has a higher storage density and lower cost than the SRAM, but charges of the storage capacitor are easily leaked, and thus the DRAM cell needs to frequently refresh data to prevent information loss. The FLASH unit stores charges by using the floating gate of a single transistor, writes charges into the floating gate or removes charges from the floating gate based on tunneling effect, and can realize data retention capacity of more than 500 hours by using the floating gate to store data, so the FLASH unit can be used as a storage unit of a solid state disk.

In chinese patent application 202110418615.6, the inventors have proposed using the channel region junction capacitance of a field effect transistor to store data to form a single transistor memory cell. The transistor has a planar transistor structure in which a channel control region extends to a channel region through an opening of a gate, thereby forming a junction capacitance with the channel region. The transistor charges and discharges the junction capacitance formed by the control region and the channel through the voltage of the electrode applying the voltage of the channel control region and the like, so that the data storage function can be realized.

Although the above-described single transistor memory cell may implement a data storage function using a charge storage function of a junction capacitance of a channel region. However, single transistors based on planar structures still have the following problems: the single transistor of the planar structure has large occupied area, thus the storage density is lower, and the area of the channel control region is limited, thus the retention time of the memory cell is shorter; the transistors in the memory array form respective sources, and wirings of the sources occupy a wafer area, so that the memory density is further reduced, and further, a large parasitic capacitance exists between the gate and the electrode wirings of the channel control region, so that the read/write speed is also limited.

Disclosure of Invention

The present disclosure provides a memory transistor, a method for manufacturing the same, a memory array, and a data operation method thereof, so as to at least solve the above technical problems in the prior art.

According to a first aspect of the present disclosure, there is provided a memory transistor comprising:

a semiconductor substrate having a first surface and a second surface opposite to each other;

a semiconductor layer located on a first surface of the semiconductor substrate;

at least one first trench partially within the semiconductor layer, and at least one second trench extending into the semiconductor layer;

A gate stack located within the first trench; the gate stack comprises a gate dielectric layer covering the bottom and the side walls of the first trench and a gate conductor wrapped by the gate dielectric layer;

and a channel control region located inside the second trench and in contact with the semiconductor layer to form a junction capacitance for storing charges.

In an embodiment, the at least one portion is located in a first trench in the semiconductor layer, including:

the first trench extends through the semiconductor layer and into the semiconductor substrate, or,

the first trench extends into the semiconductor layer.

In an embodiment, the channel control region is located inside the second trench, and includes: the channel control region is located at a lower portion of the second trench.

In an embodiment, the memory transistor further includes:

a conductor region in the semiconductor layer; wherein,

the semiconductor substrate and the conductor layer are formed as a source region and a drain region of the memory transistor, respectively, and a portion of the semiconductor layer between the first trench and the second trench is formed as a channel region of the memory transistor.

In an embodiment, the at least one first trench partially within the semiconductor layer and the at least one second trench extending into the semiconductor layer comprise:

the first groove penetrates through the conductor region and is partially located in the semiconductor layer, and the second groove penetrates through the conductor region and extends into the semiconductor layer;

the memory transistor further includes: a first insulating layer covering the channel control region and located at an upper portion of the second trench; wherein,

the top surface of the channel control region is lower than the bottom surface of the drain region, and the first insulating layer isolates the channel control region and the drain region.

In one embodiment, the channel control region includes a channel control region at least partially surrounding the gate stack to obtain a predetermined junction area.

In an embodiment, the channel control region includes a plurality of channel control regions spaced around the gate stack and respectively contacting the semiconductor layer to form a plurality of junction capacitances.

According to a second aspect of the present disclosure, there is provided a method of manufacturing a memory transistor, comprising:

Providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite to each other;

forming a semiconductor layer on a first surface of the semiconductor substrate;

forming at least one first trench partially within the semiconductor layer;

forming a gate stack located in the first trench, wherein the gate stack comprises a gate dielectric layer covering the bottom and the side wall of the first trench and a gate conductor wrapped by the gate dielectric layer;

forming at least one second trench extending into the semiconductor layer;

a channel control region is formed inside the second trench, the channel control region being in contact with the semiconductor layer to form a junction capacitance for storing charge.

In an embodiment, the forming at least one first trench partially within the semiconductor layer includes:

a first trench is formed through the semiconductor layer and extending into the semiconductor substrate, or,

a first trench is formed extending into the semiconductor layer.

In an embodiment, the forming a channel control region located inside the second trench includes: a channel control region is formed at a lower portion of the second trench.

In an embodiment, the method further comprises:

forming a conductor region in the semiconductor layer; wherein,

In an embodiment, the forming at least one first trench partially within the semiconductor layer and forming at least one second trench extending into the semiconductor layer includes:

forming a first trench extending through the conductor region and partially within the semiconductor layer, and forming a second trench extending through the conductor region and into the semiconductor layer;

the method further comprises the steps of: forming a first insulating layer covering the channel control region and positioned at the upper part of the second trench; wherein,

In an embodiment, the channel control region is processed through doping process, deposition process, epitaxy process, self-assembly process, spin-coating process, self-assembly process, roll-to-Roll process, hydrothermal process, embossing process, rolling process, printing process, or vapor deposition process.

According to a third aspect of the present disclosure, there is provided a memory array including a plurality of the memory transistors described in any one of the above embodiments, the plurality of memory transistors being arranged in an array along a row and column direction;

a plurality of word lines, the gate conductors of the memory transistors in the same row being connected to the same word line;

a plurality of first bit lines to which channel control regions of memory transistors located in the same row or the same column of the plurality of memory transistors are connected;

a plurality of second bit lines to which drain regions of memory transistors located in the same column of the plurality of memory transistors are connected;

Wherein the source regions of a plurality of the memory transistors are connected to a fixed potential, the plurality of first bit lines are for applying a control region voltage in a write operation, the plurality of second bit lines are for applying a drain voltage in a write operation and a read operation, and for detecting a drain current in a read operation, the drain current being used to characterize a memory state of the memory transistors.

In one embodiment, a plurality of the memory transistors share a semiconductor substrate to form a common source structure.

According to a fourth aspect of the present disclosure, there is provided a data operation method of a memory array, applied to the memory array described in any one of the above embodiments, the method including:

in a write operation, applying a gate voltage via a selected one of the plurality of word lines and a drain voltage via a selected one of the plurality of second bit lines to place a selected memory transistor in an on state, and applying a control region voltage to the selected memory transistor via a selected one of the plurality of first bit lines to change a memory state of the selected memory transistor;

in a read operation, a gate voltage is applied via a selected one of the plurality of word lines and a drain voltage is applied via a selected one of the plurality of second bit lines to place a selected memory transistor in an on state, and a drain current of the selected memory transistor is detected via a selected one of the plurality of second bit lines to obtain a memory state of the selected memory transistor.

In one embodiment, the plurality of first bit lines are disconnected or connected to a fixed potential during a read operation.

In one embodiment, the memory transistor includes a plurality of channel control regions to which respective control region voltages are applied in a write operation to write a digital value of a plurality of bits, and a drain current commonly modulated by the plurality of channel control regions is detected in a read operation to read the digital value of the plurality of bits.

According to the memory transistor, the preparation method thereof, the memory array and the data operation method thereof, the channel control region which is in direct contact with the semiconductor layer is formed to form the junction capacitance for storing charges, so that charges can be stored by directly utilizing the junction capacitance of the channel region of the memory transistor without containing a separate storage capacitance, the wafer area occupied by a memory cell is obviously reduced, and the storage density of a memory device can be obviously improved. And the storage transistor provided by the embodiment of the disclosure is a transistor with a vertical structure, and the source region and the drain region of the storage transistor are respectively positioned on the opposite surfaces of the semiconductor layer, so that the total chip area of the source region and the drain region can be reduced, the limit of the gate length can be reduced, the wiring is more flexible, and the total wiring area of the source electrode and the drain electrode can be reduced. Therefore, the cell size of the memory transistor can be reduced for each memory cell, thereby improving the storage density of the memory.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

FIG. 1 is a cross-sectional view of a planar memory transistor;

FIG. 2 is a transfer characteristic of a memory transistor;

FIG. 3 is a three-dimensional view of a memory transistor provided by an embodiment of the present disclosure;

FIG. 4 is a cross-sectional view of the memory transistor shown in FIG. 3;

FIG. 5 is a cross-sectional view of a memory transistor according to other embodiments of the present disclosure;

FIG. 6a is a second cross-sectional view of a memory transistor according to other embodiments of the present disclosure;

FIG. 6b is a third cross-sectional view of a memory transistor provided by other embodiments of the present disclosure;

FIG. 6c is a cross-sectional view of a memory transistor according to other embodiments of the present disclosure;

Fig. 7 is a flowchart of a method for manufacturing a memory transistor according to an embodiment of the present disclosure;

fig. 8a to 8h are schematic diagrams of a memory transistor according to an embodiment of the present disclosure in a manufacturing process;

FIG. 9 is a circuit diagram of a two-dimensional memory array provided by an embodiment of the present disclosure;

FIG. 10 is a circuit diagram of a two-dimensional memory array according to another embodiment of the present disclosure;

FIG. 11 is a circuit diagram of a three-dimensional stacked memory array formed from the memory array of FIG. 10;

FIG. 12 is a flow chart of a method of data manipulation of a memory array provided by an embodiment of the present disclosure;

FIG. 13 is a schematic diagram illustrating a write operation to a memory cell in the memory array of FIGS. 9 and 10;

FIG. 14 is a schematic diagram illustrating a read operation of memory cells in the memory array of FIGS. 9 and 10;

fig. 15 shows data retention characteristics of memory transistors in the memory arrays shown in fig. 9 and 10.

Detailed Description

In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

Fig. 1 is a cross-sectional view of a planar memory transistor. As shown in fig. 1, the memory transistor 10 is similar in structure to a planar MOSFET (metal-oxide-semiconductor field effect transistor) structure, with the main difference being that the memory transistor 10 further includes an additional channel control region.

Referring to fig. 1, a source region 12 and a drain region 13 are formed in a semiconductor substrate 11. For an N-channel transistor, the semiconductor substrate 11 is, for example, a P-type doped monocrystalline silicon substrate, and the source region 12 and the drain region 13 are, for example, N-type doped regions. The source region 12 and the drain region 13 extend downward to a predetermined depth, for example, from the surface of the semiconductor substrate 11. A gate stack consisting of a gate dielectric layer 14 and a gate conductor 15 is formed on a semiconductor substrate 11. A gate stack is located at least over a portion of the semiconductor substrate 11 between the source region 12 and the drain region 13, a channel region is formed at a portion of the semiconductor substrate 11 between the source region 12 and the drain region 13, and an electric field generated by the gate conductor 15 acts on the channel region to control an on state of the memory transistor 10.

The memory transistor 10 will be described in detail with an N-channel transistor as an example. However, the memory transistor 10 may be any one of an N-channel transistor and a P-channel transistor, and layers and doped regions in the memory transistor have respective doping types according to channel types.

Channel control regions 16 are formed in the semiconductor substrate 11 at the sides and/or bottom of the channel region. The channel control region 16 is composed of, for example, a conductor, a semiconductor, or any stack of a conductor and a semiconductor. The channel control region is to store charge in capacitance with the channel forming junction. The conductor includes at least one selected from the group consisting of metal, alloy, ITO, doped silicon, doped polysilicon, metal nitride, and metal silicide. Preferably, the metal comprises at least one selected from Pt, pd, au, ni, ag, cu, al, mo, in, ti. For example, the channel control region 16 is composed of Pt. The channel control region 16 is in direct contact with the channel region to form a junction capacitance, such as a schottky junction capacitance. In the on state of the memory transistor 10, a suitable voltage is applied via the gate electrode, the drain electrode, the source electrode, and the channel electrode, and by a combined action, charge is stored and released in the junction capacitance, thereby realizing a write operation of the memory transistor 10, and in the on state of the memory transistor 10, the drain current Ids (i.e., channel current) of the memory transistor 10 is obtained under a predetermined bias condition for characterizing the storage state of the charge.

Further, referring to the transfer characteristic curve of the memory transistor shown in fig. 2, the drain current Ids of the memory transistor 10 is obtained under a predetermined bias condition before and after writing, and it can be seen that the writing operation of the memory transistor 10 causes a significant change in the drain current Ids. That is, the drain current of the memory transistor that is not written to is smaller than the drain current of the memory transistor that is written to.

For application scenarios such as memory arrays, the planar memory transistor shown in fig. 1 has an adverse effect on the memory density and read-write speed of the memory array. The source, drain, gate and channel electrodes of the planar memory transistor are located on the same side surface of the semiconductor substrate and wiring layers of the source, drain, gate and channel electrodes are formed on the same side surface, and thus, the doped region and wiring layers of the memory transistor each occupy a considerable wafer area, making it difficult to increase the memory density of the memory array. Further, the gate conductor and the channel electrode of the memory transistor extend laterally in the same direction, and an opening is formed in the gate to provide a conductive path for the channel electrode, and therefore, there is coupling between the gate of the memory transistor and the wiring of the channel electrode, thereby generating parasitic capacitance, making it difficult to increase the read/write speed of the memory array.

Based on this, the embodiment of the disclosure provides a memory transistor, fig. 3 is a three-dimensional diagram of the memory transistor provided by the embodiment of the disclosure, fig. 4 is a cross-sectional diagram of the memory transistor shown in fig. 3, and fig. 5 is a cross-sectional diagram of the memory transistor provided by another embodiment of the disclosure.

As shown in fig. 3 to 5, the memory transistor 100 includes:

a semiconductor substrate 101, the semiconductor substrate 101 having a first surface and a second surface opposite to each other;

a semiconductor layer 102 on a first surface of the semiconductor substrate 101;

at least one first trench (not identified) partially within the semiconductor layer, and at least one second trench (not identified) extending into the semiconductor layer 102;

a gate stack located within the first trench; the gate stack comprises a gate dielectric layer 104 covering the bottom and sidewalls of the first trench and a gate conductor 105 surrounded by the gate dielectric layer 104;

a channel control region 106 is located inside the second trench and contacts the semiconductor layer 102 to form a junction capacitance for storing charge.

In an embodiment, the at least one first trench partially within the semiconductor layer 102 comprises: the first trench penetrates the semiconductor layer 102 and extends into the semiconductor substrate 101, or the first trench extends into the semiconductor layer 102.

Specifically, in some embodiments, as shown in fig. 4, the first trench extends through the semiconductor layer 102 and into the semiconductor substrate 101.

In other embodiments, as shown in fig. 5, the first trench extends into the semiconductor layer 102 and does not extend through the semiconductor layer 102. Although the first trench does not penetrate the semiconductor layer, the gate stack formed in the first trench may control the entire channel.

In one embodiment, the memory transistor 100 further comprises: a conductor region 103 located in the semiconductor layer 102; wherein,

the semiconductor substrate 101 and the conductor region 103 are formed as a source region and a drain region of the memory transistor 100, respectively, and a portion of the semiconductor layer 102 between the first trench and the second trench is formed as a channel region of the memory transistor 100.

The conductor region 103 may be a doped region, a deposited region, a conductive region, an evaporation region, and an imprint region.

In this embodiment, the memory transistor 100 will be described in detail by taking an N-channel transistor as an example. The semiconductor substrate 101 is, for example, an N-type doped single crystal silicon substrate, and can be used as a source region of the memory transistor 100, and the conductor region 103 is, for example, an N-type doped region, and can be used as a drain region of the memory transistor 100. The semiconductor layer 102 is, for example, a P-type doped epitaxial layer. However, the present disclosure is not limited thereto, and the memory transistor 100 may be any one of an N-channel transistor and a P-channel transistor, and layers and conductor regions in the memory transistor have respective doping types according to channel types.

In one embodiment, a gate stack comprised of a gate dielectric layer 104 and a gate conductor 105 is formed in a first trench. A gate dielectric layer 104 is located on the bottom and sidewalls of the first trench and a gate conductor 105 is located within the first trench, the gate dielectric layer 104 separating the gate conductor 105 from the semiconductor substrate 101, the semiconductor layer 102 and the conductor region 103. In the on state of the memory transistor 100, a channel region extending substantially vertically from one surface to the other surface of the semiconductor layer 102 is formed in the semiconductor layer 102 along the sidewall of the first trench under the voltage applied to the gate conductor 105.

In a specific embodiment, the gate stack fills the first trench.

In the present embodiment, the gate dielectric layer 104 of the memory transistor 100 is composed of, for example, silicon oxide, and the gate conductor 105 is composed of, for example, doped polysilicon.

Further, the gate dielectric layer 104 may further include one or more of ferroelectric material, magneto-electric material, phase change material, quantum effect material, resistive effect material, memory effect material, semiconductor material, conductor material, superconducting material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, and silicide.

The above-mentioned materials may also be used as an insulating layer additive layer, an insulating layer material, an insulating layer additive material, a semiconductor layer material, a semiconductor channel material, or a channel electrode material.

Optionally, the ferroelectric material is H ₃ S、NbN、LaH ₁₀ 、BaTiO ₃ 、PbZr _x Ti _1-x O ₃ 、BiFeO _3、 CIPS(CuIn _x P _(3-x) S _y For example CuInP ₂ S ₆ )、HZO(HfZrO _x )、MoTe ₂ 、ZrTiO ₄ 、PbTiO ₃ 、Ba(Zr,Ti)O ₃ 、SrTiO ₃ 、BaWO ₄ 、BaFe ₁₂ O ₁₉ 、YBCO(YBa ₂ Cu ₃ O _7-x For example YBa ₂ Cu ₃ O ₇ )，BFMO(BiFe _1-x MnxO ₃ For exampleBiFe _0.9 Mn _0.1 O ₃ )，PCMO(Pr _1-x CaxMnO ₃ For example Pr _0.7 Ca _0.3 MnO)，LBCO(La _2-x BaxCuO ₄ For example La _1.9 Ba _0.1 CuO ₄ )，SmFeAsO _1-x Fx (e.g. SmFeAsO _0.85 F _0.15 )，CaK(Fe _1-x Mx) ₄ As ₄ (e.g. CaKFE ₄ As ₄ )，NdFe _1-x MxAsO _0.85 (e.g. NdFeAsO) _0.85 ) Etc.

Optionally, the phase change material is VO _2、 Ge ₁₅ Sb _85、 Ga ₃₆ Sb _64、 Fe ₃ O _4、 NbO _2、 PEG((C ₂ H ₄ O) n), an alloy of indium (In) and tin (Sn), C ₆₀ 、C ₇₀ Etc.; RMS (Re) _x Mo _1-x S ₂ )、GST((GeTe) _x (Sb ₂ Te ₃ ) _y ，AIST((Ag _1-x In _x )(Sb _1- _x Te _x ) ₂ For example Ag ₅ In ₅ Sb ₆₀ Te ₃₀ ) GSST (e.g. Ge ₂ Sb ₂ Se ₁ Te ₄ ,Ge ₂ Sb ₂ Se ₄ Te ₁ )，Gd ₅ (Si ₁ Ge _1-X ) ₄ (e.g. Gd ₅ Si ₂ Ge ₂ )，LaFe _13-x Si _x (e.g. LaFe ₁₂ Si)，La _0.5 Pr _0.5 Fe _11.5-x Co _x Si _1.5 C _0.2 (e.g. La _0.5 Pr _0.5 Fe _10.7 Co _0.8 Si _1.5 C _0.2 (e.g. Ge ₂ Sb ₂ Te ₅ )、Sb ₂ Te ₃ 、GSB((GeSn) _x (Sb) _y (e.g., geSnSb), AST ((AlSb) ₂ ) _x (Te) _y For example Al _1.5 Sb ₃ Te)、TASG(Ti ₄₈ As ₃₀ Si ₁₂ Ge ₁₀ ) One or more of them.

Optionally, the magneto-electric material is ZrTiO ₄ 、Fe ₂ O ₃ 、Fe ₃ O ₄ 、SrBaTiO ₃ 、Sr _1-x Ba _x TiO ₃ 、Bi ₄ Ge ₃ O ₁₂ 、BaTiO ₃ 、Ba _0.8 Sr _0.2 TiO ₃ 、NiO、NiZnFe ₂ O ₄ 、LiNbO ₃ 、BTO-PZT、BaFe ₁₂ O ₁₉ 、Cr ₂ O ₃ 、BiFeO ₃ 、BiMnO ₃ And LuFe ₂ O ₄ 、FCSB(Fe ₉₀ Co ₇₈ Si ₁₂ B ₁₀ )、PMN-PZT((Pb(Mg _1/3 Nb _2/3 )O ₃ ) _1-x -(Pb(Zr _1-y Ti _y )O ₃ ) _x For example Pb (Mg) _x Nb _1-x )O ₃ -PbZrO ₃ -PbTiO ₃ )、PMN-PT((Pb(Mg _1/3 Nb _2/3 )O ₃ ) _1-x -(PbTiO ₃ ) _x For example Pb (Mg) _1/3 Nb _2/3 )O ₃ -PbTiO ₃ ) One or more of them.

Optionally, the quantum effect material is YBCO, pbLaTiO ₃ CdSe, gaAs, pbSe, BBO, PPLN and lead, zinc and tin alloys. Cold atomic gas (such as rubidium, lithium, sodium), magnetic materials such as iron, nickel, cobalt, etc.

Optionally, the resistive effect material is ZrO ₂ 、TiO、Ta ₂ O ₅ 、BiFeO ₃ 、SrRuO、SrZrO、Fe ₃ O ₄ 、ZnFe ₂ O ₄ 、BaTiO ₃ 、Pb(Mg _1/3 Nb _2/3 )O ₃ -PbTiO ₃ 、Ba(Sr _0.7 Ba _0.3 )TiO ₃ 、In ₂ O ₃ -SnO ₂ 、Cu ₂ ZnSnSe ₄ Polystyrene (PS), la1-xSrxMnO ₃ 、(Pb,Fe)NbO ₃ CuO _x (e.g. CuO _0.5 )、MoS _2-x O (e.g. MoS) ₂ O ₄ )、HfO _x (e.g. HfO) ₂ )、WO _X (e.g. WO ₂ )、PCMO(Pr _1-x Ca _x MnO, e.g. Pr _0.7 Ca _0.3 MnO)、LSMO(La _x Sr _1-x MnO, e.g. La _0.5 Sr _0.5 MnO ₃ )、LCMO(La _x Ca _1-x MnO, e.g. La _0.7 Ca _0.3 MnO ₃ ) Etc.

Optionally, the storage effect material is Fe ₃ O ₄ 、Fe ₂ O ₃ CoFe (cobalt-iron alloy), feCo, feAlSi, fePt, mnFe, feNi, coPt, coFeB, sbI ₃ Polycarbonate, si ₃ N ₄ 、SiO ₂ 、SiO _x N _y 、Se、BaFe ₁₂ O ₁₉ 、NiFe、AgCl、AgBr、Ge ₂ Sb ₂ Te ₅ 、GeSbTe、Al ₂ O ₃ /Fe、FeAlO _x Polyaniline (PANI).

Optionally, the superconducting material is H ₂ S、CeCu ₂ Si、CeTIn ₅ 、CePt ₃ Si、Ba _0.6 K _0.4 Fe ₂ As ₂ 、LaNiC ₂ 、LaNiGa ₂ 、CaPtAs、Y ₃ Fe ₅ O ₁₂ /Al、2H-MX ₂ (M＝transition metals；X＝chalcogenides)、2H-NbSe ₂ 、(magic-angle twisted trilayer graphene)(MATTG)、2H-WS ₂ 、2HeTaS ₂ 、1Td-MoTe ₂ 、W ₂ N ₃ 、1T-PdTe ₂ 、Pb _10-x Cu _x (PO ₄ ) ₆ 、(Li,Fe)OHFeSe、CuInCo ₂ Te ₄ 、YBa ₂ Cu ₃ O ₇ (yttrium alloy copper oxide), ba (Fe 1-xCox) ₂ As ₂ 、Pb、MgB ₂ 、CuInSe ₂ 、LaFeAsO、Ba(Fe,Co) ₂ As ₂ 、BSCCO、GdBCO、IBi ₂ Sr ₂ Ca ₂ Cu ₃ O ₁₀ (BSCCO)、T _l2 Ba ₂ CuO ₆ 、YBa ₂ Fe ₃ Se ₅ Etc.

Optionally, the semiconductor effect material is Si, in ₂ Se ₃ 、GaAs、GaP、CdSe、ZnSe、PbSe、BN、ZnS、PbS、InP、GaN、Al ₂ Se ₃ AlAs, inAs, siGe, cdSe, etc.

Optionally, the perovskite material is CsPbBr ₃ 、MAPbI _3-x Cl _x 、SBT(SrBi _1-x Ti _x O ₉ For example SrBiTiO ₉ )、BLT(Bi _4-x La _x Ti ₃ O ₁₂ For example Bi _3.5 La _0.5 Ti ₃ O ₁₂ )、PZT(PbZr _1-x T _ix O ₃ . For example PbZr _0.7 Ti _0.3 O ₃ )、Cs _-x FA _x PbBr, e.g. Cs _0.8 FA _0.2 PbBr、CH ₃ NH ₃ PbX ₃ (e.g. CH ₃ NH ₃ PbBr、CH ₃ NH ₃ PbI)。

Optionally, the two-dimensional material is GaS, h-BN, as ₂ Te ₃ 、Bi ₂ S ₃ 、2H-WS ₂ 、GaSe、GeS、GeSe、HfS ₂ 、HfSe ₂ 、In ₂ Se ₃ 、MoS ₂ 、2H-MoS ₂ 、MoTe ₂ 、MoSe ₂ 、MoSSe、MoWS ₂ 、MoWSe ₂ 、ReS ₂ 、ReSe ₂ 、Sb ₂ Te ₃ 、SnS ₂ 、SnSe ₂ 、1T-TaS ₂ 、WSe ₂ 、ZrSe ₂ 、ZrSe ₃ ACS, etc.

In this embodiment, the gate stack includes one gate stack.

In other embodiments, the gate stack includes a plurality of gate stacks, and the plurality of gate stacks respectively control the channel therebetween in combination with at least one channel control region.

In an embodiment, the at least one first trench partially within the semiconductor layer and the at least one second trench extending into the semiconductor layer 102 comprise:

the first trench penetrates the conductor region 103 and is partially located in the semiconductor layer 102, and the second trench penetrates the conductor region 103 and extends into the semiconductor layer 102;

in an embodiment, the channel control region 106 is located inside the second trench, and includes: the channel control region 106 is located in a lower portion of the second trench.

In a specific embodiment, the trench control region fills the interior of the second trench.

The memory transistor 100 further includes: a first insulating layer 107 covering the channel control region 106 and located at an upper portion of the second trench; wherein,

the top surface of the channel control region 106 is lower than the bottom surface of the drain region (conductor region) 103, and the first insulating layer 107 isolates the channel control region 106 from the drain region 103.

A channel control region 106 and a first insulating layer 107 are formed in the second trench and on the second trench, respectively, the channel control region 106 having a top surface lower than the bottom surface of the conductor region 103, the first insulating layer 107 isolating the two from each other. In the memory transistor 100, the channel control region 106 is in direct contact with the semiconductor layer 102, the channel control region 106 is composed of a conductive material, for example, a metal, the semiconductor layer 102 is composed of a P-type semiconductor, and a junction capacitance is formed between the channel control region 106 and the semiconductor layer 102.

In this embodiment, the channel control region 106 is composed of, for example, a conductor, a semiconductor, or an arbitrary stack of a conductor and a semiconductor. Preferably, the conductor comprises at least one selected from the group consisting of metal, alloy, ITO, doped silicon, doped polysilicon, metal nitride, and metal silicide. Preferably, the metal comprises at least one selected from Pt, pd, au, ni, ag, cu, al, mo, in, ti. For example, the channel control region 106 is composed of Pt. The material of the first insulating layer 107 includes an insulating material.

In this embodiment, the channel control region 106 includes one channel control region that at least partially surrounds the gate stack to obtain a predetermined junction area.

The memory transistor further includes: a second insulating layer 110 on the conductor region 103; a drain electrode 121, a gate electrode 123 and a channel electrode 124 on the second insulating layer, and a source electrode 122 on the second surface of the semiconductor substrate 101.

The second insulating layer 110 covers the surface of the conductor region 103 as an interlayer dielectric layer. The drain electrode 121 is connected to the conductor region 103 via a first conductive via (conductive via) 111 penetrating the second insulating layer 110. The gate 123 is connected to the gate conductor 105 via a second conductive via 113 through the second insulating layer 110. The channel electrode 124 is connected to the channel control region 106 via a third conductive path 114 penetrating the second insulating layer 110 and the first insulating layer 107.

The material of the second insulating layer 110 includes an insulating material.

In the present embodiment, the channel control region 106 of the memory transistor 100 is adjacent to one side surface of the gate conductor 105, and the channel control region 106 and the gate conductor 105 respectively extend substantially vertically in the semiconductor layer 102. A gate dielectric layer 104 is sandwiched between the gate conductor 105 and the semiconductor layer 102, and a gate voltage applied to the gate conductor 105 acts on an adjacent region of the semiconductor layer 102 in a write operation and a read operation, thereby forming a substantially vertically extending channel extending from one surface to the other surface of the semiconductor layer 102 between the gate conductor 105 and the channel control region 106. The channel control region 106 is in direct contact with the semiconductor layer 102 to form a junction capacitance.

In a write operation, a control region voltage applied across the channel control region 106 stores charge on the junction capacitance or discharges charge from the junction capacitance into the channel. The storage state of the storage transistor 100 is related to the charge state of the junction capacitance, and in a read operation, the storage state of the storage transistor 100 is obtained by detecting a change in the drain current (i.e., channel current) of the storage transistor 100.

The memory transistor 100 is a vertical structure transistor, as compared to a planar memory transistor, in which the source and drain regions of the memory transistor 100 are located on opposite surfaces of the semiconductor layer 102, respectively. Not only can the total chip area of the source and drain regions be reduced, but also the gate length limitations, the wiring is more flexible, and the total wiring area of the source and drain can be reduced as compared to planar transistors. Therefore, the cell size of the memory transistor 100 can be reduced for each memory cell, thereby improving the storage density of the memory. Further, the semiconductor substrate 101 of the memory transistor 100 serves as a source region, and for a memory array, a "common source structure" of a plurality of memory transistors may be formed using the semiconductor substrate 101. Therefore, the use of the "common source structure" for a plurality of memory cells can reduce the number of wirings and the wiring area of the source.

In the present embodiment, the source electrode 122 is formed on the second surface (i.e., the back surface) of the semiconductor substrate 101. In an alternative embodiment, the source electrode 122 may be formed on the surface of the second insulating layer 110. In this case, for example, the source electrode 122 is patterned from the same metal layer as the drain electrode 121, and the source electrode 122 is connected to the semiconductor substrate 101 via a conductive path. For multiple memory cells, a "common source structure" is used, and the memory transistors of the multiple memory cells may share a common source 122. The use of the "common source structure" can reduce the number of wirings and the wiring area of the source electrode, whether the source electrode 122 is located on the front surface or the back surface of the semiconductor substrate 101, further reducing the overall size of the memory array, thereby improving the memory density of the memory.

In contrast to planar memory transistors, memory transistor 100 is a vertical structure transistor in which gate conductor 105 and channel control region 106 are located in a first trench and a second trench, respectively. In contrast to the planar transistor, the channel control region 106 of the memory transistor 100 is located only inside the second trench, and the channel electrode 124 is connected to the channel control region 106 via the third conductive path 114. With the first insulating layer 107 and the second insulating layer 110, the channel control region 106 and the conductor region 103 of the memory transistor and the electrode wiring are isolated from each other, and thus parasitic capacitance associated with the channel control region 106 can be reduced to improve the read-write speed of the memory device.

In an embodiment, as shown in fig. 6a, the memory transistor further includes: a first insulator 108, the first insulator 108 penetrating the semiconductor substrate (source region) 101 and the source electrode 122. The first insulator 108 may be located on a side of the channel control electrode 106 remote from the gate conductor 105 and/or between the channel control electrode 106 and the gate conductor 105 and/or on a side of the gate conductor 105 remote from the channel control electrode 106.

In an embodiment, as shown in fig. 6b, the memory transistor further includes: a second insulator 109, said second insulator 109 extending through the entire memory transistor, i.e. from the drain of the top layer to the source of the bottom layer.

In this embodiment, by adding the first insulator and the second insulator, the source regions, the semiconductor layers, the channel regions, the drain regions, and the drain regions of the respective transistors can be isolated from each other, thereby reducing leakage current therebetween.

Fig. 6c is a cross-sectional view of a memory transistor provided in accordance with yet another embodiment of the present disclosure.

The structure in the embodiment shown in fig. 6c is similar to that in the embodiment shown in fig. 4, and thus the same structure will be described with reference to the embodiment shown in fig. 4, and will not be repeated here.

The only difference is that the channel control region 106 includes a plurality of channel control regions spaced around the gate stack and respectively in contact with the semiconductor layer 102 to form a plurality of junction capacitances.

As shown in fig. 6c, the memory transistor 200 includes a second trench and a third trench penetrating the conductor region 103 and extending into the semiconductor layer 102, and a channel control region 106 and a first insulating layer 107 formed inside and on the second trench, respectively, and a channel control region 108 and a first insulating layer 109 formed inside and on the third trench, respectively.

Further, the memory transistor 200 further includes channel electrodes 124 and 125, the channel electrode 124 is connected to the channel control region 106 via a third conductive path 114 penetrating the second insulating layer 110 and the first insulating layer 107, and the channel electrode 125 is connected to the channel control region 108 via a third conductive path 115 penetrating the second insulating layer 110 and the first insulating layer 109.

In this embodiment, the channel control regions 106 and 108 of the memory transistor 200 are adjacent to opposite surfaces of the gate conductor 105, and the channel control regions 106 and 108, respectively, the gate conductor 105 extend substantially vertically in the semiconductor layer 102. A gate dielectric layer 104 is sandwiched between the gate conductor 105 and the semiconductor layer 102, and a gate voltage applied to the gate conductor 105 is applied to adjacent regions of the semiconductor layer 102 in write and read operations, thereby forming first and second channels extending substantially vertically from one surface to the other surface of the semiconductor layer 102 between the gate conductor 105 and the channel control regions 106 and 108. The channel control regions 106 and 108 are in direct contact with the semiconductor layer 102 to form a first junction capacitance and a second junction capacitance.

The memory transistor 200 shown in fig. 6c may form two channel control regions and two junction capacitances using a three-trench structure, as compared to the vertical structure transistor shown in fig. 4. The charge state of the two junction capacitances can thus be changed independently by applying a control region voltage Vc across the two channel control regions. Thus, the memory transistor according to the embodiment shown in fig. 5 can realize a 2-bit memory cell using two junction capacitances of a single transistor, further improving the memory density of the memory array using the multi-bit memory characteristic. For example, with two junction capacitances, four memory states corresponding to the digital values 00, 01, 10, 11 can be stored.

In an alternative embodiment, the memory transistor includes a channel control region formed in a second trench surrounding the first trench, thereby increasing a contact area between the channel control region and the semiconductor layer to increase junction capacitance, and thus, a retention time of the memory device may be increased.

The memory transistors of the present disclosure may be used in a cell of a memory integrated array to change the memory state of a plurality of memory transistors by applying different gate electrode and control region voltages across the plurality of memory transistors and to take this as a computational cell.

The design of the memory transistor has multifunction, and not only can realize a logic gate function, but also can realize a bionic function. Logic gate function: through appropriate circuit connections and input signal control, the transistors may generate corresponding output logic states, such as AND, OR, NOT, NAND, NOR, XOR, AND, OR, logic, based on the input signals; complex digital logic operations can be implemented by basic logic gates. Besides the logic gate function, the transistor of the invention can also be applied to bionic circuits and neural network simulation. The bionic function is to simulate the characteristics and behaviors of a biological nervous system and realize the calculation and treatment of similar biological neurons.

The embodiment of the disclosure also provides a method for manufacturing a memory transistor, referring to fig. 7, and as shown in fig. 7, the method for manufacturing a memory transistor includes the following steps:

step 701: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite to each other;

step 702: forming a semiconductor layer on a first surface of the semiconductor substrate;

step 703: forming at least one first trench partially within the semiconductor layer;

Step 704: forming a gate stack located in the first trench, wherein the gate stack comprises a gate dielectric layer covering the bottom and the side wall of the first trench and a gate conductor wrapped by the gate dielectric layer;

step 705: forming at least one second trench extending into the semiconductor layer;

step 706: a channel control region is formed inside the second trench, the channel control region being in contact with the semiconductor layer to form a junction capacitance for storing charge.

The method for manufacturing the memory transistor according to the embodiments of the present disclosure is described in further detail below with reference to specific embodiments. Fig. 8a to 8h are schematic diagrams of a memory transistor according to an embodiment of the disclosure in a manufacturing process.

Referring first to fig. 8a, step 701 is performed to provide a semiconductor substrate 101, the semiconductor substrate 101 having a first surface and a second surface opposite to each other.

The semiconductor substrate 101 is, for example, an N-type doped silicon substrate.

With continued reference to fig. 8a, a step 702 is performed of forming a semiconductor layer 102 on a first surface of the semiconductor substrate 101.

Continuing next with fig. 8a, in the method further comprises: a conductor region 103 is formed in the semiconductor layer 102.

The semiconductor layer 102 is, for example, a P-type doped silicon epitaxial layer, and the conductor region 103 is, for example, an N-type doped conductor region. The conductor region 103 extends downward from the surface of the semiconductor layer 102 by a predetermined distance but does not reach the first surface of the semiconductor substrate 101. The semiconductor substrate 101 and the conductor region 103 are formed as a source region and a drain region of the memory transistor, respectively. The conductor region 103 is shown above the semiconductor layer 102 in the figure, however, it is understood that the conductor region 103 is a conductor region formed in a part of the surface area of the semiconductor layer 102.

Epitaxial growth processes for forming the semiconductor layer 102 are known. In the epitaxial growth process, a single crystal layer having a crystal orientation consistent with that of the single crystal substrate may be grown on the single crystal substrate. The high quality single crystal layer can reduce crystal defects, thereby reducing the performance degradation (e.g., large leakage current, low voltage breakdown) of the transistor due to the crystal defects. In this embodiment, the epitaxial growth process includes, for example: sputtering, thermal evaporation, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic Chemical Vapor Deposition (MOCVD), vapor Phase Epitaxy (VPE), organometallic vapor phase epitaxy (OMVPE), molecular Beam Epitaxy (MBE), chemical Beam Epitaxy (CBE), atomic Layer Epitaxy (ALE), and Pulsed Laser Deposition (PLD).

Ion implantation processes for forming the conductor region 103 are known. In the ion implantation process, high-energy ions are implanted into the semiconductor layer to form a conductor region. The conductivity type of the conductor region is related to the dopant type, and for silicon epitaxial layers, the P-type dopant used to form the P-type conductor region is, for example, boron (B) or indium (In), and the N-type dopant used to form the N-type conductor region is, for example, phosphorus (P), arsenic (As), or strontium (Sr). The doping profile of the conductor region is related to the ion energy of the ion implantation, and by controlling the ion energy, a predetermined depth can be reached, and even a buried layer can be formed.

Next, referring to fig. 8b, step 703 is performed to form at least one first trench 151 partially within the semiconductor layer 102.

In an embodiment, the forming at least one first trench 151 partially within the semiconductor layer 102 includes: a first trench 151 is formed to extend through the semiconductor layer 102 into the semiconductor substrate 101, or a first trench 151 is formed to extend into the semiconductor layer 102.

In some embodiments, as shown in fig. 8b, the first trench 151 extends downward from the surface of the conductor region 103, sequentially through the conductor region 103, the semiconductor layer 102, until reaching the first surface of the semiconductor substrate 101, or reaching a predetermined depth below the first surface of the semiconductor substrate 101.

In other embodiments, as shown in fig. 5, a first trench (not identified in fig. 5) extends downwardly from the surface of conductor region 103, through conductor region 103, and terminates within semiconductor layer 102.

The process for forming the first trench 151 includes forming a resist mask PR1 by photolithography and etching, etching through an opening of the resist mask PR1, and sequentially removing the exposed portions of the semiconductor layer 102 and the conductor region 103.

The etching process is, for example, an anisotropic dry etching process in which an etching gas selectively removes materials of the conductor region and the semiconductor layer with respect to the resist mask, and may be etched in a single direction to form a trench having a vertical profile. The trench may be controlled to a predetermined depth by controlling the etching time or by using the semiconductor substrate as a stop layer. Preferably, the dry etching process is, for example, reactive Ion Etching (RIE), wherein the etching is achieved by physical and chemical effects, with the advantages of both anisotropy and high etching rate. For silicon etching, a fluorine-based gas (e.g., SF 6) may be used as an etching gas in reactive ion etching to obtain good anisotropy. Preferably, the etching process may further form a hard mask instead of the resist mask PR1, and a deep trench of a greater depth may be formed using the corrosion resistance of the hard mask.

Next, referring to fig. 8c, step 704 is performed to form a gate stack located in the first trench 151, where the gate stack includes a gate dielectric layer 104 covering the bottom and sidewalls of the first trench 151 and a gate conductor 105 surrounded by the gate dielectric layer 104.

The gate dielectric layer 104 covers the bottom and sidewalls of the first trench 151 and the gate conductor 105 is located in the first trench 151. The gate dielectric layer 104 is sandwiched between the gate conductor 105 and the semiconductor layer 102. When a gate voltage is applied to the gate conductor 105, a portion of the semiconductor layer 102 adjacent to the first trench 151 may form a channel extending substantially vertically along sidewalls of the first trench 151.

In a specific embodiment, the gate stack fills the first trench.

The process for forming gate dielectric layer 104 may employ thermal oxidation. The temperature of the thermal oxidation is, for example, 950 to 1200 degrees celsius. The exposed surfaces of the semiconductor substrate 101, the semiconductor layer 102 and the conductor region 103 form silicon oxide during thermal oxidation. The thermal oxidation process forms a gate dielectric layer 104 at the bottom and sidewalls of the first trench 151. Further, although not shown in the drawings, silicon oxide is formed on the surface of the conductor region 103 outside the first trench 151, and is used as a part of an interlayer dielectric layer together with an additional second insulating layer in a subsequent process.

The process for forming the gate conductor 105 includes, for example, depositing a conductive material to fill the first trench 151 using a sputtering process or the like. The gate conductor 105 is composed of doped polysilicon or polysilicon, for example. The polysilicon material forming the gate conductor 105 may be deposited one or more times, and the multiple depositions may improve the filling characteristics of the polysilicon, avoiding defects such as holes in the gate conductor 105. The polysilicon not only fills the first trench 151 but also covers the surface of the conductor region 103. Next, a Chemical Mechanical Polishing (CMP) process is used to remove the portion of the polysilicon on the surface of the conductor region 103, thereby forming the gate conductor 105.

Next, referring to fig. 8d, step 705 is performed to form at least one second trench 152 extending into the semiconductor layer 102.

The second trench 152 extends downward from the surface of the conductor region 103, reaching a predetermined depth in the semiconductor layer 102 after penetrating the conductor region 103. The second grooves 152 are adjacent to the first grooves 151 and each extend in parallel in the vertical direction, but reach different depths. As shown, the second trench 152 reaches only a predetermined depth in the semiconductor layer 102 and does not penetrate the semiconductor layer 102.

The etching process for forming the second trenches 152 is substantially the same as the etching process for forming the first trenches 151, and will not be described in detail herein. By controlling the etching time, the etching depth of the etching process can be controlled.

Next, referring to fig. 8e and 8f, step 706 is performed to form a channel control region 106 located inside the second trench 152, the channel control region 106 being in contact with the semiconductor layer 102 to form a junction capacitance for storing charges.

In an embodiment, the forming the channel control region 106 inside the second trench 152 includes: a channel control region 106 is formed at a lower portion of the second trench 152.

The channel control region 106 is located inside the second trench 152, the channel control region 106 being adjacent to the gate conductor 105 and in direct contact with the semiconductor layer 102 to form a junction capacitance for storing charge.

In a specific embodiment, the channel control region fills the interior of the second trench.

The channel control region 106 may be processed by a doping process, or/and a deposition process, or/and an epitaxy process, or/and a self-assembly process, or/and a spin-coating process, or/and a self-assembly process, or/and a Roll-to-Roll process, or/and a hydrothermal process, or/and an imprinting process, or/and a rolling process, or/and a printing process, or/and an evaporation process.

The channel control region 106 is composed of, for example, a conductor, a semiconductor, or any stack of a conductor and a semiconductor. Preferably, the conductor comprises at least one selected from the group consisting of metal, alloy, ITO, doped silicon, doped polysilicon, metal nitride, and metal silicide. Preferably, the metal comprises at least one selected from Pt, pd, au, ni, ag, cu, al, mo, in, ti. For example, the channel control region 106 is composed of Pt. In the case where the channel control region 106 is comprised of metal, the process for forming the channel control region 106 includes, for example, depositing metal to fill the second trench 152 using a sputtering or the like process. In this embodiment, as shown in fig. 8e, the second trench 152 is completely filled with metal by using a deposition process, and further, as shown in fig. 8f, the metal is etched back to form the channel control region 106, and the channel control region 106 reaches a predetermined top position by controlling the etching time of the etching back. In an alternative embodiment, the second trench 152 is filled directly with metal portions using a deposition process, and the channel control region 106 reaches a predetermined top position by controlling the deposition time.

In this step, a Chemical Mechanical Polishing (CMP) process is also included to remove the portion of the metal that is outside of the second trench 152.

In an embodiment, a portion of the semiconductor layer 102 between the first trench 151 and the second trench 152 is formed as a channel region of the memory transistor.

Next, referring to fig. 8g, the method further includes: forming a first insulating layer 107 covering the channel control region 106 and located on top of the second trench 152; wherein the top surface of the channel control region 106 is lower than the bottom surface of the drain region (conductor region) 103, and the first insulating layer 107 isolates the channel control region 106 from the drain region 103.

Next, with continued reference to fig. 8g, a second insulating layer 110 is formed over the conductor region 103.

The first insulating layer 107 and the second insulating layer 110 together serve as an interlayer dielectric layer.

In this embodiment, the first insulating layer 107 is, for example, a capping layer formed using a deposition process, and after deposition, chemical Mechanical Polishing (CMP) is used to remove portions located outside the second trenches 152. The second insulating layer 110 is, for example, a capping layer formed using a deposition process, and after deposition, chemical Mechanical Polishing (CMP) is used to planarize the surface of the second insulating layer 110.

The materials of the first insulating layer 107 and the second insulating layer 110 include insulating materials.

In an alternative embodiment, the first insulating layer 107 and the second insulating layer 110 are insulating layers integrally formed using a deposition process, which are not only located at the upper portion of the second trench 152 but also cover the surface of the conductor region 103, and, after deposition, chemical Mechanical Polishing (CMP) is used to planarize the surface of the insulating layers.

Next, referring to fig. 8h, the method further includes: a drain electrode 121, a gate electrode 123, and a channel electrode 124 are formed on the second insulating layer 110, and a source electrode 122 is formed on the second surface of the semiconductor substrate 101.

This step includes forming a through hole (through hole) in the second insulating layer 110, and filling the through hole with a conductive material, thereby forming a first conductive path 111, a second conductive path 113, and a third conductive path 114 reaching the conductor region 103, the gate conductor 105, and the channel control region 106, respectively.

Further, a conductive layer is formed on the surface of the second insulating layer 110, and patterned to form a drain electrode 121, a gate electrode 123, and a channel electrode 124. The drain electrode 121 is connected to the conductor region 103 via a first conductive via 111 penetrating the second insulating layer 110. The gate 123 is connected to the gate conductor 105 via a second conductive via 113 through the second insulating layer 110. The channel electrode 124 is connected to the channel control region 106 via a third conductive path 114 penetrating the second insulating layer 110 and the first insulating layer 107.

Further, a conductive layer is formed on the second surface of the semiconductor substrate 101 to form the source electrode 122.

In some embodiments, as shown in fig. 8h, the channel control region 106 comprises one channel control region at least partially surrounding the gate stack to obtain a predetermined junction area.

In other embodiments, as shown in fig. 5, the channel control region 106 includes a plurality of channel control regions spaced around the gate stack and respectively in contact with the semiconductor layer 102 to form a plurality of junction capacitances.

The embodiment of the disclosure also provides a memory array, and fig. 9 is a circuit diagram of the two-dimensional memory array provided by the embodiment of the disclosure.

As shown in fig. 9, the memory array includes a plurality of memory transistors 100 described in any of the above embodiments, and the plurality of memory transistors 100 are arranged in an array along a row and column direction;

a plurality of word lines WL to which gate conductors of the memory transistors 100 located in the same row of the plurality of memory transistors 100 are connected;

a plurality of first bit lines BL1, the channel control regions of the memory transistors 100 located in the same row or the same column of the plurality of memory transistors 100 are connected to the same first bit line BL1;

A plurality of second bit lines BL2, drain regions of the memory transistors 100 located in the same column of the plurality of memory transistors 100 being connected to the same second bit line BL2;

wherein the source regions of the plurality of memory transistors 100 are connected to a fixed potential, the plurality of first bit lines BL1 are used to apply a control region voltage in a write operation, the plurality of second bit lines BL2 are used to apply a drain voltage in a write operation and a read operation, and to detect a drain current in a read operation, the drain current being used to characterize the memory state of the memory transistors 100.

In the present embodiment, the memory transistor 100 in the memory array 20 is, for example, an N-channel transistor. The source regions of the memory transistors 100 in the memory array are all grounded. The gate conductors of the memory transistors 100 located in the same row are connected to the same word line WL, the channel electrodes of the memory transistors 100 located in the same row are connected to the same bit line BL1, and the drain regions of the memory transistors 100 located in the same column are connected to the same bit line BL2.

In the memory array 20, a word line WL is used for a data line for row selection, a bit line BL1 is a data line for row writing, and a bit line BL2 is a data line for column reading and drain biasing.

In writing the selected memory transistor 100, the word line WL of the corresponding row of memory transistors is selected to apply the gate voltage Vgs, and the second bit line BL2 of the corresponding column of memory transistors is selected to apply the drain voltage Vds, so that the selected memory transistor 100 is turned on. Further, applying a control region voltage on the first bit line BL1 of the selected memory transistor 100 may change the charge storage state of the junction capacitance of the memory transistor 100.

At this time, the channel electrodes of the memory transistors of the corresponding row each receive the control region voltage, and there may be a write disturbance. By selecting the appropriate bias voltage (i.e., gate voltage) and control region voltage, the write disturbance of the corresponding row of memory transistors can be minimized.

In one embodiment, a plurality of the memory transistors 100 share a semiconductor substrate to form a common source structure. The adoption of the common source structure can reduce the wiring quantity and the wiring area of the source electrode, further reduce the whole size of the memory array, and further improve the storage density of the memory.

Fig. 10 is a circuit diagram of a two-dimensional memory array according to another embodiment of the present disclosure, and fig. 11 is a circuit diagram of a three-dimensional stacked memory array formed by the memory array of fig. 10.

The memory array shown in fig. 10 is substantially the same as the memory array shown in fig. 9, but differs from the memory array shown in fig. 9 only in the manner of connection of the first bit line BL1.

Referring to fig. 10, in the memory array 30, a plurality of memory transistors 100 are arranged in an array in rows and columns. In the present embodiment, the memory transistor 100 in the memory array is, for example, an N-channel transistor. The source regions of the memory transistors 100 in the memory array are all grounded. The gate conductors of the memory transistors 100 located in the same row are connected to the same word line WL. The channel electrodes of the memory transistors 100 located in the same column are connected to the same first bit line BL1. The drain regions of the memory transistors 100 located in the same column are connected to the same second bit line BL2. The word line WL is a data line for row selection, the first bit line BL1 is a data line for column writing, and the second bit line BL2 is a data line for column reading and drain biasing.

Referring to fig. 11, in the memory array 40, a plurality of two-dimensional memory arrays as shown in fig. 10 are stacked in a three-dimensional structure along a direction x shown in fig. 11. The row and column directions of each two-dimensional memory array are the direction y and direction z shown in fig. 11, respectively. The plurality of two-dimensional memory arrays includes word lines independent of each other, and first and second bit lines common to each other. For example, a first column of memory transistors in a plurality of two-dimensional memory arrays are connected to the same first bit line BL1 and the same second bit line BL2. The word line WL is a data line for row selection, the first bit line BL1 is a data line for column writing, and the second bit line BL2 is a data line for column reading and drain biasing.

In writing to the selected memory transistor 100, a row or column in the three-dimensional memory array may be selected by floating the word line WL of the selected memory transistor or applying the gate voltage Vgs, and the second bit line BL2 of the corresponding column of memory transistors is selected to apply the drain voltage Vds such that the selected memory transistor 100 is turned on. Further, applying a control region voltage on the first bit line BL1 of the selected memory transistor 100 may change the charge storage state of the junction capacitance of the memory transistor 100.

At this time, the channel electrodes of the corresponding one column of memory transistors each receive the control region voltage, and in the corresponding one column of memory transistors, only the gate voltage Vgs of the selected memory transistor 100 is higher than the threshold voltage, so that the write disturbance of the corresponding one column of memory transistors can be minimized. Therefore, the memory array shown in fig. 10 can effectively reduce write disturbance as compared with the memory array shown in fig. 9.

The embodiment of the disclosure also provides a data operation method of the memory array, and the operation method of the memory array is applied to the memory array in any one of the embodiments. Referring to fig. 12, as shown in fig. 12, the data operation method of the storage array includes the following steps:

Step 1201: in a write operation, applying a gate voltage via a selected one of the plurality of word lines and a drain voltage via a selected one of the plurality of second bit lines to place a selected memory transistor in an on state, and applying a control region voltage to the selected memory transistor via a selected one of the plurality of first bit lines to change a memory state of the selected memory transistor;

step 1202: in a read operation, a gate voltage is applied via a selected one of the plurality of word lines and a drain voltage is applied via a selected one of the plurality of second bit lines to place a selected memory transistor in an on state, and a drain current of the selected memory transistor is detected via a selected one of the plurality of second bit lines to obtain a memory state of the selected memory transistor.

The data operation method of the memory array provided by the embodiment of the disclosure is described in further detail below with reference to specific embodiments.

Fig. 13 is a schematic diagram showing a write operation to a memory cell in the memory array shown in fig. 9 and 10.

As shown in fig. 13, step 1201 is performed.

The memory device includes a word line driving module 21, a bit line driving module 22, and a memory array 20. In this embodiment, one memory transistor 100 in the memory array 20 shown in fig. 9 is taken as an example for the detailed description. The word line driving module 21 is connected to the gate of the memory transistor 100 via a word line WL, and the bit line driving module 22 is connected to the channel electrode of the memory transistor 100 via a first bit line BL1 and to the drain of the memory transistor 100 via a second bit line BL 2.

In a write operation, the gate voltage Vgs is provided via the word line WL, the control region voltage Vc is provided via the first bit line BL1, and the drain voltage Vds is provided via the second bit line BL 2. The source of memory transistor 100 is grounded. At this time, the memory transistors 100 in the memory array are in an on state, and the unselected memory transistors in the memory array are in an off state. Preferably, in the write operation, the gate voltage Vgs of the memory transistor 100 is 0.5 to 10V and the drain voltage Vds is 0.01 to 10V.

Further, the write operation includes, for example, data erase and data program. In data erasure, the control region voltage Vc of the memory transistor 100 is, for example, 1.5V, and the junction capacitance of the memory transistor 100 is discharged to discharge electric charges. In data programming, the control region voltage Vc of the memory transistor 100 is, for example, -1.5V, so that the voltage difference of the gate voltage Vgs with respect to the control region voltage Vc exceeds a predetermined value, and the junction capacitance of the memory transistor 10 is charged to store electric charges. The write operation may change the memory state of the memory transistor 100, for example, the erase state of the memory transistor 100 is a high resistance state for representing a digital value of 0, and the write state is a low resistance state for representing a digital value of 1.

Fig. 14 is a schematic diagram showing a read operation of memory cells in the memory array of fig. 9 and 10.

As shown in fig. 14, step 1202 is performed. In this embodiment, a memory array shown in fig. 9 is taken as an example for a detailed description.

In a read operation, the gate voltage Vgs is provided via the word line WL and the drain voltage Vds is provided via the second bit line BL 2. The source of memory transistor 100 is grounded. The channel electrode of the memory transistor 100 is in a floating state due to the first bit line BL1 being turned off. At this time, the memory transistors 100 in the memory array are in an on state, and the unselected memory transistors in the memory array are in an off state. Preferably, in the read operation, the gate voltage Vgs of the memory transistor 100 is 0.5 to 1.2V and the drain voltage Vds is 0.05 to 2V.

In one embodiment, in a read operation, the plurality of first bit lines are disconnected or connected to a fixed potential.

Further, the read operation includes detecting the drain current Ids of the memory transistor 100. In a write operation of the memory transistor 100, the memory state of the memory transistor 100 is related to the resistance state. Even with the same bias conditions, i.e., the same gate voltage, drain voltage, and source voltage, the drain current levels of the memory transistors in different memory states are different.

Therefore, the drain current Ids is compared with the current reference Iref, and the memory state of the memory transistor 100 can be determined based on the magnitude of the drain current Ids. For example, when the drain current of the memory transistor 100 is greater than the current reference Iref, the digital value stored in the memory transistor 100 is determined to be 1, and when the drain current of the memory transistor 100 is less than or equal to the current reference Iref, the digital value stored in the memory transistor 100 is determined to be 0.

In the embodiment of the disclosure, in the read operation, the drain current of the memory transistor is detected by adopting the current detection method to acquire the memory state of the memory transistor, so that the power consumption of the memory array in the read operation can be remarkably reduced.

In the embodiments described above, the connection mode and the data operation method of the memory array are described using the N-channel transistor as an example. In an alternative embodiment, the memory transistor 100 in the memory array is, for example, a P-channel transistor, the source of the memory transistor 100 being connected to the supply voltage VDD. It will be appreciated that the source region of the memory transistor 100 is not limited to the ground connection shown in fig. 9, and may be connected to a fixed high or low level depending on the channel type of the memory transistor 100.

As shown in fig. 15, after the write operation of the memory transistor 100, the memory transistor 100 is read a plurality of times at different times, and the drain current Ids of the memory transistor 100 changes only slightly for a certain period of time. From the trend of the drain current Ids, it can be judged that the holding time of the memory transistor 100 is longer than 20 minutes. The switching ratio of the two memory states of the memory transistor 100 is also maintained at approximately the same value, i.e., the drain current Ids in the on state/the drain current Ids in the off state.

In this embodiment, the holding time of the memory cell may reach 20 minutes or more. The memory cells of the memory array can reduce the refresh times, and therefore, the power consumption of the memory array in the data refresh operation can be significantly reduced.

The memory transistor 100 exhibits both erasable and writeable capabilities of the memory design after a write operation, with a drain current change at the same bias condition. The write operation of the memory transistor 100 can also eliminate the charge erasure accumulation effect.

According to the memory transistor of the embodiment of the present invention, the memory mechanism of the memory transistor 100 is attributable to the junction capacitance effect induced by the additional electrode (additional electrodes, AE), wherein the channel electrode forms a junction capacitance between the additional electrode and the channel, and the data storage is realized by using the mechanism of storing charges by the junction capacitance.

In the write operation, when a forward bias voltage is applied to the channel electrode of the memory transistor 100, charges are injected from the channel region into the junction capacitance and stored in the junction capacitance, thereby realizing data programming; when a reverse bias voltage is applied to the channel electrode of the memory transistor 100, charge is discharged from the junction capacitance back to the channel region, thereby achieving data erasure.

In a read operation, the new charge storage mechanism described above produces additional dimensional control of the channel carriers of the memory transistor 100, so that memory transistors in different memory states produce different magnitudes of drain current under the same bias conditions. In a conventional memory array, a memory cell has a "1T1C" cell structure including at least one transistor and one storage capacitor for storing one bit of information. In a write operation, a transistor is used to control charge injection and release of a storage capacitor, and in a read operation, the transistor connects the capacitor to a bit line, and reads the storage state of the storage capacitor according to the bit line voltage.

The memory array according to the embodiment of the present disclosure is different from a conventional memory array in that: the memory cell has a "1T" cell structure, and charges are stored directly by using the junction capacitance of the channel region of the memory transistor. The memory cells of the memory array do not need to contain separate memory capacitors, the occupied wafer area of the memory cells is obviously reduced, and therefore, the memory density of the memory device can be obviously improved.

It should be appreciated that the disclosed structures may be implemented with existing process lines, or may be implemented with adjustments based on existing process steps, and that the channel control region, control region materials may be semiconductor materials, conductor materials, or a combination of materials. The actual manufacturing process may vary depending on factors such as manufacturer, device size, and process technology.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory transistor, comprising:

2. The memory transistor of claim 1, wherein,

The at least one first trench partially within the semiconductor layer, comprising:

the first trench extends into the semiconductor layer.

3. The memory transistor of claim 1, wherein,

the channel control region is located inside the second trench, and includes: the channel control region is located at a lower portion of the second trench.

4. The memory transistor of claim 1, wherein the memory transistor further comprises:

a conductor region in the semiconductor layer; wherein,

5. The memory transistor of claim 4 wherein,

the at least one first trench partially within the semiconductor layer, and at least one second trench extending into the semiconductor layer, comprising:

6. The memory transistor of claim 1, wherein,

the channel control region includes a channel control region at least partially surrounding the gate stack to obtain a predetermined junction area.

7. The memory transistor of claim 1, wherein,

the channel control region includes a plurality of channel control regions spaced around the gate stack and respectively contacting the semiconductor layer to form a plurality of junction capacitances.

8. A method of manufacturing a memory transistor, comprising:

forming at least one first trench partially within the semiconductor layer;

Forming at least one second trench extending into the semiconductor layer;

9. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

the forming at least one first trench partially within the semiconductor layer includes:

a first trench is formed extending into the semiconductor layer.

10. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

the forming a channel control region located inside the second trench includes: a channel control region is formed at a lower portion of the second trench.

11. The method of claim 8, wherein the method further comprises:

forming a conductor region in the semiconductor layer; wherein,

12. The method of claim 11, wherein the step of determining the position of the probe is performed,

the forming at least one first trench partially within the semiconductor layer, forming at least one second trench extending into the semiconductor layer, comprising:

13. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

14. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

15. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

the channel control region is processed through doping process, deposition process, epitaxy process, self-assembly process, spin-coating process, self-assembly process, roll-to-Roll process, hydrothermal process, embossing process, rolling process, printing process, and vapor plating process.

16. A memory array comprising a plurality of memory transistors according to any one of claims 1 to 7, the plurality of memory transistors being arranged in an array in a row and column direction;

17. The memory array of claim 16, wherein the memory array is configured to store,

a plurality of the memory transistors share a semiconductor substrate to form a common source structure.

18. A method of data manipulation of a storage array as claimed in any one of claims 16 to 17, the method comprising:

19. The method of claim 18, wherein the step of providing the first information comprises,

in a read operation, the plurality of first bit lines are disconnected or connected to a fixed potential.

20. The method of claim 18, wherein the step of providing the first information comprises,

the memory transistor includes a plurality of channel control regions to which respective control region voltages are applied in a write operation to write a digital value of a plurality of bits, respectively, and a drain current commonly modulated by the plurality of channel control regions is detected in a read operation to read the digital value of the plurality of bits.