CN117729780A

CN117729780A - Memory structure, memory, differential amplifying circuit, chip and electronic device

Info

Publication number: CN117729780A
Application number: CN202311382000.8A
Authority: CN
Inventors: 戴明志; 薛志彪; 许智亮; 吴嘉锋; 徐吉; 吕明明; 张笑阳
Original assignee: Ningbo Institute of Material Technology and Engineering of CAS
Current assignee: Ningbo Institute of Material Technology and Engineering of CAS
Priority date: 2023-10-23
Filing date: 2023-10-23
Publication date: 2024-03-19

Abstract

The invention discloses a storage structure, a storage, a differential amplifying circuit, a chip and electronic equipment, and relates to the field of electronic circuits. The storage structure includes: the first transistor is provided with a first source electrode, a first drain electrode, a first grid electrode and a first channel electrode, and a first junction capacitor is formed; the second transistor is provided with a second source electrode, a second drain electrode, a second grid electrode and a second channel electrode, and a second junction capacitor is formed; the first drain electrode is connected with the first bit line; the second drain electrode is connected with the second bit line; the first source electrode and the second source electrode are commonly connected with an output end, a grounding end or a non-grounding end; the first gate and the second gate may be connected in line or with the word line, respectively; the first channel electrode and the second channel electrode may be connected by a common word line or by word lines, respectively, and the output currents of the first transistor and the second transistor may be different. The invention realizes differential storage by regulating and controlling different output currents, can counteract common mode noise anti-interference, enlarges window size, and can realize integration.

Description

Memory structure, memory, differential amplifying circuit, chip and electronic device

Technical Field

The present invention relates to the field of electronic circuits, and in particular, to a memory structure, a memory, a differential amplifying circuit, a chip, and an electronic device.

Background

With the development of science, integrated circuits are widely used in various electronic devices, transistors are basic components of the integrated circuits, the transistors can be used as switches for carrying out signal switching, voltage switching or realizing unidirectional conduction and signal storage of the circuits, single transistors are easy to be influenced by noise and weak in anti-interference capability, and single transistors have the problem of sensitivity to process difference, namely the performance of the devices is easy to be influenced by tiny changes in the manufacturing process, when a plurality of transistors are arranged on a chip, each transistor has different performance, the problem of window overlapping exists for reading currents of different transistors, and therefore the tolerance of the single transistor to variability is limited, namely the storage state of the transistors is difficult to be effectively identified under the condition of large signal change.

Disclosure of Invention

In order to solve the technical problem of large area of a differential storage structure in the prior art, one aspect of the invention discloses a storage structure, which comprises:

a first transistor including a first source, a first drain, a first gate, and a first channel electrode; the first channel electrode is in electrical contact with the channel region exposed by the first grid electrode, and the first channel electrode and the channel region form a first junction capacitor;

A second transistor including a second source, a second drain, a second gate, and a second channel electrode; the second channel electrode is in electrical contact with the channel region exposed by the second gate, and the second channel electrode and the channel region form a second junction capacitance;

the first drain electrode is connected with a first bit line; the second drain electrode is connected with a second bit line; the first source electrode and the second source electrode are commonly connected with an output end, a grounding end or a non-grounding end;

a target word line control terminal including at least one of a first word line and a second word line; the target word line control end is used for conducting the first transistor and the second transistor; the first grid electrode and the second grid electrode are connected with the first word line in a collinear manner, or the first grid electrode and the second grid electrode are respectively connected with the first word line; the first channel electrode and the second channel electrode are connected with the second word line in a collinear manner, or the first channel electrode and the second channel electrode are respectively connected with the second word line; the target word line control terminal is used for realizing that the output currents of the first transistor and the second transistor are different.

Optionally, the target word line control terminal includes the first word line, and when the first junction capacitance is different from the second junction capacitance, the first gate and the second gate are connected in line with the first word line, or the first gate and the second gate are respectively connected with the first word line; the input voltage of the first channel electrode is the same as or different from the input voltage of the second channel electrode;

the first drain electrode is connected with a first bit line; the second drain electrode is connected with a second bit line; the first source electrode and the second source electrode are commonly connected with an output end, a grounding end or a non-grounding end.

Optionally, the target word line control terminal includes the first word line, and when the first junction capacitance is the same as the second junction capacitance, the first gate and the second gate are connected in line with the first word line, or the first gate and the second gate are respectively connected with the first word line; the input voltage of the first channel electrode is different from the input voltage of the second channel electrode;

Optionally, the target word line control terminal includes the second word line, and when the first junction capacitance is different from the second junction capacitance, the first channel electrode and the second channel electrode are connected in line with the second word line, or the first channel electrode and the second channel electrode are respectively connected with the second word line; the input voltage of the first grid electrode is the same as or different from the input voltage of the second grid electrode;

Optionally, the target word line control terminal includes the second word line, and when the first junction capacitance is the same as the second junction capacitance, the first channel electrode and the second channel electrode are connected in line with the second word line, or the first channel electrode and the second channel electrode are respectively connected with the second word line; the input voltage of the first grid electrode is different from the input voltage of the second grid electrode;

Optionally, the target word line control terminal includes the first word line and the second word line, and when the first junction capacitance is different from the second junction capacitance, the first gate and the second gate are connected to the first word line in a collinear manner, or the first gate and the second gate are respectively connected to the first word line;

and the first channel electrode and the second channel electrode are connected with the second word line in a collinear manner, or the first channel electrode and the second channel electrode are respectively connected with the second word line; the input voltage of the first word line is the same as or different from the input voltage of the second word line;

Optionally, the target word line control terminal includes the first word line and the second word line, and when the first junction capacitance is the same as the second junction capacitance, the first gate and the second gate are connected to the first word line in a collinear manner, or the first gate and the second gate are respectively connected to the first word line;

And the first channel electrode and the second channel electrode are connected with the second word line in a collinear manner, or the first channel electrode and the second channel electrode are respectively connected with the second word line; an input voltage of the first word line is different from an input voltage of the second word line;

Optionally, the first gate includes one or more separate first sub-gates, and the second gate includes one or more separate second sub-gates;

the first channel electrode comprises one or more separate first sub-channel electrodes; the second channel electrode includes one or more separate second sub-channel electrodes.

Optionally, one or more of ferroelectric material, magneto-electric material, phase change material, quantum effect material, resistive effect material, memory effect material, semiconductor material, conductor material, superconducting material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, silicide is used as the insulating layer additive layer, insulating layer material, insulating layer additive material, semiconductor layer material, semiconductor channel material, or channel electrode material.

Optionally, the channel electrode is processed through doping process, or/and deposition process, or/and epitaxy process, or/and self-assembly process, or/and spin-coating process, or/and self-assembly process, or/and Roll-to-Roll process, or/and hydrothermal process, or/and imprinting process, or/and rolling process, or/and printing process, or/and evaporation process.

In another aspect, a memory is provided, comprising a memory structure as described above.

In another aspect, there is provided a memory array comprising:

a plurality of memories as described above, the plurality of memories being arranged in an array in a row and column direction;

and a plurality of word lines, the gate conductors of the memories in the same row being connected to the same word line.

A plurality of first bit lines to which channel control regions of memories located in the same column or the same row of the plurality of memories are connected; and the drain regions of the memories in the same column are connected to the same second bit line.

Wherein the source regions of the plurality of memories are connected to a fixed potential, the plurality of first bit lines are for applying a control region voltage in a write operation, the plurality of second bit lines are for applying a drain voltage in a write operation and a read operation, and for detecting a drain current in a read operation, the drain current being used to characterize a storage state of the memories.

In another aspect, a differential amplifying circuit is provided, comprising a memory structure as described above.

In another aspect, a chip is provided, characterized by comprising a memory structure as described above.

In another aspect, a circuit is provided that includes a memory structure as described above.

In another aspect, an electronic device is provided, characterized by comprising a circuit as described above.

By adopting the technical scheme, the invention has the following beneficial effects:

compared with the storage of a single transistor, the storage structure provided by the invention has the advantages that the single transistor is easy to be influenced by noise and weak in anti-interference capability, and the single transistor has the problem of process difference sensitivity, the performance is easy to be influenced by small changes in the manufacturing process, and the storage structure formed by the double transistors can reduce the sensitivity of a device to the process difference, namely the influence of the small changes in the manufacturing process on the performance of the device. The current reading window of the single transistor is smaller in size, so that the latitude of the signal variability is limited, namely, under the condition of large noise signal variation, the problem of 0 or 1 stored in a single transistor is difficult to effectively identify.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1a is a schematic plan view of a first transistor in a memory structure according to an embodiment of the present invention;

FIG. 1b is a schematic cross-sectional view of a first transistor in a memory structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an alternative memory structure according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an alternative memory structure according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an alternative memory structure according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an alternative embodiment of a differential amplifier circuit according to the present invention;

FIG. 6 is a schematic diagram of a transistor with multiple inputs according to an embodiment of the present invention;

FIGS. 7 a-7 c are schematic diagrams of differential currents before differential memory test conditioning according to embodiments of the present invention;

FIGS. 8 a-8 c are schematic diagrams of differential currents after differential memory test regulation according to embodiments of the present invention;

FIG. 9 is a diagram illustrating a bionic integration test result of a transistor with another memory structure according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a memory array according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of an alternative implementation of a memory array according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of another storage array according to an embodiment of the present invention;

FIGS. 13-14 are diagrams illustrating the results of another random access memory test according to the present invention;

fig. 15 is a schematic diagram of a typical process for manufacturing a transistor with a channel electrode according to an embodiment of the present invention.

Fig. 16 is a schematic view showing a planar structure of a transistor having a channel electrode according to the present invention.

Fig. 17 is a schematic diagram of a three-dimensional structure of a transistor with a channel electrode according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

For the purposes of the following detailed description, it is to be understood that the invention may assume various alternative variations and step sequences, except where expressly specified to the contrary. Furthermore, except in any operating examples, or where otherwise indicated, all numbers expressing, for example, quantities of ingredients used in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. When a range of values is disclosed herein, the range is considered to be continuous and includes both the minimum and maximum values for the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values of the range is included. Further, when multiple range description features or characteristics are provided, the ranges may be combined. In other words, unless otherwise indicated, all ranges disclosed herein are to be understood to include any and all subranges subsumed therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between the minimum value of 1 and the maximum value of 10. Exemplary subranges from 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, and the like

The invention discloses a storage structure of a digital circuit, wherein transistors used in the storage of a transistor control circuit are field effect transistors, and the field effect transistors mainly have two types: junction field effect transistors (FET-JFETs) and metal-oxide semiconductor field effect transistors (MOSFET for short).

The transistor used in the embodiment of the invention is a MOSFET transistor, but is different from a conventional MOSFET transistor, the embodiment of the invention leads out a channel electrode in a channel region, namely comprises a source electrode, a drain electrode, a grid electrode and a channel electrode, and the channel electrode and the channel region form a junction capacitance, so that the transistor has the capacity of storing charges. The transistors used in the embodiments of the present invention and how the differential storage can be achieved using two of the transistors will be described in detail below.

In one aspect, the invention discloses a storage structure comprising:

a first transistor including a first source, a first drain, a first gate, and a first channel electrode; the first channel electrode is in electrical contact with the channel region where the first gate is exposed, and the first channel electrode and the channel region form a first junction capacitance.

Specifically, referring to the planar structure of the first transistor shown in fig. 1, for the first transistor, ions are doped on the substrate 1 to form the first source region 3 and the first drain region 4, where the substrate 1 may be selected from a semiconductor substrate or an insulating substrate, and if the substrate is a semiconductor substrate, the semiconductor material may be a semiconductor material such as silicon, a compound of silicon, germanium, a compound of germanium, or gallium arsenide, and the semiconductor material may be a photoelectric material, such as a carbon-based material, or a bionic material, such as an oxide material, or a semiconductor material such as a polymer material (with a conductive agent). In the case of an insulating substrate, the insulating substrate may be an insulating material such as ITO glass, PDMS, or a polymer material.

In the embodiment of the present invention, a semiconductor substrate is selected as the substrate 1, an insulating layer 5 is covered on the surface of the substrate 1, the material may be oxide such as silicon dioxide or a high-K material, etc., in one possible embodiment, the material of the insulating layer 5 is selected from silicon dioxide insulating layer, the insulating layer 5 is etched to form a portion corresponding to the first source region 3 and the first drain region 4, a first source electrode 31 is disposed on the surface of the first source region 3 facing away from the substrate 1, and a first drain electrode 41 is disposed on the surface of the first drain region 4 facing away from the substrate 1. The insulating layer 5 between the first source electrode 31 and the first drain electrode 41 draws out the electrode as the first gate electrode 51, and the first gate electrode 51 is electrically insulated from the first source electrode 31 and the first drain electrode 41.

The semiconductor substrate between the first source region 3 and the first drain region 4 is provided with a channel region 2, which channel region 2 comprises a plurality of sides, such as shown with reference to fig. 1b, the channel region 12 of the first transistor being rectangular in cross-section in a direction perpendicular to the direction of extension (extending from the first source region 3 to the first drain region 4), the channel region 2 comprising opposite first and second sides 21, 22, opposite third and fourth sides 23, 24.

In the embodiment of the present invention, the material of the channel region 2 in the first transistor may be any one or more of an electrical or photoelectric material, such as a carbon-based material, a novel carbon material, an oxide combination, a two-dimensional material (such as a two-dimensional transition metal sulfide, etc.), a one-dimensional material (such as an oxide nanowire, etc.), a 0-dimensional material (such as a carbon quantum dot, etc.), a perovskite, graphene, a carbon nanotube, a polymer material, a mono-oxide, or a binary oxide or a ternary oxide, a quaternary oxide or a oxide with more than four elements (such as Indium Gallium Zinc Oxide (IGZO), indium Strontium Zinc Oxide (ISZO), indium Strontium Oxide (ISO), indium Zinc Oxide (IZO), etc.), and a semiconductor material.

The first gate electrode 51 surrounds a portion of the channel region 2, and an insulating layer 5 is provided between regions of the first gate electrode 51 opposite to the channel region 2, and the first gate electrode 51 exposes at least a portion or all of one side surface of the channel region 2 for providing the first channel electrode 6. For example, in one embodiment, referring to fig. 1b, the first gate 51 surrounds the first side 21 and the fourth side 24 of the channel region 2, exposing the second side 22 and the third side 23 of the channel region 2, and the first channel electrode 6 is in electrical contact with the third side 23 of the channel region 2, i.e. the first channel electrode 6 and the third side 23 have overlapping portions in the extending direction of the channel region 2 (extending from the first source region 3 to the first drain region 4). And in one possible embodiment, the first channel electrode 6 is insulated from the first gate 51. That is, the first channel electrode 6 is isolated from the first gate electrode 51 in a physical structure, without direct contact, and isolated from each other electrically, without electrical connection.

For a specific arrangement of the first channel electrode 6, when the first channel electrode 6 is located in the substrate 1, a recess may be formed in the substrate 1, in which recess the first channel electrode 6 is formed. The first channel electrode 6 may also be formed directly in the substrate 1 by ion implantation of the substrate 1, the thickness of the first channel electrode 6 not exceeding the thickness of the channel region 2.

In the embodiment of the present invention, the material of the first channel electrode 6 may be any one or more of a novel carbon material, an oxide combination, a two-dimensional material (such as a two-dimensional transition metal sulfide, etc.), an oxide nanowire, a perovskite, graphene, a carbon nanotube, an Indium Gallium Zinc Oxide (IGZO), an Indium Strontium Zinc Oxide (ISZO), an Indium Strontium Oxide (ISO), an Indium Zinc Oxide (IZO), and other semiconductor materials. Specifically, the material of the first channel electrode 6 may be any one or more of a single element oxide, a binary oxide, a ternary oxide, a quaternary or higher oxide, a polymer material, an electrical or photoelectric material, such as a carbon-based material, a novel carbon material, an oxide combination, a two-dimensional material (such as a two-dimensional transition metal sulfide, etc.), a one-dimensional material (such as an oxide nanowire, etc.), a 0-dimensional material (such as a carbon quantum dot, etc.), perovskite, graphene, a carbon nanotube, indium Gallium Zinc Oxide (IGZO), indium Strontium Zinc Oxide (ISZO), indium Strontium Oxide (ISO), indium Zinc Oxide (IZO), a metal material, etc. semiconductor material, and conductor material.

The first channel electrode 6 forms a first junction capacitance with the channel region 2 for storing charge. The first gate electrode 51 and the first channel electrode 6 serve as input control electrodes in a differential memory structure.

Further, the differential memory structure disclosed by the invention further comprises a second transistor, wherein the second transistor comprises a second source electrode, a second drain electrode, a second gate electrode and a second channel electrode; the second channel electrode is in electrical contact with the channel region where the second gate is exposed, and the second channel electrode and the channel region form a second junction capacitance.

Specifically, for the second transistor, ions are doped on the substrate to form the second source region and the second drain region, the selected substrate can be a semiconductor substrate or an insulating substrate, and the substrate material can be selected by referring to the substrate material of the first transistor. And a second source electrode is arranged on the surface, facing away from the substrate, of the second source region, and a second drain electrode is arranged on the surface, facing away from the substrate, of the second drain region, and the second gate electrode is electrically insulated from the second source electrode and the second drain electrode.

In the embodiment of the invention, the substrate is a semiconductor substrate, the surface of the substrate is covered with an insulating layer, the material can be oxide such as silicon dioxide or high-K material, and the like, in one possible embodiment, the material of the insulating layer is a silicon dioxide insulating layer, a second source region and a second drain region corresponding part are etched on the insulating layer, a second source electrode is arranged on the surface of the second source region, which is away from the substrate, and a second drain electrode is arranged on the surface of the second drain region, which is away from the substrate. An insulating layer extraction electrode between the second source electrode and the second drain electrode serves as a second gate electrode, and the second gate electrode is electrically insulated from the second source electrode and the second drain electrode.

The semiconductor substrate between the second source region and the second drain region is provided with a channel region of the second transistor, which channel region comprises a plurality of sides, such as in one embodiment, the channel region of the second transistor having a rectangular cross section perpendicular to the extension direction, the channel region comprising opposite first and second sides, opposite third and fourth sides. In the embodiment of the present invention, the channel region of the second transistor may be an electrical or photoelectric material, and specific material selection may be described with reference to the channel region material of the first transistor.

The second grid surrounds part of the channel region, an insulating layer is arranged between the second grid and the region opposite to the channel region, and the second grid exposes part or all of at least one side face of the channel region and is used for arranging a second channel electrode. For example, in one embodiment, the second gate surrounds the first side, the second side, and the fourth side of the channel region, exposing the third side of the channel region, and the second channel electrode is in electrical contact with the third side of the channel region, i.e., the second channel electrode has an overlapping portion with the third side in the extending direction of the channel region. And in one possible embodiment, the second channel electrode is insulated from the second gate electrode. The second channel electrode and the second grid electrode are isolated in physical structure, are not in direct contact, are isolated in electrical independent mode, and are not in electrical connection.

For a specific arrangement mode of the second channel electrode, when the second channel electrode is located in the substrate, a groove may be formed in the substrate, and the second channel electrode may be formed in the groove. The second channel electrode may also be formed directly in the substrate by ion implantation of the substrate, the thickness of the second channel electrode not exceeding the thickness of the channel region.

In the embodiment of the present invention, the material of the second channel electrode may be any one or more of a novel carbon material, an oxide combination, a two-dimensional material (such as a two-dimensional transition metal sulfide, etc.), an oxide nanowire, a perovskite, graphene, a carbon nanotube, an Indium Gallium Zinc Oxide (IGZO), an Indium Strontium Zinc Oxide (ISZO), an Indium Strontium Oxide (ISO), an Indium Zinc Oxide (IZO), etc., and the selection of the specific material of the second channel electrode may be described with reference to the material of the first channel electrode. The structure of the first transistor and the structure of the second transistor may be as shown with reference to fig. 1 and 1 b. Since the structure of the first transistor is identical to that of the second transistor, the structure of the second transistor can refer to the planar structure of the first transistor shown in fig. 1 and the cross-sectional view shown in fig. 1b, and will not be described herein.

Likewise, the second channel electrode and the channel region form a second junction capacitance for storing charge; the second gate and the second channel electrode also serve as input control electrodes in a differential memory structure.

Further, in the embodiment of the present invention, the first drain is connected to the first bit line; the second drain electrode is connected with the second bit line; the first source electrode and the second source electrode are commonly connected with the output end, the grounding end or the non-grounding end. In one possible implementation, the output signal of the first bit line is opposite to the output signal of the second bit line. In one embodiment, the first bit line is BitLine (BL) and the second bit line is BitLineBIn another embodiment, the first bit line is BitLineB +.>The second bit line is a BitLine (BL) for reading or writing the saved states of the first transistor and the second transistor, and the inverted first bit line and the second bit line contribute to improvement of noise margin.

In practical applications, in one possible implementation, when the first transistor and the second transistor are P-type transistors, the voltage applied to the first drain and the voltage applied to the second drain are zero; in another possible embodiment, when the first transistor and the second transistor are N-type transistors, the voltage applied to the first drain and the voltage applied to the second drain are greater than zero.

The invention also includes a target word line control terminal comprising at least one of a first word line and a second word line; the target word line control end is used for conducting the first transistor and the second transistor; the first grid electrode and the second grid electrode are connected with the first word line in a collinear manner, or the first grid electrode and the second grid electrode are respectively connected with the first word line; the first channel electrode and the second channel electrode are connected with the second word line in a collinear manner, or the first channel electrode and the second channel electrode are respectively connected with the second word line. That is, the voltage input control electrode in the embodiment of the present invention may be a gate electrode or a channel electrode, and a voltage may be applied to the gate electrode or the channel electrode.

It should be noted that the first junction capacitance and the second junction capacitance in the embodiments of the present invention may be the same or different. The junction capacitance is directly affected by the size of the gate and the channel electrode size, so that different gate or channel electrodes can make the junction capacitance different.

Referring to fig. 2, in some possible embodiments, the target word line control terminal includes a first word line L1 when the gate electrode serves as an input control electrode. In one embodiment, when the first junction capacitance is different from the second junction capacitance, the storage structure is connected in the following manner: the first grid G1 and the second grid G2 are connected with the same first word line L1 in a collinear manner; alternatively, in another embodiment, the first gate G1 and the second gate G2 are respectively connected to one first word line L1, that is, the first gate G1 and the second gate G2 are not connected to the same first word line L1. The input voltage of the first channel electrode is the same as or different from the input voltage of the second channel electrode; the first drain electrode D1 is connected with the first bit line BL; the second drain electrode D2 and the second bit line Connecting; the first source electrode S1 and the second source electrode S2 are connected to an output terminal, a ground terminal or a non-ground terminal.

Specifically, to realize that the first junction capacitance is different from the second junction capacitance, the dimensions of the first gate G1 and the second gate G2 may be set to be different, or the dimensions of the first channel electrode P1 and the second channel electrode P2 may be set to be different, and since the first junction capacitance is different from the second junction capacitance, the output current of the first transistor and the output current of the second transistor may be necessarily different.

In the read-write operation, the first channel electrode and the second channel electrode are suspended, the first word line L1 provides a gate voltage for the first gate and the second gate, the first bit line and the second bit line provide a drain voltage for the first drain and the second drain, respectively, the first transistor and the second transistor are in a conducting state, respectively generate electron flows in the first transistor and the second transistor, charges can be stored in the first junction capacitor and the second junction capacitor, and because the first junction capacitor and the second junction capacitor are different, the capacity of the first junction capacitor and the second junction capacitor for storing charges is different, so that the respective output currents of the first transistor and the second transistor can be different, the respective output currents of the first transistor and the second transistor can be read, the state in which high charges are stored can be defined as logic '1', the state in which low charges are stored is considered as logic '0', and when reading, the high output current is read as logic '1', and the low output current is read as logic '0', and the difference is obtained.

In a write operation, the first word line L1 provides a gate voltage to the first gate and the second gate, the first bit line and the second bit line provide drain voltages to the first drain and the second drain, respectively, the first transistor and the second transistor are in an on state, the input voltage of the first channel electrode and the input voltage of the second channel electrode form voltage differences between the two gate voltages, respectively, so as to change a storage state, the first junction capacitor and the second junction capacitor charge stored charges, and since the first junction capacitor and the second junction capacitor are different, the stored charges are different, the state in which the high charges are stored can be defined as logic "1", the state in which the low charges are stored can be defined as logic "0", for example, the original storage state is "0", then the respective output currents of the first transistor and the second transistor can be different, one corresponds to logic "1", the other corresponds to logic "0", and the difference between the two corresponds to realize the storage of "1". It is noted that the input voltage of the first channel electrode may be the same as or different from the input voltage of the second channel electrode, because the first junction capacitance is different from the second junction capacitance, and the output currents of the first transistor and the second transistor respectively are necessarily different.

In the erasing operation, the first word line L1 supplies the gate voltages to the first gate and the second gate, the first bit line and the second bit line supply the drain voltages to the first drain and the second drain, respectively, the first transistor and the second transistor are in the on state, the input voltage of the first channel electrode and the input voltage of the second channel electrode form voltage differences with the two gate voltages, respectively, the first junction capacitor and the second junction capacitor discharge charges, and finally the charges are discharged, and the currents of the first drain and the second drain approach zero, so that the storage states of the first transistor and the second transistor become "0".

With continued reference to fig. 2, in another embodiment, when the first junction capacitance is the same as the second junction capacitance, then the input voltage of the first channel electrode and the input voltage of the second channel electrode are set to be different, and other connection manners are unchanged, and the first gate and the second gate are connected in line with the same first word line, or, as before, the first gate G1 and the second gate G2 are respectively connected with different first word lines L1; the first drain electrode is connected with a first bit line; the second drain electrode is connected with a second bit line; the first source electrode and the second source electrode are commonly connected with an output end, a grounding end or a non-grounding end. The output currents of the first transistor and the second transistor may be different, so that the above-mentioned operations of reading, writing, storing and erasing may be implemented as well, which are not described herein.

When a single transistor is used as a memory, since the single transistor has the problem of sensitivity of process difference, the performance is easy to be influenced by tiny changes in the manufacturing process, and the current reading window of the single transistor is small in size, so that the latitude of the signal variability is limited, namely, 0 or 1 stored in the single transistor is difficult to be effectively identified under the condition of large noise signal variation.

Referring to fig. 3, in some possible embodiments, when the channel electrode is used as the input control electrode, the target word line control terminal includes the second word line L2, and in one example, when the first junction capacitance is different from the second junction capacitance, the connection manner of the storage structure is: the first channel electrode P1 and the second channel electrode P2 are connected with the same second word line L2 in a collinear manner; alternatively, in another embodiment, the first channel electrode P1 and the second channel electrode P2 are respectively connected to one second word line L2, that is, the first channel electrode P1 and the second channel electrode P2 are not connected to the same second word line L2. The input voltage of the first grid electrode is the same as or different from the input voltage of the second grid electrode; the first drain electrode D1 is connected with the first bit line BL; the second drain electrode D2 and the second bit line Connecting; the first source electrode S1 and the second source electrode S2 are connected to an output terminal, a ground terminal or a non-ground terminal.

In the read-write operation, the second word line L2 is suspended, a gate voltage is provided for the first gate and the second gate, a drain voltage is provided for the first drain and the second drain by the first bit line and the second bit line, respectively, the first transistor and the second transistor are in a conducting state, respectively, electrons flow in the first transistor and the second transistor, and charges can be stored in the first junction capacitor and the second junction capacitor.

In a write operation, a gate voltage is provided to a first gate and a second gate, a first bit line and a second bit line provide drain voltages to a first drain and a second drain respectively, a first transistor and a second transistor are in a conducting state, a second word line L2 applies an input voltage to a first channel electrode and a second channel electrode, the input voltage of the first channel electrode and the input voltage of the second channel electrode respectively form a voltage difference with two gate voltages to change a storage state, a first junction capacitor and a second junction capacitor charge stored charges, and since the first junction capacitor and the second junction capacitor are different, the stored charges are different, the state stored with high charges can be defined as logic "1", the state stored with low charges is considered as logic "0", for example, the original storage state is "0", the respective output currents of the first transistor and the second transistor can be different, one corresponds to logic "1", and the other corresponds to logic "0", and the difference is made between the two to realize storage of "1". It should be noted that the input voltage of the first gate may be the same as or different from the input voltage of the second gate, because the first junction capacitance is different from the second junction capacitance, and the output currents of the first transistor and the second transistor are necessarily different.

In an erase operation, a gate voltage is supplied to a first gate and a second gate, a first bit line and a second bit line supply drain voltages to a first drain and a second drain, respectively, a first transistor and a second transistor are in a conductive state, a second word line L2 applies an input voltage to a first channel electrode and a second channel electrode, the input voltage of the first channel electrode and the input voltage of the second channel electrode form a voltage difference with the two gate voltages, respectively, a first junction capacitor and a second junction capacitor discharge charges, and finally the charges are discharged, and currents of the first drain and the second drain approach zero, so that a storage state of the first transistor and the second transistor becomes "0".

With continued reference to fig. 3, in another embodiment, when the first junction capacitance is the same as the second junction capacitance, the input voltage of the first gate and the input voltage of the second gate are set to be different, and the other connection manner is unchanged, and the first channel electrode P1 and the second channel electrode P2 are connected in line with the same second word line L2, or, as before, the first channel electrode P1 and the second channel electrode P2 are respectively connected with different second word lines L2; the first drain electrode D1 is connected with the first bit line BL; the second drain electrode and the second bit line Connecting; the first source electrode S1 and the second source electrode S2 are connected to an output terminal, a ground terminal or a non-ground terminal. The output currents of the first transistor and the second transistor may be different, so that the above-mentioned operations of reading, writing, storing and erasing may be implemented as well, which are not described herein.

Referring to fig. 4, in one possible implementation, when the gate electrode and the channel electrode are both input control electrodes, the target word line control terminal includes a first word line and a second word line, and when the first junction capacitance is different from the second junction capacitance, the storage structure is connected in the following manner: the first gate G1 and the second gate G2 are connected with the first word line L1 in a collinear manner, or the first gate G1 and the second gate G2 are respectively connected with the first word line L1; the first channel electrode P1 and the second channel electrode P2 are connected with the second word line L2 in a collinear manner, or the first channel electrode P1 and the second channel electrode P2 are respectively connected with the second word line L2; the input voltage of the first word line is the same as or different from the input voltage of the second word lineThe method comprises the steps of carrying out a first treatment on the surface of the The first drain electrode D1 is connected with the first bit line BL; the second drain electrode D2 and the second bit line Connecting; the first source electrode S1 and the second source electrode S2 are connected to an output terminal, a ground terminal or a non-ground terminal.

In the read-write operation, the second word line L2 is suspended, the first word line L1 provides a gate voltage to the first gate and the second gate, the first bit line and the second bit line provide a drain voltage to the first drain and the second drain, respectively, the first transistor and the second transistor are in a conducting state, respectively generate electron flows in the first transistor and the second transistor, charges can be stored in the first junction capacitor and the second junction capacitor, and because the first junction capacitor and the second junction capacitor are different, the capacity of the first junction capacitor and the second junction capacitor for storing charges is different, the output currents of the first transistor and the second transistor can be read, the state in which high charges are stored can be defined as logic "1", the state in which low charges are stored is considered as logic "0", and when reading, the high output currents are read as logic "1", the low output currents are read as logic "0", and the difference is read to obtain reading "1".

In a write operation, a first word line L1 is used to provide a gate voltage to a first gate and a second gate, a first bit line and a second bit line are used to provide a drain voltage to a first drain and a second drain, respectively, a first transistor and a second transistor are in an on state, a second word line L2 is used to apply an input voltage to a first channel electrode and a second channel electrode, respectively, the input voltage of the first channel electrode and the input voltage of the second channel electrode form a voltage difference with two gate voltages to change a storage state, a first junction capacitor and a second junction capacitor charge and store charges, and since the first junction capacitor and the second junction capacitor are different, the stored charges are different, the state in which a high charge is stored can be defined as logic "1", the state in which a low charge is stored is regarded as logic "0", for example, the respective output currents of the first transistor and the second transistor can be different, one corresponds to logic "1", and the other corresponds to logic "0", and the difference realizes storage of "1". It is noted that the input voltage of the first word line may be the same as or different from the input voltage of the second word line, because the first junction capacitance is different from the second junction capacitance, and the output currents of the first transistor and the second transistor must be different.

In the erase operation, the first gate and the second gate are supplied with gate voltages through the first word line L1, the first drain and the second drain are supplied with drain voltages respectively, the first transistor and the second transistor are in a conductive state, the second word line L2 applies input voltages to the first channel electrode and the second channel electrode, the input voltages of the first channel electrode and the second channel electrode respectively form voltage differences with the two gate voltages, the first junction capacitor and the second junction capacitor discharge charges, and finally the charges are discharged, the currents of the first drain and the second drain approach zero, so that the storage states of the first transistor and the second transistor become "0".

With continued reference to fig. 4, in another embodiment, when the first junction capacitance is the same as the second junction capacitance, then the input voltage of the first word line L1 is different from the input voltage of the second word line L2, and the other connection manner is unchanged, and the first gate G1 and the second gate G2 are connected to the first word line L1 in a collinear manner, or the first gate G1 and the second gate G2 are respectively connected to the first word line L1; the first channel electrode P1 and the second channel electrode P2 are connected in line with the second word line L2, or the first channel electrode P1 and the second channel electrode P2 are respectively connected with the second word line L2. The first source electrode and the second source electrode are commonly connected with an output end, a grounding end or a non-grounding end. The output currents of the first transistor and the second transistor are different, so that the above operations of reading, writing, storing and erasing can be realized as well, and are not described herein.

In summary, since the channel region of the first transistor is provided with the first channel electrode, the first channel electrode and the channel region form a first junction capacitance, so that the first transistor has the capability of storing charges; the channel region of the second transistor is provided with a second channel electrode, and the second channel electrode and the channel region form a second junction capacitance, so that the second transistor has the capacity of storing charges. And when the specifications of the first gate G1 and the second gate G2 are set to be different, or the specifications of the first channel electrode P1 and the second channel electrode P2 are set to be different, the first junction capacitance and the second junction capacitance are different, and the capacity of the first junction capacitance and the second junction capacitance to store charges is also different.

Based on this structure, the first transistor and the second transistor are subjected to structural readjustment, and a circuit as shown in fig. 5 can be obtained. When a voltage is applied to the gate electrode or the channel electrode by the above embodiments, the first junction capacitance and the second junction capacitance store or release charges, and since the first junction capacitance and the second junction capacitance are different in size, storing different amounts of charges can be regarded as different storage states, for example, a state in which a high charge (large output current) is stored is regarded as a logic "1", a state in which a low charge (small output current) is stored is regarded as a logic "0", and two output results are bad to realize operations of reading, storing, holding, erasing, and the like.

By adopting the technical scheme, the two transistors realize the function of differential amplification, and the expansion of the size of a current reading window can be realized, namely, the change of 0 and 1 is recognized in a more loose range, which means that the memory structure of the two transistors can better cope with larger signal change and provide higher recognition reliability. Meanwhile, the differential amplifying circuit with a novel structure is adopted, and the size of charges and currents can be changed by regulating and controlling the voltage of the channel electrode, so that the amplification factor can be accurately regulated and controlled more accurately, efficiently and conveniently, and polymorphic regulation and control are realized. Such a structure implies both a better common mode rejection ratio and an amplification function of the differential mode signal.

In summary, since the channel region of the first transistor is provided with the first channel electrode, the first channel electrode and the channel region form a first junction capacitance, so that the first transistor has the capability of storing charges; the channel region of the second transistor is provided with a second channel electrode, and the second channel electrode and the channel region form a second junction capacitance, so that the second transistor has the capacity of storing charges. And when the specifications, dimensions, materials, voltages, etc. of the first gate G1 and the second gate G2 are set to be different, or the specifications, dimensions, materials, voltages, etc. of the first channel electrode P1 and the second channel electrode P2 are set to be different, the first junction capacitance and the second junction capacitance are different, and the capacity of the first junction capacitance and the second junction capacitance to store charges is also different.

Based on this structure, the first transistor and the second transistor are subjected to structural readjustment, and a circuit as shown in fig. 5 can be obtained. When a voltage is applied to the gate electrode or the channel electrode by the above embodiments, the first junction capacitance and the second junction capacitance store or release charges, and since the first junction capacitance and the second junction capacitance are different in size, storing different amounts of charges can be regarded as different logic, storage states, for example, a state in which high charges (large output current) are stored is regarded as logic "1", a state in which low charges (small output current) are stored is regarded as logic "0", and the two output results are bad to realize operations such as reading, storing, holding, erasing, and the like.

In summary, since the channel region of the first transistor is provided with the first channel electrode, the first channel electrode and the channel region form a first junction capacitance, so that the first transistor has the capability of storing charges; the channel region of the second transistor is provided with a second channel electrode, and the second channel electrode and the channel region form a second junction capacitance, so that the second transistor has the capacity of storing charges. And when the dimensions, materials, voltages, etc. of the first gate G1 and the second gate G2 are the same, or the dimensions, materials, voltages, etc. of the first channel electrode P1 and the second channel electrode are the same, the first junction capacitance and the second junction capacitance are the same, the capacity of charges stored in the first junction capacitance and the second junction capacitance is the same, the same working voltage is input, the same output current is obtained, different voltage conditions are input, different output currents can be obtained, and the difference is realized. When the capacitances are different, the same voltage conditions (such as the same gate voltage and the same channel electrode voltage) are input, and different output currents can be obtained; when the capacitances are different, different working voltages (such as different gate voltages and different channel electrode voltages) are input, and the same output current can be obtained. Therefore, the same output current and different output currents can be realized by adjusting the structure, the comparison size of the transistors and the voltage.

Based on this structure, the first transistor and the second transistor are subjected to structural readjustment, and a circuit as shown in fig. 5 can be obtained. When voltages are applied to the gate or channel electrode in the above embodiments, the channel current is controlled differently, and the state of storage, for example, the state in which high charge (large output current) is stored is regarded as logic "1", the state in which low charge (small output current) is stored is regarded as logic "0", and the two output results are inferior to each other to perform operations such as reading, storing, holding, erasing, etc.

Based on this structure, the first transistor and the second transistor are subjected to structural readjustment, and a circuit as shown in fig. 5 can be obtained. When a voltage is applied to the gate electrode in each of the above embodiments, the voltage of the channel electrode is extracted, and the extracted channel electrode can be regarded as a different logic or storage state, for example, a state in which the channel electrode outputs a high voltage (the output voltage is large) is regarded as a logic "1", a state in which the channel electrode outputs a low voltage (the output voltage is small) is regarded as a logic "0", and the two output results are bad to perform operations such as reading, storing, holding, erasing, and the like.

The storage may be single-value storage or multi-value storage, and the single-value storage may be realized by the above embodiment, and how to realize multi-value storage is described below. There are various implementations of multi-value memory technology, where different values can be represented by different charge storage states or different control voltages. In order to implement multi-value storage, in one possible implementation, a plurality of voltage input control electrodes are required, and then the embodiment of the present invention may be implemented by providing a plurality of sub-gates for the first gate and the second gate, or providing a plurality of sub-channel electrodes for the first channel electrode and the second channel electrode.

In one possible embodiment, the first gate includes one or more separate first sub-gates and the second gate includes one or more separate second sub-gates; the first channel electrode comprises one or more separate first sub-channel electrodes; the second channel electrode includes one or more separate second sub-channel electrodes.

Specifically, for the first transistor, the first sub-gates are respectively arranged on different sides of the channel region, so that separation of a plurality of first sub-gates is realized. In one embodiment, the first gate includes a first sub-gate that covers at least a portion or all of one side of the channel region, such as the first sub-gate covering a portion or all of the first side of the channel region; in another embodiment, the first gate comprises two first sub-gates, which each cover at least part or all of the two sides of the channel region, respectively, as shown with reference to fig. 1b, since the channel region comprises opposite first and third sides and opposite second and fourth sides, respectively, each first sub-gate covers at least part of the first side 21 and part of the fourth side 24 of the channel region, respectively. One or more first sub-gates may be provided corresponding to the same channel region, and the number of the first sub-gates may be set based on the requirement, and the plurality of first sub-gates may be used as a plurality of input electrodes, for example, as shown in fig. 6.

For the arrangement of the first sub-channel electrodes, the first channel electrode comprises one or more first sub-channel electrodes, and when the first sub-channel electrodes are provided, the first sub-channel electrodes can be located on the same side or different sides of the channel region. In an embodiment, the first channel electrode comprises a first sub-channel electrode located on one side of the channel region exposed by the first gate, such as shown with reference to fig. 1b, located on a third side 23 of the channel region; in another embodiment, the first channel electrode includes two first sub-channel electrodes, which are disposed on one side of the channel region at a predetermined distance, such that the two first sub-channel electrodes are not in contact with each other, for example, the two first sub-channel electrodes are disposed on a third side of the channel region at a predetermined distance. Corresponding to the same channel region, the number of the first sub-channel electrodes can be set based on the requirement, one or more first sub-channel electrodes can be set, and the plurality of first sub-channel electrodes can be used as a plurality of input electrodes.

For the second transistor, second sub-gates are respectively arranged on different sides of the channel region so as to realize separation of a plurality of second sub-gates. In one embodiment, the second gate includes a second sub-gate that covers at least a portion or all of one side of the channel region, such as the second sub-gate covering a portion or all of the first side of the channel region; in another embodiment, the second gate comprises two second sub-gates, the channel region comprising opposite first and third sides and opposite second and fourth sides, the two second sub-gates covering at least part or all of the two sides of the channel region, respectively, such as shown with reference to fig. 1b, each second sub-gate covering at least part of the first and fourth sides of the channel region, respectively. One or more second sub-gates may be provided as a plurality of input electrodes, corresponding to the same channel region, based on the number of second sub-gates required.

For the arrangement of the second sub-channel electrodes, the second channel electrode comprises one or more second sub-channel electrodes, and when a plurality of second sub-channel electrodes are provided, the plurality of second sub-channel electrodes can be located on the same side or different sides of the channel region. In an embodiment, the second channel electrode comprises a second sub-channel electrode located at one side of the channel region exposed by the second gate, such as shown with reference to fig. 1b, located at a third side 23 of the channel region; in another embodiment, the second channel electrode includes two second sub-channel electrodes, the two second sub-channel electrodes are disposed at a predetermined distance on one side of the channel region such that the two second sub-channel electrodes do not contact each other, and the two second sub-channel electrodes are disposed at a predetermined distance on a third side of the channel region. Corresponding to the same channel region, the number of the second sub-channel electrodes can be set based on the requirement, one or more second sub-channel electrodes can be set, and the plurality of second sub-channel electrodes can be used as a plurality of input electrodes.

Through the implementation mode, the plurality of sub-channel electrodes and the plurality of sub-grids are arranged, so that the number of transistors in a storage structure can be greatly reduced, the circuit structure is simplified, the integration level is improved, and multi-value storage is realized.

For a further better understanding of the memory structure of the present invention, the effect of the first transistor and the second transistor of the memory structure of the present invention will be described with reference to specific test data:

testing of simple differential storage: referring to FIG. 6, for example, by applying voltages to the first gate and the second gate, as shown in FIG. 7a, in one memory state, a current I flows through the first transistor _DS1 With the voltage V of the first grid _GS1 As shown in FIG. 7b, the current I flowing through the second transistor _DS2 With the voltage V of the second gate _GS2 As shown in FIG. 7c, the current I of the first transistor _DS1 Current I with the second transistor _DS2 There is a current difference Δi=i _DS2 -I _DS1 The method comprises the steps of carrying out a first treatment on the surface of the As shown in fig. 8a, in another memory state, a current I flows through the first transistor _DS1 With the voltage V of the first grid _GS1 As shown in FIG. 8b, the current I flowing through the second transistor _DS2 With the voltage V of the second gate _GS2 As shown in FIG. 8c, the current I of the first transistor _DS1 Current I with the second transistor _DS2 There is also a current difference Δi=i _DS2 -I _DS1 . The above description indicates that the differential current exists after the first transistor and the second transistor are conductedTherefore, differential storage can be realized, the size of a current reading window can be enlarged under different modulation states, and different current differences can be regulated and controlled, so that differential storage of data with different values can be realized.

And (3) testing bionic integration: referring to fig. 8, a transistor is used to simulate a biomimetic biological signal, using a first transistor as shown in diagram a of fig. 9, where an excitatory postsynaptic current (excitatory postsynaptic current, EPSC) is simulated, the EPSC being the current generated when a neuron receives an input from an excitatory synapse, and when the excitatory synapse releases a neurotransmitter (e.g., glutamate) into the synaptic cleft, these transmitters bind to the excitatory receptor of the receiving neuron, causing ion channels to open, thereby producing an EPSC. By applying a voltage pulse signal to the first transistor, the current I of the first transistor can be found _DS1 Pulse current is also generated, which means that the first transistor in the embodiment of the invention can generate a bionic signal. Likewise, taking the first transistor as an example, as shown in the b diagram of FIG. 9, two different voltage pulse signals-0.2V and 0V are applied to the first gate of the first transistor, the current I of the first transistor _DS1 Corresponding pulse currents are generated respectively, so that the grid electrodes or channel electrodes of the first transistor and the second transistor are different, and voltage pulses are applied to the first transistor and the second transistor, so that the first transistor and the second transistor correspond to different voltage pulses, different pulse currents are generated, and differential storage is realized. Taking the second transistor as an example, as shown in figure 9 c, here mimicking Paired-pulse motion (PPF), PPF is a short-term synaptic plasticity phenomenon that is typically observed between two short-time-interval stimulation pulses. When two pulses stimulate synapses at certain intervals, the second pulse will induce a larger EPSC than the first pulse. This is because the first pulse causes some pre-synaptic region to react, resulting in a greater amount of delivered by the second pulse, thus enhancing the EPSC. PPF is generally thought to be caused by a short-term increase in presynaptic region release transmitter. Applying different dipulse signals-0.2V and 0V to the second gate of the second transistor, a second Current I of transistor _DS2 Corresponding double pulse currents are generated respectively, which means that the second transistor in the embodiment of the invention can generate bionic signals.

According to another aspect of the present invention, there is provided a memory array, referring to fig. 10, including: the above-mentioned multiple differential memory structures, the said multiple differential memory structures form the array according to row and column, and, source areas of the first transistor and second transistor located in the same row in the said multiple differential memory structures are connected to the fixed potential; a plurality of first bit lines, wherein first drains of the plurality of differential storage structures located in the same row are connected with the corresponding first bit lines; the second drains of the differential storage structures are positioned in the same row and are connected with the corresponding second bit lines; the first source electrode and the second source electrode are commonly connected with an output end, a grounding end or a non-grounding end; the first grid electrode and the second grid electrode of the differential storage structure, which are positioned in the same row, can be connected in a collinear way or respectively connected with the corresponding word lines; the first channel electrode and the second channel electrode may be connected by a common word line or by word lines, respectively.

According to another aspect of the present invention, there is provided a data operation method of the above memory array, including: in a write operation, applying a gate voltage via a selected one of the plurality of word lines and a drain voltage via a selected one of the plurality of first bit lines to place a selected memory transistor in an on state, and applying a control region voltage to the selected memory transistor via a selected one of the plurality of word lines to change a memory state of the selected memory transistor; and in a read operation, applying a gate voltage via a selected one of the plurality of word lines and a drain voltage via a selected one of the plurality of first bit lines to place the selected memory transistor in an on state, and detecting a drain current of the selected memory transistor via the selected one of the plurality of first bit lines to obtain a memory state of the selected memory transistor.

On the other hand, the invention also relates to a memory integrated array based on the memory structure, which uses the array to map convolution multiply-add calculation in the memory integrated,the integrated memory-calculation array integrates calculation and storage, utilizes the channel electrode as an output end to realize logic states of different storage currents, and then performs calculation processing to realize a more efficient integrated memory-calculation scheme. Referring to fig. 11, an array of six transistors is taken as an example, each two transistors are in a group, three groups are connected in parallel, the connection mode can be consistent with that in the above embodiment, two transistors in each group share a source, drains of the two transistors are not connected with a bit line and a bit line respectively, two transistors are connected with a first word line L1, channel electrodes of the two transistors are connected with a control voltage, junction capacitances of the two transistors are different, three groups are all connected in parallel, and gates of the transistors in each group are connected with word lines L1, L2 and L3 respectively. For each group of transistors, the input voltage of the first word line L1 is different from the control voltage of the channel electrode, the grid voltages are provided for the grid electrodes of the two transistors through the first word line L1, the bit line and the bit line do not respectively provide the drain voltages for the drain electrodes of the two transistors, the two transistors are in a conducting state, the input voltages of the two channel electrodes respectively form voltage differences with the two grid voltages, the first junction capacitor and the second junction capacitor charge and store charges, the output currents of the two transistors can be different to form different output currents I ₁ And I ₂ The method comprises the steps of carrying out a first treatment on the surface of the Then there are six different output currents in total for three groups of transistors, and each transistor has a junction capacitance, which can store charge, and the preservation of current state can last for a considerable period of time, during which time a combination of memory and calculation can be realized, and logic operations such as addition/multiplication are realized for different output currents. In other embodiments, the integrated memory array according to the present invention is not limited to the connection method and the number of transistors in the above-described embodiments.

On the other hand, the present invention can be designed into a memory array based on the above memory structure, as shown in fig. 12. The method is characterized in that a formed memory array is provided with a plurality of memories which are arranged in an array manner along the row and column directions; and a plurality of word lines, the gate conductors of the memories in the same row being connected to the same word line.

A plurality of first bit lines to which channel control regions of memories located in the same column or the same row of the plurality of memories are connected; a plurality of second bit lines, wherein drain regions of memories located in the same column in the plurality of memories are connected to the same second bit line;

The data operation method of the memory array comprises the following steps: in a write operation, applying a gate voltage via a selected one of the plurality of word lines and a drain voltage via a selected one of the plurality of second bit lines to turn on a selected memory transistor, and applying a control region voltage via a selected one of the plurality of first bit lines to the selected memory to change a storage state of the selected memory;

in a read operation, a gate voltage is applied via a selected one of the plurality of word lines and a drain voltage is applied via a selected one of the plurality of second bit lines to place a selected memory in an on state, and a drain current of the selected memory transistor is detected via a selected one of the plurality of second bit lines to obtain a storage state of the selected memory.

The channel electrode is processed through doping process, deposition process, epitaxy process, self-assembly process, spin-coating process, self-assembly process, roll-to-Roll process, hydrothermal process, embossing process, rolling process, printing process, and vapor plating process.

One or more of ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material, memory effect material, semiconductor material, conductor material, insulating material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, silicide as an insulating layer additive layer, insulating layer material, insulating layer additive material, semiconductor layer material, semiconductor channel material, or channel electrode material. Logic polymorphism and memory polymorphism can be realized.

Ferroelectric material, magneto-electric material, phase change material, quantum effect material, resistance change effect material, memory effect material, etc. as an insulating layer addition layer, insulating layer material, insulating layer addition material, semiconductor layer material, semiconductor channel material, or channel electrode material. Logic polymorphism and memory polymorphism can be realized.

Ferroelectric, phase change or magneto-electric materials in the gate dielectric, semiconductor layer, semiconductor channel;

in one possible embodiment, the ferroelectric material is one of H3S, nbN, laH, baTiO3, pbZrxTi1-xO3, biFeO3, CIPS (CuInxP (3-x) Sy, e.g., cuInP2S 6), HZO (HfZrOx), moTe2, zrTiO4, pbTiO3, ba (Zr, ti) O3, srTiO3, baWO4, baFe12O19, YBCO (YBa 2Cu3O7-x, e.g., YBa2Cu3O 7), BFMO (BiFe 1-xMnxO3, e.g., biFe0.9Mn0.1O 3), PCMO (Pr 1-xCaxMnO3, e.g., pr0.7Ca0.3MnO3), LBCO (La 2-xBaxCuO4, e.g., la1.9Ba0.1 CuO4), smFeAsO1-xFx (e.g., smFeAs0.85F0.15), caK (Fe 1-xMnOx 4), or MxFe0.85.MxAs (e.g., mxO4.85.MxAs).

In one possible embodiment, the superconducting material is one or more of H2S, ceCu Si, ceTIn5, cePt3Si, ba0.6K0.4Fe2As2, laNiC2, laNiGa2, caPtAs, Y3Fe5O12/Al, 2H-MX2 (M= transition metals; X=chalcogenide), 2H-NbSe2, (magic-angle twisted trilayer graphene) (MATG), 2H-WS2, 2HeTaS2, 1Td-MoTe2, W2N3, 1T-PdTE2, pb10-xCux (PO 4) 6, (Li, fe) OHFeSe, cuInCo Te 4.

In one possible embodiment, the phase change material is VO2, ge15Sb85, ga36Sb64, fe3O4, nbO2, PEG ((C2H 4O) n), an alloy of indium (In) and tin (Sn), C60, C70, etc.; RMS (RexMo 1-xS 2), GST ((GeTe) X (Sb 2Te 3) y, AIST ((Ag 1-xTex) (Sb 1-xTex) 2, e.g. Ag5In5Sb60Te 30), GSST (e.g. Ge2Sb2Se1Te4, ge2Sb2Se4Te 1), gd5 (Si 1Ge 1-X) 4 (e.g. Gd5Si2Ge 2), laFe13-xSix (e.g. LaFe12 Si), la0.5pr0.5fe11.5-xcaxsi1.5c0.2 (e.g. la0.5pr0.5fe10.7co0.8si1.5c0.2 (e.g. Ge2Sb2Te 5), sb2Te3, GSB ((GeSn) X (Sb) y (e.g. GeSnSb), AST ((AlSb 2) X (Te) y, e.g. al1.5sbte) and tasg. Ti48As30Si 12.

In one possible embodiment, the magneto-electric material is one or more of ZrTiO4, fe2O3, fe3O4, srBaTiO3, sr1-xBaxTiO3, bi4Ge3O12, baTiO3, ba0.8Sr0.2TiO3, niO, niZnFe2O4, liNbO3, BTO-PZT, baFe12O19, cr2O3, biFeO3, biMnO3, and LuFe2O4, FCSB (Fe 90Co78Si12B 10), PMN-PZT ((Pb (Mg 1/3Nb 2/3) O3) 1-x- (Pb (Zr 1-yTiy) O3) x, such as Pb (MgxNb 1-x) O3-PbZrO3-PbTiO 3), PMN-PT ((Pb (Mg 1/3Nb 2/3) O3) 1-x- (PbTiO 3) x, such as Pb (Mg 1/3Nb 2/3) O3-PbTiO 3).

In one possible embodiment, the quantum effect materials are YBCO, pbLaTiO3, cdSe, gaAs, pbSe, BBO, PPLN, and lead, zinc tin alloys. Cold atomic gas (such as rubidium, lithium, sodium), and one or more of magnetic materials such as iron, nickel, cobalt, etc.

In one possible embodiment, the resistive effect material is one of ZrO2, tiO2, ta2O5, biFeO3, srRuO3, srZrO3, fe3O4, znFe2O4, baTiO3, pb (Mg 1/3Nb 2/3) O3-PbTiO3, ba (sr0.7ba0.3) TiO3, in2O3-SnO2, cu2ZnSnSe4, polystyrene (PS), la1-xSrxMnO3, (Pb, fe) NbO3CuOx (e.g., cuo0.5), moS2-xO4 (e.g., moS2O 4), hfOx (e.g., hfO 2), WOX (e.g., WO 2), PCMO (Pr 1-xCaxMnO3, e.g., pr0.7ca0.3mno3), LSMO (LaxSr 1-xMnO3, e.g., la0.5sr0.5mn3), laxo (e.caxca1-xMnO 3, e.g., 0.7ca3), etc.

In one possible embodiment, the storage effect material is one or more of Fe3O4, fe2O3, coFe (cobalt iron alloy), feCo, feAlSi, fePt, mnFe, feNi, coPt, coFeB, sbI3, polycarbonate, si3N4, siO2, siOxNy, se, baFe O19, niFe, agCl, agBr, ge Sb2Te5, geSbTe, al2O3/Fe, fearox, polyaniline (PANI).

In one possible embodiment, the superconducting effect material is one or more of YBa2Cu3O7 (yttrium alloy copper oxide), ba (Fe 1-xCox) 2As2, pb, mgB2, cuInSe2, laFeAsO, ba (Fe, co) 2As2, BSCCO, gdBCO, IBi2Sr2Ca2Cu3O10 (BSCCO), tl2Ba2CuO6, YBa2Fe3Se 5.

In one possible embodiment, the semiconductor effect material is one or more of Si, in2Se3, gaAs, gaP, cdSe, znSe, pbSe, BN, znS, pbS, inP, gaN, al Se3, alAs, inAs, siGe, cdSe, and the like.

In one possible embodiment, the perovskite material is one or several of CsPbBr3, MAPbI3-xClx, SBT (SrBi 1-xTixO9, e.g. SrBiTiO 9), BLT (Bi 4-xLaxTi3O12, e.g. Bi3.5La0.5Ti3O12), PZT (PbZr 1-xTixO3, e.g. PbZr0.7Ti0.3O3), cs1-xFAxPbBr3, e.g. Cs0.8FA0.2PbBr3, CH3NH3PbX3 (e.g. CH3NH3PbBr3, CH3NH3PbI 3).

In one possible embodiment, the two-dimensional material is one or more of GaS, H-BN, as2Te3, bi2S3, 2H-WS2, gaSe, geS, geSe, hfS2, hfSe2, in2Se3, moS2, 2H-MoS2, moTe2, moSe2, moSSe, moWS2, moWSe2, reS2, reSe2, sb2Te3, snS2, snSe2, 1T-TaS2, WSe2, zrSe3, ACS, and the like.

As shown in fig. 13, since ferroelectric material, magneto-electric material, phase change material, quantum effect material, resistance change effect material, memory effect material are added, the transistor can have two states of memory 0 and memory 1, then the logic states 0 and 1 given in the memory 0 of the transistor are different, and the logic states 0 and 1 when the transistor stores 1 are different, so that multi-state memory can be realized.

As shown in fig. 14, since ferroelectric material, magneto-electric material, phase change material, quantum effect material, resistive effect material, and memory effect material are added, the transistor can have two memory states of 0 and 1 after the junction capacitance of the channel and the channel electrode is introduced by adding the channel electrode and has charge storage effect, so that the logic states 0 and 1 given by the new memory 0 of the transistor are different from the logic states 0 and 1 given by the new memory 0 of the transistor, and the logic states 0 and 1 given by the new memory 1 of the transistor are different from the states before the memory is regulated by the channel electrode. By regulating the memory state of the transistor through the channel electrode, more multi-state memory can be realized.

In short, the states before and after the storage are regulated and controlled by the channel electrode are different, and the states before and after the storage are also different by adding ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistance change effect materials and transistors for storing the effect materials, and the two storage modes are organically combined to cause more logic states and storage states.

By adding ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material, storage effect material and organically combining channel electrode to regulate the storage state of the transistor, the device and more polymorphic storage can be realized compared with the prior device which only adds ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material, storage effect material, has no channel electrode or only channel electrode, has no ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material and storage effect material.

In addition, further describing the manufacturing technology of the transistor used in the embodiment of the present invention, fig. 15 is a schematic diagram of a typical process preparation flow of adding a channel electrode transistor provided in the embodiment of the present invention, (1) preparing a substrate: first, an appropriate semiconductor material is selected as a substrate, and chemical and physical treatments are performed to remove impurities and impurities. (2) forming transistor portions: and forming a transistor channel, a gate oxide layer, a source electrode, a drain electrode, a channel electrode and a gate electrode by using technologies such as oxidation, photoetching, doping, deposition, etching and the like. (3) forming a contact: metal contacts are formed on the gate, source, drain, and control regions using photolithography and etching techniques to connect to external circuitry. (4) surface planarization: uneven surfaces may occur during the manufacturing process. A surface planarization process is required. (5) metallization: in a final step, the entire transistor is metallized, connecting the transistor electrode to an external circuit.

The above is only a typical process flow for the channel electrode transistor fabrication process.

The above is only a typical process flow for the channel electrode transistor fabrication process. The structure can be realized by an existing process line, can be realized based on the adjustment of the existing process steps, and can be made of a semiconductor material, a conductor material or a combination of several materials. The actual manufacturing process may vary depending on factors such as manufacturer, device size, and process technology.

Fig. 16 and 17 are a schematic plan view and a schematic three-dimensional structure of a transistor having a channel electrode according to the present invention. The substrate 1 is a semiconductor substrate, the surface of the substrate 1 is covered with an insulating layer 5, the material may be oxide such as silicon dioxide or a high-K material, in one possible embodiment, the material of the insulating layer 5 is a silicon dioxide insulating layer, a portion corresponding to the first source region 3 and the first drain region 4 is etched on the insulating layer 5, a first source electrode 31 is disposed on the surface of the first source region 3 facing away from the substrate 1, and a first drain electrode 41 is disposed on the surface of the first drain region 4 facing away from the substrate 1. The insulating layer 5 between the first source electrode 31 and the first drain electrode 41 draws out the electrode as the first gate electrode 51, and the first gate electrode 51 is electrically insulated from the first source electrode 31 and the first drain electrode 41. A channel region 2 is provided in the semiconductor substrate between the first source region 3 and the first drain region 4, said channel region 2 comprising a plurality of sides. A first source 31 is arranged on the surface of the first source region 3 facing away from the substrate 1 and a first channel electrode 6 forms a first junction capacitance with said channel region 2 for storing charge. The first gate electrode 51 and the first channel electrode 6 serve as input control electrodes in a differential memory structure.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory structure, comprising:

2. The memory structure of claim 1, wherein the target word line control terminal comprises the first word line, the first gate and the second gate are connected collinearly with the first word line when the first junction capacitance is different from the second junction capacitance, or the first gate and the second gate are each connected with the first word line, respectively; the input voltage of the first channel electrode is the same as or different from the input voltage of the second channel electrode;

3. The memory structure of claim 2, wherein the target word line control terminal comprises the first word line, the first gate and the second gate are connected collinearly with the first word line when the first junction capacitance is the same as the second junction capacitance, or the first gate and the second gate are each connected with the first word line, respectively; the input voltage of the first channel electrode is different from the input voltage of the second channel electrode;

4. The memory structure of claim 1, wherein the target word line control terminal comprises the second word line, the first channel electrode and the second channel electrode are connected collinearly with the second word line when the first junction capacitance is different from the second junction capacitance, or the first channel electrode and the second channel electrode are each connected with the second word line, respectively; the input voltage of the first grid electrode is the same as or different from the input voltage of the second grid electrode;

5. The memory structure of claim 4, wherein the target word line control terminal comprises the second word line, the first channel electrode and the second channel electrode are connected collinearly with the second word line when the first junction capacitance is the same as the second junction capacitance, or the first channel electrode and the second channel electrode are each connected with the second word line, respectively; the input voltage of the first grid electrode is different from the input voltage of the second grid electrode;

6. The memory structure of claim 1, wherein the target word line control terminal comprises the first word line and the second word line, the first gate and the second gate are connected collinearly with the first word line when the first junction capacitance is different from the second junction capacitance, or the first gate and the second gate are each connected with the first word line, respectively;

7. The memory structure of claim 6, wherein the target word line control terminal comprises the first word line and the second word line, the first gate and the second gate are connected collinearly with the first word line when the first junction capacitance is the same as the second junction capacitance, or the first gate and the second gate are each connected with the first word line, respectively;

8. The memory structure of claim 1, wherein the first gate comprises one or more separate first sub-gates and the second gate comprises one or more separate second sub-gates;

9. The memory structure according to claim 1, wherein one or more of a ferroelectric material, a magneto-electric material, a phase change material, a quantum effect material, a resistance change effect material, a memory effect material, a semiconductor material, a conductor material, a superconducting material, an insulating material, a dielectric material, a two-dimensional material, a one-dimensional material, a three-dimensional material, a perovskite material, an oxide, a sulfide, a cyanide, a hydride, a silicide is used as the insulating layer additive layer, the insulating layer material, the insulating layer additive material, the semiconductor layer material, the semiconductor channel material, or the channel electrode material.

10. The memory structure according to claim 1, wherein the channel electrode is processed by a doping process, or/and a deposition process, or/and an epitaxy process, or/and a self-assembly process, or/and a spin-coating process, or/and a self-assembly process, or/and a Roll-to-Roll process, or/and a hydrothermal process, or/and an embossing process, or/and a rolling process, or/and a printing process, or/and an evaporation process.

11. A memory comprising a memory structure as claimed in any one of claims 1 to 10.

12. A memory array, comprising:

a plurality of memories according to claim 11, the plurality of memories being arranged in an array in a row and column direction;

13. A differential amplifying circuit comprising a memory structure as claimed in any one of claims 1 to 10.

14. A chip comprising a memory structure as claimed in any one of claims 1 to 10.

15. A circuit comprising a memory structure as claimed in any one of claims 1 to 10.

16. An electronic device comprising the circuit of claim 15.