KR20150124498A - Semiconductor Device Having Fin Gate and Method of Manufacturing The Same - Google Patents

Abstract

The present technique relates to a semiconductor device having a fin gate capable of improving an operating current, and a method of manufacturing the same. The semiconductor device includes an active pillar which is formed in the upper part of a semiconductor substrate and surrounds a first region and at least a side of the first region; and a fin gate which is extended to overlap the upper side and lateral side of the active pillar. The first region of the active pillar comprises a semiconductor layer which has a smaller lattice constant than the second region of the active pillar.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device having a pin gate structure, a resistance change memory device including the same,

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a PMOS transistor having a fin gate structure, a resistance change memory device including the PMOS transistor, and a manufacturing method thereof.

With the rapid development of mobile and digital information communication and consumer electronics industries, it is expected that device research based on charge control of existing electron will be limited. Therefore, development of a novel functional memory device which is not a concept of an existing electronic charge device is required. In particular, in order to meet the demand for increasing the memory capacity of the main information equipment, it is necessary to develop a next-generation high-capacity super-high-speed and super-power memory device.

At present, a resistance change memory using a variable resistance material as a memory medium has been proposed as a next generation memory device, and typically includes a phase change memory device, a resistance memory, and a magnetoresistive memory.

The resistance change memory device has a basic configuration of an access element and a resistance element, and stores data of "0" or "1" according to the state of the resistance element.

However, improvement of integration density is also a top priority for such a resistance change memory device, and it is important to integrate the largest memory cell in a narrow area.

To meet this demand, the resistance change memory also employs a three-dimensional transistor structure. The three-dimensional transistor may include a three-dimensional vertical channel and a surrounding gate or a three-dimensional horizontal channel and a fin gate.

Since the three-dimensional transistor of the resistance change memory is also used as a switching element, it is required to provide a high operating current.

Embodiments of the present invention provide a PMOS transistor having high operating current characteristics, a resistance change memory device including the PMOS transistor, and a method of manufacturing the same.

The semiconductor device according to an embodiment of the present invention includes: an active filament formed on a semiconductor substrate and including a first region and a second region surrounding at least one side of the first region; And a fin gate extending to overlap the upper surface and the side surface of the active pillar, wherein the first region of the active pillar may be composed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar .

Also, the resistance change memory device according to an embodiment of the present invention includes an active filer including a channel region and a P-type source and drain located on both sides of the channel region, an active filament And a variable resistor electrically extended with the drain, wherein the active pillar includes an inner region and an outer region formed to surround at least one surface of the inner region, And a compress stress is generated at a junction interface between the inner region and the outer region.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming an active filament on a semiconductor substrate, the active filament having a lattice constant smaller than that of an external material; Forming a gate insulating film on a surface of the active pillars; And forming a pin gate on the gate insulating film so as to surround three sides of the active pillars.

According to the present invention, in the pillars having the inside and the outside, the inside where the channels are formed substantially can be made of a material having a smaller lattice constant than the outside. Accordingly, as the compressive stress is applied to the inside of the pillar, the channel mobility of the PMOS transistor, that is, the current driving capability can be greatly increased.

In addition, by using the pin gate, the gate electric field is applied from the three surfaces of the channel, and the operation characteristics of the PMOS transistor can be further improved.

FIGS. 1A to 1D are cross-sectional views for explaining a method of manufacturing a PMOS transistor having a pin gate according to an embodiment of the present invention.
2 is a perspective view of a PMOS transistor having a fin gate fabricated according to an embodiment of the present invention.
3A to 3E are cross-sectional views illustrating a method of manufacturing a PMOS transistor having a pin gate according to another embodiment of the present invention.
4 is a perspective view of a PMOS transistor having a pin gate according to another embodiment of the present invention.
5 is a perspective view of a resistance change memory device having a pin gate according to an embodiment of the present invention.
6 to 8 are perspective views showing a pillar of a semiconductor device having a pin gate according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

First, referring to FIG. 1A, a semiconductor substrate 200 is prepared. The semiconductor substrate 200 may be, for example, a Si substrate containing a first conductivity type impurity, for example, an n-type impurity. A first semiconductor layer 210 is deposited on the semiconductor substrate 200. The first semiconductor layer 210 may be made of a material having a lattice constant smaller than that of the semiconductor substrate 200. As the first semiconductor layer 210 of this embodiment, for example, one selected from SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BP and InN may be used. The first semiconductor layer 210 may be a region in which a substantial channel is to be formed, and the thickness thereof may be determined in consideration of the channel length. For example, the first semiconductor layer 210 may be monocrystalline grown by an epitaxial growth method. When the first semiconductor layer 210 is formed by the epitaxial growth method, the hole mobility characteristics can be improved as compared with the case where the first semiconductor layer 210 is formed in the polycrystalline state.

Referring to FIG. 1B, the first semiconductor layer 210 and a part of the semiconductor substrate 200 are patterned to form a pre-filler P. Reference numeral 210a denotes a patterned first semiconductor layer and 200a denotes a patterned semiconductor substrate portion. The pre-pillar P of this embodiment may be a structure having a certain length, that is, a structure extending in a line shape.

Referring to FIG. 1C, a second semiconductor layer 222 is formed on a semiconductor substrate 200 on which a pre-filler P is formed. The second semiconductor layer 222 may be formed of the same material as the semiconductor substrate 200, for example, Si, and may be formed by an epitaxial growth method, for example.

Referring to FIG. 1D, a gate insulating layer 230 and a gate conductive layer are deposited on the second semiconductor layer 222. The gate insulating layer 230 may be formed by an oxidation process of the second semiconductor layer 222 or may include a metal oxide such as TaO, TiO, BaTiO, BaZrO, ZrO, HfO, LaO, AlO, YO, and ZrSi, Or the like. The gate conductor may be formed of a material selected from the group consisting of W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ta, Tisi, TaSi, TiW, TiON, TiAlON, WON, TaON, or a doped polysilicon film.

As shown in FIG. 2, a gate conductor is patterned in a substantially line shape so as to intersect with the active pillars P, thereby forming a fin gate 240. At the time of gate conductor patterning, the gate insulating film 230 can be simultaneously patterned. Thus, the pin gate 240 can overlap the top and both sides of the active pillars P.

An impurity of a second conductivity type such as a high concentration n type impurity is implanted into the active pillars P on both sides of the pin gate 240, (S), and the drain (D) can be formed on the other side. The source S and drain D may be formed in a lightly doped drain (LDD) manner to reduce short channel effects such as gate induced drain leakage (GIDL).

When implementing the resistance change memory, the bit line and the variable resistor can be formed in a known manner to be electrically connected to the drain D.

The three-dimensional transistor having the pin gate 240 is formed of a semiconductor material having a lattice constant smaller than that of the outside, in the active filament P in which the channel is formed. A compressive stress due to a difference in lattice constant may be generated at the joint interface between the inside and the outside of the active filament P. If compression stress is provided inside the active filament P, the carrier mobility of the PMOS transistor having the hole as the main mobility can be greatly increased. Thus, the current driving capability of the PMOS transistor is improved.

Referring to FIG. 3A, a semiconductor substrate 200 is prepared. The semiconductor substrate 200 may be, for example, a Si substrate containing a first conductivity type impurity, for example, an n-type impurity. As the n-type impurity, for example, P or As ion may be used. A first semiconductor layer 210 and a second semiconductor layer 220 are sequentially stacked on the semiconductor substrate 200. The first semiconductor layer 210 may be made of a material having a smaller lattice constant than that of the semiconductor substrate 200 made of Si. As the first semiconductor layer 210, for example, one selected from SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BP and InN may be used. The thickness of the first semiconductor layer 210 may be determined in consideration of the channel length. Also, the first semiconductor layer 210 can be monocrystallically grown by an epitaxial growth method in consideration of hole mobility characteristics. The second semiconductor layer 220 may be formed on the first semiconductor layer 210. The second semiconductor layer 220 may be formed of Si, which is the same material as the semiconductor substrate 200, for example.

Referring to FIG. 3B, the second semiconductor layer 220, the first semiconductor layer 210, and a part of the semiconductor substrate 200 may be patterned to form the preliminary pillars P1. Reference numeral 220a denotes a patterned second semiconductor layer, 210a denotes a patterned first semiconductor layer, and 200a denotes a patterned semiconductor substrate portion. The spare pillars P1 can be extended with a predetermined length. That is, the preliminary pillars P1 may correspond to line structures.

Referring to FIG. 3C and FIG. 4, a third semiconductor layer 225 having a larger lattice constant than the first semiconductor layer 210a is formed on the outer surface of the pre-pillar P1 (see FIG. 3B). For example, the third semiconductor layer 225 may be formed of Si, which is the same material as the semiconductor substrate 200 and the second semiconductor layer 220a. In addition, the third semiconductor layer 225 may be formed using an epitaxial growth method, or may be formed by a deposition and a spacer formation process. According to the formation of the third semiconductor layer 225, the first semiconductor layer 210a is entirely covered with a semiconductor material having a lattice constant larger than that of the first semiconductor layer 210a, for example, a Si material It can be surrounded. Thus, the active pillars P on which the three-dimensional transistors are to be formed can be formed.

Referring to FIG. 3E, the surface of the active pillars P and the exposed semiconductor substrate 200 are oxidized to form a gate insulating film 230. Although the gate insulating film 230 of the present embodiment is formed by the oxidation method, the gate insulating film 230 can be formed by an evaporation method without being limited thereto. When the gate insulating film 230 is formed by a deposition method, a metal oxide such as TaO, TiO, BaTiO, BaZrO, ZrO, HfO, LaO, AlO, YO and ZrSi, nitride or a composite film thereof may be used. In addition, the gate insulating layer 230 formed on the surface of the semiconductor substrate 200 may be thicker than the active pillars P, or may have the same thickness.

Referring to FIGS. 3E and 5, a gate conductor may be deposited over the structure of the semiconductor substrate 200 on which the active pillars P are formed. The gate conductor may be formed of a material selected from the group consisting of W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ta, Tisi, TaSi, TiW, TiON, TiAlON, WON, TaON, or a doped polysilicon film.

The gate conductor may then be patterned in part to form a fin gate 240. The pin gate 240 may be formed to overlap with the top surface and a part of the side surface of the active pillar P coated with the gate insulating film 230, as shown in FIG.

An impurity of a second conductivity type, for example, a high concentration n type impurity is implanted into the active pillars P on both sides of the pin gate 240, S, and the drain D can be formed on the other side. The source S and drain D may be formed in a lightly doped drain (LDD) manner to reduce short channel effects such as gate-induced drain leakage (GIDL).

Thereafter, a variable resistor Rv connected to the bit line BL may be formed in a known manner to be electrically connected to the drain D. Here, the variable resistor Rv may be formed of a material selected from the group consisting of a PCMO film which is a material of the resistance memory, a chalcogenide film which is a material of the phase change memory, a magnetic layer which is a material of the magnetic memory, a magnetization reversing element layer which is a material of the STTMRAM, It can be used variously. Although not shown in the drawing, a heating electrode may be further interposed between the variable resistor Rv and the drain D.

The present invention is not limited to the above embodiments.

6, the first semiconductor layer 210a of the preliminary filer P1 includes a first sub-semiconductor layer 210-1, a second sub-semiconductor layer 210-2, and a third sub- 210-3. When the first semiconductor layer 210a is made of SiC, the first sub-semiconductor layer 210-1 and the third sub-semiconductor layer 210-3 are formed of a SiC layer containing C at a stoichiometric ratio of SiC or less (Hereinafter referred to as a C low-concentration SiC layer), and the second sub-semiconductor layer 210-2 may be a SiC layer (hereinafter, referred to as a C-high-concentration SiC layer) in which C is included in a stoichiometric ratio of SiC or more. When the content of C is increased in the SiC layer, the lattice constant tends to decrease. Therefore, among the first semiconductor layer 210a, the material having the smallest lattice constant is formed in a substantial effective channel zone, and thus the hole mobility in the channel can be increased. The sub-semiconductor layers 210-1, 210-2, and 210-3 may be stacked by a deposition method.

7, the active pillars P may be configured to expose the upper surface of the first semiconductor layer 212. [ Accordingly, the pin gate 240 and the first semiconductor layer 212 may overlap with each other with a gate insulating film (not shown) therebetween.

8, the first semiconductor layer 212 may include a stacked Ge low-concentration SiGe layer 212-i, and an active pillar P- 1) and Ge high-concentration SiGe layer 212-2.

According to the present embodiment, in the pillars having the inside and the outside, the inside where the channel is formed substantially can be made of a material having a smaller lattice constant than the outside. Accordingly, as the compressive stress is applied to the inside of the pillar, the channel mobility of the PMOS transistor, that is, the current driving capability can be greatly increased.

In addition, the gate electric field is applied from the three surfaces of the channel by using the pin gate, and the operation characteristics of the MOS transistor can be further improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but variations and modifications may be made without departing from the scope of the present invention. Do.

200: semiconductor substrate 210, 210a: first semiconductor layer
220, 220a: second semiconductor layer 225: third semiconductor layer
240: pin gate

Claims (18)

An active filament formed on the semiconductor substrate and consisting of a first region and a second region surrounding at least one side of the first region; And
And a fin gate extending to overlap the top and side surfaces of the active pillars,
And the first region of the active pillars is composed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillars. The method according to claim 1,
And a gate insulating film interposed between the active pillar and the pin gate. The method according to claim 1,
The active pillars extend in a direction substantially perpendicular to an extending direction of the pin gate,
And the first region extends in a direction substantially parallel to the extending direction of the active pillars. The method according to claim 1,
Wherein at least one of the semiconductor substrate and the second region is made of a material containing Si. The method according to claim 1,
Wherein the first region is made of one selected from SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BP and InN. The method according to claim 1,
When the first region is composed of a SiC layer,
Wherein the first region comprises a C low concentration SiC layer in which C is less than or equal to the stoichiometric ratio of SiC, a C high concentration SiC layer in which C is included in a stoichiometric ratio or more of SiC, and C is less than or equal to the stoichiometric ratio of SiC C low-concentration SiC layer. The method according to claim 1,
A P-type source formed on the active pillars on one side of the pin gate; And
And a P-type drain formed on the active pillars on the other side of the pin gate. The method according to claim 1,
Wherein the first region is configured to be exposed through an upper surface of the active pillar. 9. The method of claim 8,
In the case where the first semiconductor layer is composed of a SiC layer,
Wherein the first semiconductor layer is composed of a C low concentration SiC layer in which C is less than or equal to the stoichiometric ratio of SiC and a C high concentration SiC layer in which C is included in a stoichiometric ratio or more of SiC. 10. The method of claim 9,
Wherein the first semiconductor layer is structured such that a C high-concentration SiC is interposed between the C low-concentration Sic layers. An active filament including a channel region and a P-type source and drain located on both sides of the channel region;
A pin gate extending to cover an upper surface and a side surface of the channel region of the active pillars;
A gate insulating film interposed between the active pillars and the fin gate; And
And a variable resistor that is electrically extended with the drain,
The active pillar includes:
Inner region; And
And an outer region formed to surround at least one side of the inner region, wherein compress stress is generated at a junction interface between the inner region and the outer region. 12. The method of claim 11,
And the active region of the active region is made of a material having a lattice constant smaller than that of the second region. 13. The method of claim 12,
Wherein the inner region comprises one material selected from SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BP and InN,
And the outer region is configured to include a Si layer. Forming an active filament on the semiconductor substrate such that the internal material has a smaller lattice constant than the external material;
Forming a gate insulating film on a surface of the active pillars; And
And forming a pin gate on the gate insulating film so as to surround three sides of the active pillars. 15. The method of claim 14,
Wherein forming the active pillars comprises:
Forming a first semiconductor layer having a lattice constant smaller than that of the semiconductor substrate on the semiconductor substrate;
Patterning the first semiconductor layer and a portion of the semiconductor substrate to form a preliminary pillar; And
And forming a second semiconductor layer having a lattice constant substantially equal to that of the semiconductor substrate on the semiconductor substrate on which the preliminary pillar is formed. 16. The method of claim 15,
Wherein at least one of the semiconductor substrate and the second semiconductor layer includes a Si material. 17. The method of claim 16,
Wherein the first semiconductor layer and the second semiconductor layer are formed by an epitaxial growth method. 15. The method of claim 14,
Wherein the first semiconductor layer is made of one selected from SiC, AlN, GaN, ZnS, ZnO, ZnSe, CdS, BP and InN.

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