KR20150124499A - Semiconductor Device Having Fin Gate and Method of Manufacturing The Same - Google Patents

Abstract

The present technique relates to a semiconductor device having a fin gate capable of improving an operating current, and a method of manufacturing the same. The semiconductor device includes an active pillar which is formed in the upper part of a semiconductor substrate and comprises an internal region and an external region surrounding the internal region; and a fin gate which is extended along the upper side and lateral side of the active pillar. The internal region of the active pillar comprises a first semiconductor layer having a first lattice constant. The external region of the active pillar comprises a second semiconductor layer which has a second lattice constant which is smaller than the first lattice constant.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device having a pin gate structure, a resistance change memory device including the same,

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a pin gate structure, a resistance change memory device including the same, and a manufacturing method thereof.

With the rapid development of mobile and digital information communication and consumer electronics industries, it is expected that device research based on charge control of existing electron will be limited. Therefore, development of a novel functional memory device which is not a concept of an existing electronic charge device is required. In particular, in order to meet the demand for increasing the memory capacity of the main information equipment, it is necessary to develop a next-generation high-capacity super-high-speed and super-power memory device.

At present, a resistance change memory using a variable resistance material as a memory medium has been proposed as a next generation memory device, and typically includes a phase change memory device, a resistance memory, and a magnetoresistive memory.

The resistance change memory device has a basic configuration of an access element and a resistance element, and stores data of "0" or "1" according to the state of the resistance element.

However, improvement of integration density is also a top priority for such a resistance change memory device, and it is important to integrate the largest memory cell in a narrow area.

To meet this demand, the resistance change memory also employs a three-dimensional transistor structure. The three-dimensional transistor may include a three-dimensional vertical channel and a surrounding gate or a three-dimensional horizontal channel and a fin gate.

Since the three-dimensional transistor of the resistance change memory is also used as a switching element, it is required to provide a high operating current.

Embodiments of the present invention provide a semiconductor device having high operating current characteristics, a resistance change memory device including the same, and a method of manufacturing the same.

The semiconductor device according to the present invention includes: an active filament formed on a semiconductor substrate and composed of an inner region and an outer region surrounding the inner region; And a fin gate extending along an upper surface and a side surface of the active pillar, wherein an inner region of the active pillar is composed of a first semiconductor layer having a first lattice constant, And a second semiconductor layer having a second lattice constant smaller than the upper portion of the first lattice.

Also, the resistance change memory device according to an embodiment of the present invention includes: an active filament including a channel region and a source and a drain located on both sides of the channel region; A pin gate extending to cover an upper surface and a side surface of the channel region of the active pillars; A gate insulating film interposed between the active pillars and the fin gate; And a variable resistor electrically extended with the drain, wherein the active pillar includes: a first semiconductor layer; And a second semiconductor layer formed to surround the first semiconductor layer and inducing a tensile stress at a junction surface with the first semiconductor layer.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming an active filament on a semiconductor substrate, the active filament having a lattice constant larger than that of an external material; Forming a gate insulating film on a surface of the active pillars; And forming a pin gate on the gate insulating film so as to surround three sides of the active pillars.

According to the present invention, in the pillars having the inside and the outside, the inside where the channels are formed substantially can be made of a material having a larger lattice constant than the outside. Accordingly, as the tensile stress is applied to the inside of the pillar, the channel mobility of the NMOS transistor, that is, the current driving capability can be greatly increased.

In addition, the gate electric field is applied from the three surfaces of the channel by the use of the pin gate, and the operation characteristics of the MOS transistor can be further improved.

1A to 1D are cross-sectional views for explaining a method of manufacturing a semiconductor device having a pin gate according to an embodiment of the present invention.
2 is a perspective view of a semiconductor device having a fin gate fabricated in accordance with an embodiment of the present invention.
3A to 3E are cross-sectional views for explaining a method of manufacturing a semiconductor device having a pin gate according to another embodiment of the present invention.
4 is a perspective view of a semiconductor device having a pin gate according to another embodiment of the present invention.
5 is a perspective view of a resistance change memory device having a pin gate according to an embodiment of the present invention.
6 to 8 are perspective views showing a pillar of a semiconductor device having a pin gate according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

First, referring to FIG. 1A, a semiconductor substrate 100 is prepared. The semiconductor substrate 100 may be, for example, a Si substrate containing a first conductivity type impurity, for example, a p-type impurity. A first semiconductor layer 110 is deposited on the semiconductor substrate 100. The first semiconductor layer 110 may be made of a material having a lattice constant larger than that of the semiconductor substrate 100. [ The first semiconductor layer 110 of the present embodiment may be formed of a material such as SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlP, , CdSe, and CdTe can be used. The thickness of the first semiconductor layer 110 may be determined in consideration of the channel length, and may be, for example, monocrystalline grown by an epitaxial growth method. When the first semiconductor layer 110 is formed by the epitaxial growth method, the carrier mobility characteristics can be improved as compared with the case where the first semiconductor layer 110 is formed in the polycrystalline state.

Referring to FIG. 1B, the first semiconductor layer 110 and a part of the semiconductor substrate 100 are patterned to form a preliminary pillar P. Reference numeral 110a denotes a patterned first semiconductor layer and 100a denotes a patterned semiconductor substrate portion. The pre-pillar P of this embodiment may be a structure having a certain length, that is, a structure extending in a line shape.

Referring to FIG. 1C, a second semiconductor layer 122 is formed on a semiconductor substrate 100 on which a pre-filler P is formed. The second semiconductor layer 122 may be formed of the same material as the semiconductor substrate 100, for example, Si, and may be formed by an epitaxial growth method, for example.

Referring to FIG. 1D, a gate insulating layer 130 and a gate conductive layer are deposited on the second semiconductor layer 122. The gate insulating layer 130 may be formed by an oxidation process of the second semiconductor layer 122 or may include a metal oxide such as TaO, TiO, BaTiO, BaZrO, ZrO, HfO, LaO, AlO, YO, and ZrSi, Or the like. The gate conductor may be formed of a material selected from the group consisting of W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ta, Tisi, TaSi, TiW, TiON, TiAlON, WON, TaON, or a doped polysilicon film.

As shown in FIG. 2, a gate conductor is patterned in a substantial line shape so as to intersect with the active pillars P to form a fin gate 140. At the time of gate conductor patterning, the gate insulating film 130 can be patterned at the same time. Accordingly, the pin gate 140 can overlap the upper surface and both sides of the active pillar P. [

An impurity of a second conductivity type, for example, a high concentration n type impurity is implanted into the active pillars P on both sides of the pin gate 140, (S), and the drain (D) can be formed on the other side. The source S and drain D may be formed in a lightly doped drain (LDD) manner to reduce short channel effects such as gate-induced drain leakage (GIDL).

When implementing the resistance change memory, the bit line and the variable resistor can be formed in a known manner to be electrically connected to the drain D.

In the three-dimensional transistor having the pin gate 140, a semiconductor material having a lattice constant larger than that of the outside is embedded in the active pillars P in which channels are formed, Tensile stress due to difference in lattice constant occurs. If tensile stress is provided inside the active filament P, the electron mobility of the NMOS transistor having electrons as the main mobility can be greatly increased. As a result, the current driving capability of the NMOS transistor is improved.

3A to 3E, a method of manufacturing a semiconductor device having a pin gate according to another embodiment of the present invention will be described.

Referring to FIG. 3A, a semiconductor substrate 100 is prepared. The semiconductor substrate 100 may be, for example, a Si substrate containing a first conductivity type impurity, for example, a p-type impurity. A first semiconductor layer 110 and a second semiconductor layer 120 are sequentially stacked on a semiconductor substrate 100. The first semiconductor layer 110 may be made of a material having a lattice constant larger than that of the semiconductor substrate 100 or the second semiconductor layer 120. The first semiconductor layer 110 of the present embodiment may be formed of a material such as SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlP, , CdSe, and CdTe can be used. The thickness of the first semiconductor layer 110 may be determined in consideration of the channel length, and may be, for example, monocrystalline grown by an epitaxial growth method. When the first semiconductor layer 110 is formed by the epitaxial growth method, the carrier mobility characteristics can be improved as compared with the case where the first semiconductor layer 110 is formed in the polycrystalline state. The second semiconductor layer 120 may be formed of the same material as the semiconductor substrate 100, for example, Si.

Referring to FIG. 3B, the second semiconductor layer 120, the first semiconductor layer 110, and a part of the semiconductor substrate 100 are patterned to form the preliminary pillars P1. Reference numeral 120a denotes a patterned second semiconductor layer, 110a denotes a patterned first semiconductor layer, and 100a denotes a patterned semiconductor substrate portion. Here, the preliminary pillars P1 may be a line structure having a predetermined length.

Referring to FIG. 3C and FIG. 4, a third semiconductor layer 125 having a smaller lattice constant than the first semiconductor layer 110a is formed on the outer surface of the pre-pillar P1 (see FIG. 3B). For example, the third semiconductor layer 125 may be formed of Si, which is the same material as the semiconductor substrate 100 and the second semiconductor layer 120a. In addition, the third semiconductor layer 125 may be formed using an epitaxial growth method. According to the formation of the third semiconductor layer 125, the first semiconductor layer 110a is made of a semiconductor material having a lattice constant smaller than that of the first semiconductor layer 110a, for example, a Si material, It can be surrounded. Thereby, the active pillars P on which the three-dimensional transistors are to be formed can be formed.

Referring to FIG. 3D, the active pillars P and the exposed surface of the semiconductor substrate 100 are oxidized to form a gate insulating film 130. Although the gate insulating film 130 of this embodiment is formed by the oxidation method, the gate insulating film 130 can be formed by an evaporation method without limitation. When the gate insulating film 130 is formed by a deposition method, a metal oxide such as TaO, TiO, BaTiO, BaZrO, ZrO, HfO, LaO, AlO, YO and ZrSi, a nitride or a composite film thereof may be used. In some cases, the gate insulating film 130 may be formed thicker than the surface of the active pillars P.

3E and 4, a gate conductor may be deposited over the structure of the semiconductor substrate 100 on which the active pillars P are formed. The gate conductor may be formed of a material selected from the group consisting of W, Cu, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ta, Tisi, TaSi, TiW, TiON, TiAlON, WON, TaON, or a doped polysilicon film.

Next, the gate conductor may be patterned in a predetermined pattern to form the pin gate 140. The pin gate 140 may be formed to overlap with the top surface and the side surface of the active pillar P coated with a gate insulating film (not shown), as shown in FIG.

Thereafter, the source S, the drain D, the variable resistor Rv, and the bit line BL are formed in a well-known manner to fabricate a resistance change memory including a semiconductor device.

The present invention is not limited to the above embodiments.

6, the first semiconductor layer 110a of the preliminary filer P1 includes a first sub-semiconductor layer 110-1, a second sub-semiconductor layer 110-2, and a third sub- 110-3. At this time, when the first semiconductor layer 110a is made of SiGe, the first sub semiconductor layer 110-1 and the third sub semiconductor layer 110-3 are formed such that Ge is included in a proportion of less than the stoichiometric ratio of SiGe Si Ge layer (hereinafter referred to as a Ge low-concentration SiGe layer), and the second sub semiconductor layer 110-2 may be a SiGe layer (hereinafter referred to as Ge high-concentration SiGe layer) in which Ge is contained in a stoichiometric ratio of SiGe or more. The SiGe layer has a tendency to increase the lattice constant when the content of Ge is increased. Therefore, since the material having the largest lattice constant is formed in the substantial effective channel zone among the first semiconductor layer 110a, the electron mobility in the channel can be maximized.

7, the active pillars P may be configured to expose the upper surface of the first semiconductor layer 112. [ Accordingly, the pin gate 140 and the first semiconductor layer 112 may overlap with each other with a gate insulating film (not shown) therebetween.

8, when the upper surface of the first semiconductor layer 112 is the upper surface of the active pillar P, the first semiconductor layer 112 is formed of the stacked Ge low-concentration SiGe layer 112- 1) and a Ge high-concentration SiGe layer 112-2.

According to the present embodiment, in the pillars having the inside and the outside, the inside can be made of a material having a larger lattice constant than the outside. Accordingly, as the tensile stress is applied to the inside of the pillar, the channel mobility of the NMOS transistor, that is, the current driving capability can be greatly increased.

In addition, the gate electric field is applied from the three surfaces of the channel by using the pin gate, and the operation characteristics of the MOS transistor can be further improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but variations and modifications may be made without departing from the scope of the present invention. Do.

100: semiconductor substrate 110, 110a: first semiconductor layer
120, 120a: second semiconductor layer 125: third semiconductor layer
140: pin gate

Claims (18)

An active filament formed on the semiconductor substrate and comprising an inner region and an outer region surrounding the inner region; And
And a fin gate extending to overlap the top and side surfaces of the active pillars,
Wherein the active region of the active pillar is composed of a first semiconductor layer having a first lattice constant,
And an outer region of the active pillar is formed of a second semiconductor layer having a second lattice constant smaller than that of the first lattice upper portion. The method according to claim 1,
And a gate insulating film interposed between the active pillar and the pin gate. The method according to claim 1,
The active pillars extend in a direction substantially perpendicular to an extending direction of the pin gate,
And the internal region extends in a direction substantially parallel to the extending direction of the active pillars. The method according to claim 1,
Wherein at least one of the semiconductor substrate and the outer region is made of a material containing Si. 5. The method of claim 4,
The first semiconductor layer may be formed of one selected from SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlP, AlAs, AlSb, CdS, CdSe, and CdTe . 6. The method of claim 5,
When the first semiconductor layer is composed of a SiGe layer,
Wherein the first semiconductor layer comprises: a Ge low-concentration SiGe layer in which Ge is included at a stoichiometric ratio of SiGe or less; a Ge high-concentration SiGe layer in which the Ge is contained at a stoichiometric ratio of SiGe or higher; and the Ge is a stoichiometric ratio And a Ge low-concentration SiGe layer which is included as a low-concentration SiGe layer. The method according to claim 1,
A source formed in the active pillar on one side of the pin gate,
And a drain formed on the active pillar on the other side of the pin gate. The method according to claim 1,
Wherein the first semiconductor layer is configured to be exposed through an upper surface of the active pillar. 9. The method of claim 8,
When the first semiconductor layer is composed of a SiGe layer,
Wherein the first semiconductor layer is formed by laminating a Ge low-concentration SiGe layer containing Ge at a stoichiometric ratio of SiGe or less and a Ge high-concentration SiGe layer containing Ge at a stoichiometric ratio of SiGe or higher. An active pillar comprising a channel region and source and drain located on both sides of the channel region;
A pin gate extending to cover an upper surface and a side surface of the channel region of the active pillars;
A gate insulating film interposed between the active pillars and the fin gate; And
And a variable resistor that is electrically extended with the drain,
The active pillar includes:
A first semiconductor layer; And
And a second semiconductor layer formed to surround the first semiconductor layer and causing a tensile stress at a junction interface with the first semiconductor layer. 11. The method of claim 10,
Wherein the first semiconductor layer is a material having a lattice constant larger than that of the second semiconductor layer. 12. The method of claim 11,
The first semiconductor layer may include one selected from the group consisting of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlP, AlAs, AlSb, CdS, CdSe, Of the resistance change memory device. 13. The method of claim 12,
Wherein the second semiconductor layer comprises a Si material. Forming an active filament on the semiconductor substrate such that the internal material has a larger lattice constant than the external material;
Forming a gate insulating film on a surface of the active pillars; And
And forming a pin gate on the gate insulating film so as to surround three sides of the active pillars. 15. The method of claim 14,
Wherein forming the active pillars comprises:
Forming a first semiconductor layer having a lattice constant larger than that of the semiconductor substrate on the semiconductor substrate;
Patterning the first semiconductor layer and a portion of the semiconductor substrate to form a preliminary pillar; And
And forming a second semiconductor layer having a lattice constant substantially equal to that of the semiconductor substrate on the semiconductor substrate on which the preliminary pillar is formed. 16. The method of claim 15,
Wherein at least one of the semiconductor substrate and the second semiconductor layer includes a Si material. 17. The method of claim 16,
Wherein the first semiconductor layer and the second semiconductor layer are formed by an epitaxial growth method. 16. The method of claim 15,
The first semiconductor layer may be formed of one selected from SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlP, AlAs, AlSb, CdS, CdSe, and CdTe Wherein the method comprises the steps of:

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