CN117476742A - 超结mosfet的终端结构 - Google Patents

超结mosfet的终端结构 Download PDF

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CN117476742A
CN117476742A CN202311278165.0A CN202311278165A CN117476742A CN 117476742 A CN117476742 A CN 117476742A CN 202311278165 A CN202311278165 A CN 202311278165A CN 117476742 A CN117476742 A CN 117476742A
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李东升
马彪
高伟
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Shanghai Lanxin Semiconductor Co ltd
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Abstract

本发明公开了一种超结MOSFET的终端结构，所述的终端结构包含超结结构区和终端引出区；所述的超结结构区包含交替排列的P/N薄层，其中P薄层形成P柱；P型外延层的厚度决定了P柱的深度；所述的超结结构区的表面覆盖一层绝缘介质层，所述绝缘介质层同时延伸覆盖至所述终端引出区的P型外延层表面；所述终端结构的终端引出区，P型外延层中包含有重掺杂P型注入区，形成P型引出区；所述终端引出区的表面覆盖金属层，所述金属层通过所述终端引出区表面的绝缘介质层的开口与所述重掺杂P型注入区接触形成引出。

Description

超结MOSFET的终端结构
技术领域
本发明涉及半导体器件及工艺制造领域，特别是涉及一种基于碳化硅衬底的超结MOSFET的终端结构。
背景技术
MOSFET（Metal Oxide Semiconductor Field Effect Transistor-金属氧化物半导体场效应晶体管）是一种半导体器件，广泛用于开关目的和电子设备中电子信号的放大。由于MOSFET的尺寸非常小，因此MOSFET既可以是核心也可以是集成电路，可以在单个芯片中进行设计和制造。MOSFET器件的引入带来了电子开关领域的变化。
MOSFET是具有源极（Source）、栅极（Gate）、漏极（Drain）和主体（Body）端子的四端子设备。通常，MOSFET的主体与源极端子连接，从而形成诸如场效应晶体管的三端子器件。
超级结功率器件是一种新型功率半导体器件。它是在双扩散金属氧化物半导体（DMOS）的基础上，通过引入超结（Super Junction）结构，具备DMOS输入阻抗高、开关速度快、工作频率高、热稳定好、驱动电路简单、易于集成等特点。超结结构是利用一系列的交替排列的P型和N型半导体薄层来在截止状态下、在较低电压下就将由P型和N型半导体薄层（柱状区域Pillar）组成的P型、N型区耗尽,实现电荷相互补偿。该薄层中P型杂质的载流子分布和N型杂质的载流子分布以及它们的匹配会影响器件的特性包括其反向击穿电压和电流处理能力。交替的P/N薄层达到最佳的电荷平衡以得到器件的最大的反向击穿电压。因此，超结器件是一种利用PN电荷平衡的体内Resurf技术来提升器件反向击穿电压BV的同时又保持较小的导通电阻的MOSFET结构。Resurf原理是利用器件中电场分布的二维效应，当垂直方向的P衬底/N外延结附近电场尚未达到临界电场时，由于其和横向N外延/P阱结的作用，即利用横向结和纵向结的相互作用使外延层在横向结达到临界雪崩击穿电场之前就完全耗尽，通过合理优化器件参数让器件的击穿发生在纵向结，从而起到降低表面电场的作用。
在MOSFET结构中，超结结构即可以用在器件的元胞区，也可以用在终端区。
碳化硅（SiC）是一种新型的宽禁带半导体材料，具有高温、高压、高频等优异的特性，逐渐成为下一代功率电子器件的研究热点之一。碳化硅具有宽的带隙、高的熔点、低的介电常数、高的击穿场强、高的导热系数和高的饱和电子漂移速度。这些特性使碳化硅制成的器件有可能在更高的温度、更高工作频率及更高的功率级别以及其他一些由其他半导体材料制成的器件无法工作的情况下工作。在保证器件性能的情况下，尽量缩小MOSFET器件元胞尺寸是业界努力发展的方向。不同厂商的MOSFET的工艺及结构不断的在进步，产品性能也在不断的提高。为了匹配不同的SiC MOSFET元胞工艺，目前行业内常用的终端有场限环结构、结终端扩展结构，也需要一种特别的终端结构来匹配特有的元胞结构。
发明内容
本发明所要解决的技术问题在于提供一种超结MOSFET的终端结构，具有更高的性能及可靠性。
为解决上述问题，本发明所述的超结MOSFET的终端结构，包含：
所述的超结MOSFET形成于一半导体衬底上的外延层中，所述的外延层包含下层的N型外延层和位于N型外延层之上的P型外延层；
所述的终端结构位于所述超结MOSFET的元胞结构的外围，对所述超结MOSFET的元胞结构进行隔离保护；
所述的终端结构包含超结结构区和终端引出区；所述的超结结构区包含交替排列的P/N薄层，其中P薄层形成P柱；P型外延层的厚度决定了P柱的深度；
所述的超结结构区的表面覆盖一层绝缘介质层，所述绝缘介质层同时延伸覆盖至所述终端引出区的P型外延层表面；
所述终端结构的终端引出区，P型外延层中包含有重掺杂P型注入区，形成P型引出区；所述终端引出区的表面覆盖金属层，所述金属层通过所述终端引出区表面的绝缘介质层的开口与所述重掺杂P型注入区接触形成引出。
进一步地，所述的半导体衬底及外延层包含碳化硅衬底或氮化镓衬底、锗硅衬底；所述外延层掺杂浓度为8E15～1E16CM-3；所述N型外延层的厚度为3～9um，所述P型外延层的厚度为3～7um；所述N型外延层与P型外延层的合并总厚度为10～12um。
进一步地，所述的超结结构区中，N型薄层由P型外延层进行N型离子注入反型得到，反型区之外的P型外延层形成P柱；所述的P型外延层的厚度根据N型杂质的注入深度来确定，当N型杂质的注入深度越深，P型外延层的厚度随之变厚，N型杂质的注入深度决定了P柱的深度。
进一步地，所述的N型外延层和P型外延层的浓度为一致的，或者是多层不同掺杂浓度或渐变掺杂浓度的P型外延层。
进一步地，所述的超结结构区的P型外延表面是通过衬底刻蚀工艺将其表面刻蚀掉0.5～1.5um，使其上表面低于终端引出区。
进一步地，所述的重掺杂P型注入区为所述超结MOSFET的元胞结构的P型重掺杂注入时同步注入形成。
进一步地，所述的绝缘介质层为氧化硅层。
进一步地，所述的超结结构区的形成工艺中，注入N型杂质的注入能量为4～10MeV；最大注入能量由离子注入机的最高注入能量来决定，为形成更深的P柱，采用原子量更轻的N型杂质进行注入。
进一步地，所述的注入的N型杂质为氮。
本发明所述的超结MOSFET的终端结构，由N型外延层和P型外延层组成，包含终端引出区和超结结构区；终端引出区的P型注入区与元胞区域的重掺杂P型注入同步形成；超结结构区P型外延层厚度根据N型杂质离子的注入深度而定，通过对P型外延层反型来形成P/N交替的超结结构，相对具有更深的P柱。
附图说明
图1 是本发明所述的超结MOSFET的终端结构的剖面示意图，包含左侧的终端引出区以及右侧的P/N交替的超结结构区。
1是衬底，2是N型外延层，3是P柱，4是N型注入区（反型区），5是P型外延层，6是重掺杂P型注入区，7是金属层，8是绝缘介质层。
实施方式
以下结合附图给出本发明的具体实施方式，对本发明中的技术方案进行清楚、完整的描述，但本发明不限于以下的实施方式。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用于方便、明晰地辅助说明本发明实施例的目的。本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大，自始至终相同附图标记表示相同的元件。在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
本发明所述的超结MOSFET的终端结构，为了匹配特有的元胞结构，设计了特别的终端结构和工艺流程来匹配。所述终端结构位于超结MOSFET元胞结构的外围（本发明附图中并未显示元胞结构区域），终端结构能起到隔离保护元胞结构、调节边缘电场提高器件耐压能力的作用。本发明所述的终端结构形成于一半导体衬底上的外延层中，所述的外延层包含下层的N型外延层和位于N型外延层之上的P型外延层，如图1所示。所述的半导体衬底及外延层包含碳化硅衬底或氮化镓衬底、锗硅衬底；以碳化硅衬底为例，所述外延层掺杂浓度为8E15～1E16CM-3；所述N型外延层的厚度为3～9um，所述P型外延层的厚度为3～7um；所述N型外延层与P型外延层的合并总厚度为10～12um。
所述的终端结构包含右侧的超结结构区和图中左侧的终端引出区。所述的超结结构区包含P/N交替排列的薄层，其中P薄层形成P柱；P型外延层的厚度决定了P柱的深度。
所述的超结结构区的表面覆盖一层绝缘介质层，比如氧化硅层。所述绝缘介质层同时延伸覆盖至所述终端引出区的P型外延层表面。
所述终端结构的终端引出区，P型外延层中包含有重掺杂P型注入区，形成P型引出区；所述终端引出区的表面覆盖金属层，所述金属层通过所述终端引出区表面的绝缘介质层的开口与所述重掺杂P型注入区接触形成引出。P型的终端引出区是与元胞结构区的P+注入同步注入形成，不额外增加工艺。
所述的超结结构区中，N型薄层由P型外延层进行N型离子注入反型得到，反型区之外的P型外延层形成P柱；所述的P型外延层的厚度根据N型杂质的注入深度来确定，当N型杂质的注入深度越深，P型外延层的厚度随之变厚，N型杂质的注入深度决定了P柱的深度。
采用交替的P/N 柱形成超结结构。传统的超结结构形成工艺一般是在N型外延层中刻蚀形成多个平行且等间距的深沟槽，然后在所述深沟槽内填充P型外延层，多个P型外延层和他们之间的N型外延层构成P/N交替排列的超结结构。另一种方式是离子注入法，在N型外延层中通过大量的P型离子注入形成柱状的P型注入区，直接形成P柱，与N型外延层之间形成超结结构。
本发明终端结构的超结结构采用离子注入法，本发明在P型外延层中注入大量且轻量化的N型杂质使注入区的P型外延层杂质反型为N型，与原有的非注入区的P型外延层之间形成P/N交替排列的超结结构，间接形成P柱。P型和N型的电荷平衡通过柱形的N型高能注入的窗口CD和窗口间距Space来匹配。
终端P柱和N柱形成的交替结构的尺寸(pitch)可以同原胞pitch尺寸相同，也可以和pitch尺寸不同，大小可以根据需要灵活调整。P柱和+N柱尺寸范围1.0～3.0um，终端不同尺寸的P柱和N柱可以通过N型注入的窗口调整来实现所需要的P柱和N柱的电荷平衡。
元胞pitch结构及工艺在沟道区(顶部0～1.0um区域)没有注入 N柱，因此本发明在终端区域进行SiC衬底的刻蚀工艺，是将超结结构区域的表面向下刻蚀，刻蚀深度0.5～1.5um(如图1中的虚线箭头所示)，该步骤可以通过元胞结构区的沟槽刻蚀工艺同步形成，也无需增加额外的工艺步骤。
本发明超级结终端结构形成在N型和P型两种外延层结构基础之上，N型外延层厚度3～9um，在SiC的 N型外延层上再外延一层 3～7um P型外延层(掺杂铝(AL))，此外延层厚度根据N型(氮N)注入深度来确定，按照实验数据，4MeV注入能量下氮注入深度近似3um，10Mev 氮注入近似7um）；对于1200V SiC MOSFET，N型外延层+P型外延层，两层外延叠加后10～12um）；对于750V SiC MOSFET，N型外延层+P型外延层，两层外延叠加后6～8um）。
P型外延层中P柱（外延过程通过掺杂Al实现）的深度, 取决于N型杂质的注入深度，即离子注入机的最高注入能量下N型杂质的注入深度，因此本发明限定的P型外延层厚度取决于该离子注入机的能量， P型外延层厚度3～7um范围是在10Mev注入能量下取得的，如果离子注入机能量更高，该P型外延层可以相应的更厚。另外，采用原子量更小的N型杂质进行注入能在同等注入能量下达到更深的注入深度，以相对实现更深的P柱，比如采用氮离子注入。
该终端的超结Pillar形成过程和元胞区域同时形成，该终端区域的表面碳化硅刻蚀在元胞区域栅极沟槽刻蚀工艺过程中同步形成，牺牲氧化层和栅极氧化+淀积多晶硅后，把终端的多晶硅刻蚀掉即可。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

1.一种超结MOSFET的终端结构，其特征在于：包含：
所述的超结MOSFET形成于一半导体衬底上的外延层中，所述的外延层包含下层的N型外延层和位于N型外延层之上的P型外延层；
所述的终端结构位于所述超结MOSFET的元胞结构的外围，对所述的超结MOSFET的元胞结构进行隔离保护；
所述的终端结构包含超结结构区和终端引出区；所述的超结结构区中包含交替排列的P/N薄层，其中P薄层形成P柱；P型外延层的厚度决定了P柱的深度；
所述超结结构区域的表面覆盖一层绝缘介质层，所述绝缘介质层同时延伸覆盖至所述终端引出区的P型外延层表面；
所述终端结构的终端引出区，P型外延层中包含有重掺杂P型注入区，形成P型引出区；所述终端引出区的表面覆盖金属层，所述金属层通过所述终端引出区表面的绝缘介质层的开口与所述重掺杂P型注入区接触形成引出。
2.如权利要求1所述的超结MOSFET的终端结构，其特征在于：所述的半导体衬底及外延层包含碳化硅衬底或氮化镓衬底、锗硅衬底；所述外延层掺杂浓度为8E15～1E16CM-3；所述N型外延层的厚度为3～9um，所述P型外延层的厚度为3～7um；所述N型外延层与P型外延层的合并总厚度为10～12um。
3.如权利要求2所述的超结MOSFET的终端结构，其特征在于：所述的超结结构中，N型薄层由P型外延层进行N型离子注入反型得到，反型区之外的P型外延层形成P柱；所述的P型外延层的厚度根据N型杂质的注入深度来确定，当N型杂质的注入深度越深，P型外延层的厚度随之变厚，N型杂质的注入深度决定了P柱的深度。
4.如权利要求1所述的超结MOSFET的终端结构，其特征在于：所述的N型外延层和P型外延层的浓度为一致的，或者是多层不同掺杂浓度或渐变掺杂浓度的P型外延层。
5.如权利要求1所述的超结MOSFET元胞结构的工艺方法，其特征在于：所述的超结结构的区域的P型外延表面是通过衬底刻蚀工艺将其表面刻蚀掉0.5～1.5um，使其上表面低于终端引出区。
6.如权利要求1所述的超结MOSFET的终端结构，其特征在于：所述的重掺杂P型注入区为所述超结MOSFET的元胞结构的P型重掺杂注入时同步注入形成。
7.如权利要求1所述的超结MOSFET的终端结构，其特征在于：所述的绝缘介质层为氧化硅层。
8.如权利要求3所述的超结MOSFET的终端结构，其特征在于：所述的超结结构形成工艺中，注入N型杂质的注入能量为4～10MeV；最大注入能量由离子注入机的最高注入能量来决定，为形成更深的P柱，采用原子量更轻的N型杂质进行注入。
9.如权利要求8所述的超结MOSFET的终端结构，其特征在于：所述的N型杂质为氮。
10.如权利要求1所述的超结MOSFET的终端结构，其特征在于：所述的超结结构区中，P柱和N柱形成的交替结构，相邻的P柱之间的尺寸是与元胞区的元胞尺寸相同，或者是与元胞区的元胞尺寸不同。
11.如权利要求10所述的超结MOSFET的终端结构，其特征在于：所述的通过超结结构中， P型和N型的电荷平衡通过柱形的N型高能注入的窗口CD值和窗口之间的间距来匹配，但需要实现P柱和N柱的电荷平衡。
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