CN117476668A - Array substrate, preparation method of array substrate and display device - Google Patents

Array substrate, preparation method of array substrate and display device Download PDF

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Publication number
CN117476668A
CN117476668A CN202310265253.0A CN202310265253A CN117476668A CN 117476668 A CN117476668 A CN 117476668A CN 202310265253 A CN202310265253 A CN 202310265253A CN 117476668 A CN117476668 A CN 117476668A
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electrode
layer
substrate
thin film
film transistor
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马倩
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202310265253.0A priority Critical patent/CN117476668A/en
Publication of CN117476668A publication Critical patent/CN117476668A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application provides an array substrate, a preparation method of the array substrate and a display device. The array substrate comprises a substrate, a first thin film transistor arranged on the substrate and a second thin film transistor arranged on the substrate and adjacent to the first thin film transistor. The first thin film transistor comprises a first grid electrode, a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode are positioned on one side, away from the substrate, of the first grid electrode. The second thin film transistor comprises a second grid electrode, a second source electrode and a second drain electrode, wherein the second source electrode and the second drain electrode are positioned on one side, close to the substrate, of the second grid electrode. The second source electrode, the second drain electrode and the first grid electrode are arranged in the same layer, and the second grid electrode, the first source electrode and the first drain electrode are arranged in the same layer. The array substrate provided by the application can simplify the arrangement of the film layer and save the process.

Description

Array substrate, preparation method of array substrate and display device
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
In recent years, LTPO (Low Temperature Polycrystalline Oxide, low temperature poly oxide) technology of combining a low temperature poly silicon thin film transistor and an oxide thin film transistor in the same pixel circuit has been developed, and an array substrate based on the LTPO technology is an LTPO substrate. Because the LTPO substrate comprises the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor, the low-temperature polycrystalline silicon thin film transistor has the advantages of low power consumption and low leakage current of the oxide thin film transistor, and low power consumption and high quality display can be realized.
However, the LTPO substrate has more layers, and the process is complicated, resulting in high process cost, and being unfavorable for realizing the light and thin display device. Therefore, the film structure of the LTPO substrate is to be optimized.
Disclosure of Invention
The embodiment of the application provides an array substrate, a preparation method of the array substrate and a display device, which can simplify the arrangement of a film layer and save the process.
The embodiment of the application provides an array substrate, which comprises:
a substrate;
the first thin film transistor is arranged on the substrate and comprises a first grid electrode, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on one side, far away from the substrate, of the first grid electrode; and
the second thin film transistor is arranged on the substrate and is adjacent to the first thin film transistor, the second thin film transistor comprises a second grid electrode, a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are positioned on one side, close to the substrate, of the second grid electrode;
the second source electrode, the second drain electrode and the first grid electrode are arranged in the same layer, and the second grid electrode, the first source electrode and the first drain electrode are arranged in the same layer.
Optionally, in some embodiments of the present application, the first drain includes a first drain extension, the second source includes a second source extension, an orthographic projection of the second source extension on a plane on which the first drain extension is located overlaps the first drain extension, and the second source extension is connected to the first drain extension by a portion opposite to the first drain extension.
Optionally, in some embodiments of the present application, the array substrate further includes a static eliminating layer and a first active layer, where the static eliminating layer is disposed on the same layer, the first active layer is disposed between the first gate and the substrate, an orthographic projection of the second source extending portion on a plane where the static eliminating layer is disposed overlaps the static eliminating layer, a first via hole is disposed between the first drain extending portion and the second source extending portion, the first drain extending portion extends into the first via hole and is connected with the second source extending portion, a second via hole is disposed between the second source extending portion and the static eliminating layer, and the second source extending portion extends into the second via hole and is connected with the static eliminating layer.
Optionally, in some embodiments of the present application, the array substrate further includes a static eliminating layer and a second active layer disposed on the same layer, the second active layer is disposed between the second gate and the second source and the second drain, an orthographic projection of the first drain extension portion on a plane where the static eliminating layer is located overlaps the static eliminating layer, a first via hole is disposed between the first drain extension portion and the static eliminating layer, the first drain extension portion extends into the first via hole and is connected with the static eliminating layer, a second via hole is disposed between the second source extension portion and the static eliminating layer, and the static eliminating layer extends into the second via hole and is connected with the second source extension portion.
Optionally, in some embodiments of the present application, the first via and the second via are a set of holes.
Optionally, in some embodiments of the present application, the first thin film transistor further includes a third gate, and the third gate is located on a side of the first gate away from the substrate or on a side of the first gate close to the substrate.
Optionally, in some embodiments of the present application, the array substrate includes a capacitive dielectric layer, where the capacitive dielectric layer is disposed between the first gate and the third gate, and a material of the capacitive dielectric layer includes one or more of alumina, chromia, or titania.
Optionally, in some embodiments of the present application, the first thin film transistor further includes a first active layer, and a material of the first active layer includes polysilicon; the second thin film transistor further includes a second active layer, and a material of the second active layer includes a metal oxide semiconductor.
Correspondingly, the embodiment of the application also provides a preparation method of the array substrate, which comprises the following steps:
providing a substrate;
forming a first thin film transistor on one side of the substrate, wherein the first thin film transistor comprises a first grid electrode, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on one side of the first grid electrode away from the substrate;
forming a second thin film transistor on one side of the substrate, wherein the second thin film transistor is adjacent to the first thin film transistor, the second thin film transistor comprises a second grid electrode, a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are positioned on one side, close to the substrate, of the second grid electrode;
the second source electrode, the second drain electrode and the first grid electrode are arranged in the same layer, and the second grid electrode, the first source electrode and the first drain electrode are arranged in the same layer.
Correspondingly, the embodiment of the application also provides a display device, which comprises the array substrate described in the embodiment.
According to the array substrate, the preparation method of the array substrate and the display device, the source and the drain of the second thin film transistor are arranged on the same layer as the first grid of the first thin film transistor, and the grid of the second thin film transistor is arranged on the same layer as the source and the drain of the first thin film transistor, so that one metal layer in the array substrate is reduced, one photomask is saved, one insulating layer is correspondingly reduced, the film structure of the array substrate is simplified, and the process is saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a related art array substrate.
Fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an array substrate according to another embodiment of the present application.
Fig. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
The embodiment of the application provides an array substrate, a preparation method of the array substrate and a display device. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an array substrate in the related art. The whole film structure of the array substrate comprises four metal layers and five insulating layers.
Specifically, the array substrate 100 includes a substrate 10, a first thin film transistor 20, a second thin film transistor 30, and a signal trace 40. The substrate 10 includes a first flexible substrate 11, a buffer layer 12, a second flexible substrate 13, a first barrier layer 14, a second barrier layer 15, and a barrier layer 16, which are stacked, and a static-eliminating layer 17 between the first barrier layer 14 and the second barrier layer 15. The first thin film transistor 20 is disposed at one side of the substrate 10. The first thin film transistor 20 includes a first active layer 21, a first insulating layer 22, a first gate electrode 23, a second insulating layer 24, a third gate electrode 25, a first source electrode 26, and a first drain electrode 27, which are sequentially stacked. The second thin film transistor 30 is disposed on a side of the first thin film transistor 20 remote from the substrate 10. The second thin film transistor 30 includes a light shielding layer 31, a third insulating layer 32, a second gate electrode 33, a fourth insulating layer 34, a second active layer 35, a fifth insulating layer 36, a second source electrode 37, and a second drain electrode 38, which are stacked in this order.
Referring to fig. 2, an array substrate 100 is provided according to an embodiment of the present application, and includes a substrate 10, a first thin film transistor 20, and a second thin film transistor 30.
The first thin film transistor 20 is disposed at one side of the substrate 10. The first thin film transistor 20 includes a first active layer 21, a first insulating layer 22, a first gate electrode 23, a second insulating layer 24, a first source electrode 25, and a first drain electrode 26, which are sequentially stacked.
The second thin film transistor 30 is disposed on the substrate 10 and adjacent to the first thin film transistor 20. The second thin film transistor 30 includes a second source electrode 31, a second drain electrode 32, a third insulating layer 33, a second active layer 34, a fourth insulating layer 35, and a second gate electrode 36, which are sequentially stacked. Wherein the second source 31, the second drain 32 and the first gate 23 are arranged in the same layer, and the second gate 36 is arranged in the same layer as the first source 25 and the first drain 26.
The array substrate provided by the embodiment of the application is characterized in that the source and the drain of the second thin film transistor are arranged on the same layer with the first grid electrode of the first thin film transistor, and the grid electrode of the second thin film transistor is arranged on the same layer with the source and the drain of the first thin film transistor, so that the film structure of the array substrate is simplified into three metal layers and four insulating layers, the arrangement of one metal layer in the array substrate is reduced, one photomask is saved, the arrangement of one insulating layer is correspondingly reduced, the film structure of the array substrate is simplified, and the technological process is saved.
With continued reference to fig. 2, in the present embodiment, the first thin film transistor 20 further includes a third gate 27, and the third gate 27 is located on a side of the first gate 23 near the substrate 10. The first gate 23 and the third gate 27 may form a storage capacitor to improve the stability of the gate potential. In other words, the first thin film transistor 20 is a dual-gate transistor, and the second source 31 and the second drain 32 are disposed on the same layer as the upper gate of the dual-gate transistor.
It should be noted that, in other embodiments of the present application, the third gate 27 may also be located on a side of the first gate 23 away from the substrate 10, in other words, the first thin film transistor 20 is a dual gate transistor, and the second source 31, the second drain 32 and the gate of the dual gate transistor are disposed on the same layer, which is not limited in this application.
In this embodiment, the first drain 26 further includes a first drain extension 28, and the second source 31 further includes a second source extension 37. There is a facing portion between the second source extension 37 and the first drain extension 28, specifically, the orthographic projection of the second source extension 37 on the plane of the first drain extension 28 overlaps with the first drain extension 28. At this time, the second source extension 37 and the first drain extension 28 are connected by the portions facing each other. It will be appreciated that such an arrangement saves design space and is beneficial for reducing the size of the array substrate.
In particular, the substrate 10 may be a flexible substrate. In the present embodiment, the substrate 10 includes a first flexible substrate 11, a buffer layer 12, a second flexible substrate 13, a first barrier layer 14, a second barrier layer 15, and a barrier layer 16, which are stacked. Of course, the substrate may be a rigid substrate such as glass, and the present application is not limited thereto.
The material of the first active layer 21 may be polysilicon or other materials, which is not limited in this application.
The materials of the first insulating layer 22 and the second insulating layer 24 may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. Of course, the first insulating layer 22 and the second insulating layer 24 may be made of other materials, which is not limited herein. The thickness of the first insulating layer 22 and the second insulating layer 24 may be 1000 to 3000 angstroms.
Note that, when the first thin film transistor 20 is a low temperature polysilicon thin film transistor, the material of the first insulating layer 22 may be silicon nitride. Because a large amount of ammonia (NH) is added during the formation of the silicon nitride layer 3 ) A large amount of hydrogen bonds are generated while forming silicon nitride, so that the hydrogen defect in the first active layer 21 (polysilicon layer) can be sufficiently repaired, and the leakage problem of the low-temperature polysilicon thin film transistor is effectively reduced.
When the second thin film transistor 30 is an oxide thin film transistor, since the active layer of the oxide thin film transistor is susceptible to hydrogen, the material of the second insulating layer 24 may be silicon oxide without hydrogen, and at this time, the second active layer 34 of the second thin film transistor 30 disposed on the side of the second insulating layer 24 away from the substrate 10 may be prevented from being affected by hydrogen to some extent, thereby improving the reliability of the second thin film transistor 30.
The materials of the first gate electrode 23, the third gate electrode 27, the second source electrode 31, and the second drain electrode 32 may include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The thicknesses of the first gate electrode 23, the third gate electrode 27, the second source electrode 31, and the second drain electrode 32 may be 2000 to 8000 angstroms.
In this embodiment, the orthographic projection of the second source 31 on the substrate 10 also covers the orthographic projection of the second gate 36 on the substrate 10, which can play a role of shading.
The material of the third insulating layer 33 may include silicon nitride, silicon oxide, or an organic material. The thickness of the third insulating layer 33 may be 2000 to 10000 angstroms.
The material of the second active layer 34 may include one or more of metal oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), indium tin zinc oxide (IZTO), or Indium Gallium Zinc Tin Oxide (IGZTO). Of course, the second active layer 34 may be other materials, which is not limited in this application. The thickness of the second active layer 34 may be 100 to 1000 angstroms.
The material of the fourth insulating layer 35 may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. Of course, the fourth insulating layer 35 may be made of other materials, which is not limited in this application. The thickness of the fourth insulating layer 35 may be 1000 to 3000 angstroms.
The material of the first source electrode 25, the first drain electrode 26, and the second gate electrode 36 may include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). In this embodiment, the thicknesses of the first source electrode 25, the first drain electrode 26, and the second gate electrode 36 may be 2000 to 8000 angstroms.
With continued reference to fig. 2, the array substrate 100 provided in the embodiment of the present application further includes a static-removing layer 40. Since the array substrate needs to be rigidly supported during fabrication, the array substrate is typically fabricated on a rigid substrate, and if the array substrate needs to be peeled off from the rigid substrate after the fabrication of the array substrate is completed, static electricity may be generated during the peeling, and damage may be caused to the array substrate. The static electricity removing layer 40 is arranged, so that static electricity during stripping can be prevented from affecting the array substrate, and the quality of the array substrate is improved.
In this embodiment, the static eliminating layer 40 and the first active layer 21 are disposed on the same layer, and the orthographic projection of the second source extension 37 on the plane of the static eliminating layer 40 overlaps with the static eliminating layer 40, in other words, there is a facing portion between the second source extension 37 and the static eliminating layer 40. A first via hole 50 is formed between the first drain extension portion 28 and the second source extension portion 37, the first drain extension portion 28 extends into the first via hole 50 to be connected with the second source extension portion 37, a second via hole 60 is formed between the second source extension portion 37 and the static eliminating layer 40, and the second source extension portion 37 extends into the second via hole 60 to be connected with the static eliminating layer 40. The static eliminating layer 40 and the first active layer 21 are arranged in the same layer, so that the film structure of the array substrate can be further simplified, and the process cost is reduced.
Specifically, the material of the static electricity removing layer 40 may include amorphous silicon (asi), indium Gallium Zinc Oxide (IGZO), indium tin zinc oxide (IZTO), indium Gallium Zinc Tin Oxide (IGZTO), molybdenum or other materials capable of conducting out static electricity, which is not limited in this application. It is understood that when the static-removing layer 40 and the first active layer 21 are selected from the same materials, the static-removing layer 40 and the first active layer 21 may be formed through the same process step.
In the present embodiment, the first via 50 and the second via 60 are a set of holes. Specifically, the first via 50 coincides with the via center of the second via 60. It can be appreciated that the first via hole 50 and the second via hole 60 are set as a set of holes, which can further save design space and facilitate further reduction of the size of the array substrate.
Referring to fig. 3, an array substrate 100 according to another embodiment of the present application is provided. The array substrate 100 according to another embodiment of the present application is different from the array substrate 100 according to an embodiment of the present application shown in fig. 2 in that: the static eliminating layer 40 and the second active layer 34 are arranged on the same layer, the orthographic projection of the first drain electrode extension part 28 on the plane of the static eliminating layer 40 overlaps with the static eliminating layer 40, correspondingly, a first through hole 50 is formed between the first drain electrode extension part 28 and the static eliminating layer 40, the first drain electrode extension part 28 extends into the first through hole 50 to be connected with the static eliminating layer 40, a second through hole 60 is formed between the second source electrode extension part 37 and the static eliminating layer 40, and the static eliminating layer 40 extends into the second through hole 60 to be connected with the second source electrode extension part 37. The first via 50 and the second via 60 are a set of holes.
It is understood that when the static-removing layer 40 and the second active layer 34 are selected from the same materials, the static-removing layer 40 and the second active layer 34 may be formed through the same process step.
Referring to fig. 4, another embodiment of the present application provides an array substrate 100. The array substrate 100 according to another embodiment of the present application is different from the array substrate 100 according to one embodiment of the present application shown in fig. 2 in that: the array substrate 100 further includes a capacitance dielectric layer 29 disposed between the first gate electrode 23 and the third gate electrode 27, specifically, between the first insulating layer 22 and the second insulating layer 24. The capacitor dielectric layer 29 may be a multilayer structure having a thickness of 50 to 100 angstroms. It can be understood that when the array substrate 100 includes the capacitance dielectric layer 29, the effect of increasing the storage capacitance can be achieved on the premise that the total thickness of the first insulating layer and the second insulating layer is substantially unchanged, so that the stability of the gate potential is further improved, and the display of the pixel can be driven more stably.
Specifically, the material of the capacitance dielectric layer 29 includes one or more of aluminum oxide, chromium oxide, or titanium oxide. It should be noted that alumina, chromia or titania not only has a large dielectric constant, but also has a good hydrogen-blocking effect. The material of the capacitance medium layer 29 includes one or more of aluminum oxide, chromium oxide, or titanium oxide, not only can increase the storage capacitance, but also can better block the diffusion of hydrogen to the second thin film transistor 30. When the first thin film transistor 20 is a low temperature polysilicon thin film transistor, the second thin film transistor 30 is an oxide thin film transistor, and the material of the first insulating layer 22 is silicon nitride with a high hydrogen content, the influence of the diffusion of hydrogen on the stability of the second thin film transistor 30 can be further reduced, and the reliability of the second thin film transistor 30 is further improved.
The embodiment of the application also provides a preparation method of the array substrate, which comprises the following steps:
providing a substrate;
forming a first thin film transistor on one side of a substrate, wherein the first thin film transistor comprises a first grid electrode, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on one side of the first grid electrode away from the substrate;
forming a second thin film transistor on one side of the substrate, wherein the second thin film transistor is adjacent to the first thin film transistor, and comprises a second grid electrode, a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are positioned on one side, close to the substrate, of the second grid electrode;
the second source electrode, the second drain electrode and the first grid electrode are arranged in the same layer, and the second grid electrode, the first source electrode and the first drain electrode are arranged in the same layer.
Therefore, in the preparation method of the array substrate provided by the embodiment, the source and drain electrodes of the second thin film transistor and the first grid electrode of the first thin film transistor are arranged in the same layer, the grid electrode of the second thin film transistor and the source and drain electrodes of the first thin film transistor are arranged in the same layer, and the film structure of the array substrate is simplified into three metal layers and four insulating layers, so that the arrangement of one metal layer in the array substrate is reduced, one photomask is saved, the arrangement of one insulating layer is correspondingly reduced, the film structure of the array substrate is simplified, the process is saved, and the process cost is reduced.
Next, the method for manufacturing the array substrate provided in the present application will be described in detail by taking the array substrate 100 provided in the foregoing embodiment shown in fig. 2 as an example, but it should not be construed as limiting the present application.
Specifically, the preparation method of the array substrate provided by the embodiment of the application comprises the following steps:
a substrate is provided. The substrate may be a flexible substrate, in particular, the substrate may comprise a first flexible substrate, a buffer layer, a second flexible substrate, a first barrier layer, a second barrier layer and a barrier layer in a stacked arrangement. Of course, the substrate may be a rigid substrate such as glass, and the present application is not limited thereto.
And depositing a layer of amorphous silicon on one side of the substrate, and patterning the amorphous silicon to define a first active layer and a static eliminating layer. The patterning process may include conventional processes such as photoresist coating, exposure, development, etching, and photoresist stripping, which are not described herein.
A first insulating layer is formed on a side of the first active layer remote from the substrate. The material of the first insulating layer may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. Of course, the first insulating layer may be made of other materials, which is not limited herein. The thickness of the first insulating layer may be 1000 to 3000 angstroms.
A first metal layer is formed on a side of the first insulating layer away from the first active layer, and a material of the first metal layer may include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The first metal layer may have a thickness of 2000 to 8000 angstroms. The first metal layer is patterned to form a third gate, and a forward projection area of the third gate on the substrate is positioned in a forward projection area of the first active layer on the substrate. And taking the third grid electrode as a shielding layer, and carrying out ion doping on the first active layer to form a channel region.
And forming a second insulating layer on one side of the third grid electrode far away from the first insulating layer. The material of the second insulating layer may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. Of course, the second insulating layer may be made of other materials, which is not limited herein. The thickness of the second insulating layer may be 1000 to 3000 angstroms.
And forming a second metal layer on one side of the second insulating layer away from the first metal layer. The material of the second metal layer may include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The second metal layer may have a thickness of 2000 to 8000 angstroms. The second metal layer is patterned to form a first grid electrode, a second source electrode and a second drain electrode which are sequentially arranged at intervals, a orthographic projection area of the first grid electrode on the substrate is overlapped with an orthographic projection area of the first grid electrode on the substrate, and the second source electrode comprises a second source electrode extension part.
And forming a third insulating layer on one side of the second metal layer away from the second insulating layer, and forming a via hole in the third insulating layer for overlapping the second source electrode and the second drain electrode through patterning. The material of the third insulating layer may include silicon nitride, silicon oxide, or an organic material. The thickness of the third insulating layer may be 2000 to 10000 angstroms.
And forming a second active layer on one side of the third insulating layer away from the second metal layer. The material of the second active layer may include one or more of metal oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), indium tin zinc oxide (IZTO), or Indium Gallium Zinc Tin Oxide (IGZTO). Of course, the second active layer may be made of other materials, which is not limited herein. The thickness of the second active layer may be 100 to 1000 angstroms.
A fourth insulating layer is formed on a side of the second active layer away from the third insulating layer. The material of the fourth insulating layer may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. Of course, the fourth insulating layer may be made of other materials, which is not limited in this application. The thickness of the fourth insulating layer may be 1000 to 3000 angstroms.
And forming a third metal layer on one side of the fourth insulating layer away from the second active layer. The material of the third metal layer may include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The thickness of the third metal layer may be 2000 to 8000 angstroms. The third metal layer is patterned to form a first source electrode, a first drain electrode and a second grid electrode which are sequentially arranged at intervals, and a orthographic projection area of the second grid electrode on the substrate is positioned in a orthographic projection area of the second active layer on the substrate. And taking the second grid electrode as a shielding layer, and carrying out ion doping on the second active layer to form a channel region.
And forming a passivation layer with the whole surface covering on one side of the third metal layer far away from the fourth insulating layer to obtain the array substrate. The material of the passivation layer may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. The passivation layer may have a thickness of 1000 to 5000 angstroms.
Referring to fig. 5, the present application further provides a display device 200. The display device 200 may be a product or a component with a display function, such as a watch, a bracelet, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, etc.
The display device 200 includes an array substrate 100 and a display panel 101 disposed on the array substrate 100. Specifically, the display panel 101 may be a liquid crystal display panel, an organic light emitting diode display panel, a mini light emitting diode display panel, or a micro light emitting diode display panel.
The array substrate 100 may be any one of the foregoing embodiments, and the specific structure of the array substrate may refer to the description of the foregoing embodiments, which is not repeated herein.
It can be understood that, because the array substrate included in the display device is the array substrate provided by the embodiment of the application, the film structure is simplified, the process cost is reduced, and the realization of light and thin display device is facilitated.
The array substrate, the preparation method of the array substrate and the display device provided by the embodiment of the application are described in detail, and specific examples are applied to the description of the principles and the implementation modes of the application, and the description of the above examples is only used for helping to understand the method and the core idea of the application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. An array substrate, characterized by comprising:
a substrate;
the first thin film transistor is arranged on the substrate and comprises a first grid electrode, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on one side, far away from the substrate, of the first grid electrode; and
the second thin film transistor is arranged on the substrate and is adjacent to the first thin film transistor, the second thin film transistor comprises a second grid electrode, a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are positioned on one side, close to the substrate, of the second grid electrode;
the second source electrode, the second drain electrode and the first grid electrode are arranged in the same layer, and the second grid electrode, the first source electrode and the first drain electrode are arranged in the same layer.
2. The array substrate of claim 1, wherein the first drain electrode comprises a first drain extension portion, the second source electrode comprises a second source extension portion, an orthographic projection of the second source extension portion on a plane of the first drain extension portion overlaps the first drain extension portion, and the second source extension portion is connected to the first drain extension portion through a portion opposite to the first drain extension portion.
3. The array substrate of claim 2, further comprising a static elimination layer and a first active layer disposed on the same layer, wherein the first active layer is disposed between the first gate and the substrate, a orthographic projection of the second source extension on a plane on which the static elimination layer is disposed overlaps the static elimination layer, a first via hole is disposed between the first drain extension and the second source extension, the first drain extension extends into the first via hole to be connected with the second source extension, a second via hole is disposed between the second source extension and the static elimination layer, and the second source extension extends into the second via hole to be connected with the static elimination layer.
4. The array substrate of claim 2, further comprising a static elimination layer and a second active layer disposed on the same layer, wherein the second active layer is disposed between the second gate and the second source and the second drain, an orthographic projection of the first drain extension on a plane where the static elimination layer is disposed overlaps the static elimination layer, a first via hole is disposed between the first drain extension and the static elimination layer, the first drain extension extends into the first via hole to be connected with the static elimination layer, a second via hole is disposed between the second source extension and the static elimination layer, and the static elimination layer extends into the second via hole to be connected with the second source extension.
5. The array substrate of claim 3 or 4, wherein the first via and the second via are a set of holes.
6. The array substrate of any one of claims 1 to 4, wherein the first thin film transistor further comprises a third gate electrode on a side of the first gate electrode remote from the substrate or on a side close to the substrate.
7. The array substrate of claim 6, wherein the array substrate comprises a capacitive dielectric layer disposed between the first gate and the third gate, the capacitive dielectric layer comprising a material comprising one or more of aluminum oxide, chromium oxide, or titanium oxide.
8. The array substrate of claim 7, wherein the first thin film transistor further comprises a first active layer, a material of the first active layer comprising polysilicon; the second thin film transistor further includes a second active layer, and a material of the second active layer includes a metal oxide semiconductor.
9. The preparation method of the array substrate is characterized by comprising the following steps of:
providing a substrate;
forming a first thin film transistor on one side of the substrate, wherein the first thin film transistor comprises a first grid electrode, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on one side of the first grid electrode away from the substrate;
forming a second thin film transistor on one side of the substrate, wherein the second thin film transistor is adjacent to the first thin film transistor, the second thin film transistor comprises a second grid electrode, a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are positioned on one side, close to the substrate, of the second grid electrode;
the second source electrode, the second drain electrode and the first grid electrode are arranged in the same layer, and the second grid electrode, the first source electrode and the first drain electrode are arranged in the same layer.
10. A display device comprising the array substrate according to any one of claims 1 to 8.
CN202310265253.0A 2023-03-10 2023-03-10 Array substrate, preparation method of array substrate and display device Pending CN117476668A (en)

Priority Applications (1)

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CN202310265253.0A CN117476668A (en) 2023-03-10 2023-03-10 Array substrate, preparation method of array substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310265253.0A CN117476668A (en) 2023-03-10 2023-03-10 Array substrate, preparation method of array substrate and display device

Publications (1)

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CN117476668A true CN117476668A (en) 2024-01-30

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