CN117457749A - SiC LMOS with P-type space layer below grid electrode and preparation method - Google Patents
SiC LMOS with P-type space layer below grid electrode and preparation method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a SiC LMOS with a P-type space layer below a grid electrode and a preparation method thereof, wherein the SiC LMOS comprises the following steps: a P-type space layer; the P-type space layer is positioned between the grid electrode and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region, the P+ region and the drift layer. The invention introduces the P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector, the interface mobility of the gate oxide layer and the silicon carbide is low, the resistance is large, and the conductive path shorts the interface channel of the gate oxide layer, so that the on-resistance of the SiC LMOS is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC LMOS with a P-type space layer below a grid electrode and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. Silicon carbide is more conveniently formed into silicon dioxide by thermal oxidation than other third generation semiconductors such as GaN. SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in the extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. The SiC power device has a series of advantages of high input impedance, high switching speed, high working frequency, high voltage resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high frequency, power amplifiers and the like.
Silicon carbide (SiC) materials are commonly used materials for fabricating field effect transistors, and silicon dioxide (SiO 2 ) Often used as a gate oxide layer, the prior art generally requires thermal oxidation of SiC materials to form silicon dioxide (SiO 2 ) As the dielectric layer under the grid, because the atomic surface density of SiC per unit area is higher than Si, the density of dangling Si bonds, C bonds and carbon clusters at the interface is higher, more defects are introduced when forming the grid oxide layer and serve as electron traps, thereby leading to the following problems of SiC/SiO 2 The interface trap density of the (C) is high, the problem of reduced electron mobility of the SiC field effect transistor is caused, and the electron mobility of a channel is 12cm due to the scattering and trapping of electrons at the defect of an interface point 2 Vs, and in vivo mobility of 400 cm 2 Vs thus degrading the performance of the device. At present, common SiC/SiO reduction 2 The interface trap density method is to carry out nitriding annealing treatment after thermal oxidation, but has limited effect and low controllability, and the method can increase the working procedures of the device process, so the method has higher production cost.
Disclosure of Invention
The invention aims to provide a SiC LMOS with a P-type space layer below a grid electrode and a preparation method thereof, wherein the SiC LMOS introduces the P-type space layer below a trench grid electrode, and because the thickness of the P-type space layer is very thin, when the grid electrode is connected with a positive voltage, an inversion layer is formed on the P-type space layer under a lower grid voltage, so that a conductive path from an emitter to an N+ region, from the N+ region to the P-type space layer, from the P-type space layer to a drift layer and finally to a collector electrode is formed, the mobility of a grid oxide and a silicon carbide interface is low, the resistance is large, and the conductive path shorts an interface channel of the grid oxide layer, thereby reducing the on resistance of the SiC LMOS.
A SiC LMOS having a P-type spatial layer under a gate, comprising: a P-type space layer;
the P-type space layer is positioned between the grid electrode and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region, the P+ region and the drift layer.
The thickness of the P-type space layer is 80-100nm.
Preferably, the method further comprises: an N-channel layer;
the N-channel layer is positioned between the drift layer and the P+ region, between the P-type space layer and the N+ region and is adjacent to the drift layer, the P+ region, the P-type space layer and the N+ region.
Preferably, the doping concentration of the P-type space layer is 5×10 15 To 10 16 cm -3 。
Preferably, the doping concentration of the N-channel layer is 4×10 17 cm -3 。
Preferably, the method further comprises: a P-resurf layer;
the P-resurf layer is located between and adjacent to the ILD layer and the drift layer.
Preferably, the P-resurf layer has a doping concentration of 10 16 To 10 17 cm -3 。
Preferably, the thickness of the N-channel layer is 0.3-0.5um.
Preferably, the method further comprises: a gate, a drain, a source, a substrate, a drift layer, an ILD layer, an N+ region and a P+ region;
the substrate is positioned below the drift layer;
the drift layer is positioned below the N+ region, the P+ region and the P-type space layer;
the source electrode is positioned above the N+ region and the P+ region;
the drain electrode is positioned above the N+ region;
the ILD layer is located between the source electrode and the drain electrode;
the P+ region is located below the source electrode;
the n+ region is located under the source and the drain;
the gate is located below the source.
A preparation method of SiC LMOS with a P-type space layer below a grid electrode comprises the following steps:
epitaxially forming a drift layer over a substrate;
forming an N-channel layer, a P+ region, a P-type space layer, a P-resurf layer and an N+ region on the upper layer of the drift layer by ion implantation;
etching the N+ region to form a groove;
depositing a gate in the trench, depositing an ILD layer over the p+ region, P-resurf layer, and n+ region;
and depositing a source electrode and a drain electrode.
The invention introduces a P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from an emitter to an N+ region, from the N+ region to the P-type space layer, from the P-type space layer to a drift layer and finally to a collector, the interface mobility of the gate oxide layer and silicon carbide is low, the resistance is large, the conductive path shorts the interface channel of the gate oxide layer, thereby reducing the on-resistance of SiC LMOS.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of the structure of the SiC LMOS of the present invention;
FIG. 2 is a schematic diagram of a process flow for preparing SiC LMOS of the present invention;
FIG. 3 is a schematic diagram of the preparation flow of SiC LMOS of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Silicon carbide (SiC) materials are commonly used in fabricating field effect transistorsMaterial, silicon dioxide (SiO 2 ) Often used as a gate oxide layer, the prior art generally requires thermal oxidation of SiC materials to form silicon dioxide (SiO 2 ) As the dielectric layer under the grid, because the atomic surface density of SiC per unit area is higher than Si, the density of dangling Si bonds, C bonds and carbon clusters at the interface is higher, more defects are introduced when forming the grid oxide layer and serve as electron traps, thereby leading to the following problems of SiC/SiO 2 The interface trap density of the (C) is high, the problem of reduced electron mobility of the SiC field effect transistor is caused, and the electron mobility of a channel is 12cm due to the scattering and trapping of electrons at the defect of an interface point 2 Vs, and in vivo mobility of 400 cm 2 Vs thus degrading the performance of the device. At present, common SiC/SiO reduction 2 The interface trap density method is to carry out nitriding annealing treatment after thermal oxidation, but has limited effect and low controllability, and the method can increase the working procedures of the device process, so the method has higher production cost.
The invention introduces a P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from an emitter to an N+ region, from the N+ region to the P-type space layer, from the P-type space layer to a drift layer and finally to a collector, the interface mobility of the gate oxide layer and silicon carbide is low, the resistance is large, the conductive path shorts the interface channel of the gate oxide layer, thereby reducing the on-resistance of SiC LMOS.
Example 1
A SiC LMOS having a P-type spatial layer under the gate, referring to fig. 1, comprising: a P-type space layer;
the substrate of the PN junction is divided into P type and N type, and +is heavily doped (high doping concentration), is lightly doped (low doping concentration), and P type doped with IIIA group elements, such as: boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl). N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc).
The P-type space layer is positioned between the grid electrode and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region, the P+ region and the drift layer.
The P-type space layer is a P-type doped semiconductor, the P-type space layer is arranged between the N+ region and the drift layer, a conductive path positioned in the P-type space layer can be opened by the grid electrode, negative charges positioned in the P-type space layer can be attracted by the grid electrode when the grid electrode is connected with positive voltage, so that an inversion layer is formed below the grid electrode, current can flow from the emitter to the N+ region, then flow from the N+ region to the P-type space layer, flow from the P-type space layer to the drift layer, and finally flow from the drift layer to the collector.
Because the thickness of the P-type space layer is small, the P-type space layer can form a conductive path from the N+ region to the drift layer under a lower gate voltage, so that the problem of low mobility of a silicon carbide-silicon dioxide interface is solved, the channel resistance is greatly reduced, and the electrical performance of the SiC LMOS is remarkably improved.
The thickness of the P-type space layer is 80-100nm.
The thickness of the P-type space layer can influence the opening voltage of the conductive channel, because the opening of the conductive channel needs to change the P-type space layer into an inversion layer completely in the vertical direction, the larger the thickness of the P-type space layer is, the more difficult the P-type space layer is to be completely induced into the inversion layer in the vertical direction, the higher the required gate voltage is, the thickness of the P-type space layer is not too thick, otherwise, the gate is difficult to induce to form the inversion layer, the opening voltage required by the conductive channel is too high, and the on-resistance is increased accordingly, the thickness of the P-type space layer is not too thin, the smaller the thickness of the P-type space layer can enable electrons to pass through the P-type space layer relatively easily, so that the too thin P-type space layer can enable SiC LMOS to leak electricity, and the pressure resistance is reduced.
Preferably, the method further comprises: an N-channel layer;
the N-channel layer is positioned between the drift layer and the P+ region, the P-type space layer and the N+ region and is adjacent to the drift layer, the P+ region, the P-type space layer and the N+ region.
According to the invention, the upper layer of the drift layer is replaced by the N-channel layer, the doping concentration of the N-channel layer is higher than that of the drift layer, because majority carriers of the N-type doped semiconductor are electrons, the on-resistance can be reduced by increasing the doping concentration in the drift layer, electrons pass through the N-channel layer with low resistance from the P-type space layer and finally flow from the N-channel layer to the drain electrode, the movement path of the electrons is shown by an arrow in the figure 1 of the invention, and the on-resistance of the SiC LMOS can be obviously reduced by adopting the N-channel layer with high doping concentration.
Preferably, the doping concentration of the P-type space layer is 5×10 15 To 10 16 cm -3 。
The doping concentration of the P-type space layer influences the opening voltage of the conductive channel, because majority carriers in the P-type semiconductor are holes, and the principle of opening the conductive channel by the grid is that electrons in the P-type space layer are attracted to form the conductive channel, the higher the doping concentration of the P-type semiconductor is, the higher the concentration of the holes is, the smaller the concentration of the electrons is, the more difficult the grid is to attract electrons to form the conductive channel, the higher the grid voltage is needed to form an inversion layer on the P-type space layer, so the higher the doping concentration of the P-type space layer is, the higher the opening voltage of the conductive channel is, the lower the doping concentration of the P-type space layer is, the lower the opening voltage of the conductive channel is, if the doping concentration of the P-type space layer is too small, the problem of SiC LMOS leakage and reduced pressure resistance is caused, and as a preferred embodiment, the doping concentration of the P-type space layer is set to be 10 16 cm -3 The purpose is to ensure that the SiC LMOS has better pressure resistance and stability while reducing the channel resistance.
Preferably, the doping concentration of the N-channel layer is 4×10 17 cm -3 。
The doping concentration of the N-channel layer influences the on-resistance of the SiC LMOS, the higher the doping concentration of the N-channel layer is, the more electrons the N-channel layer contains, the higher the electron density is, the lower the on-resistance of the SiC LMOS is,the on-current of the SiC LMOS will also increase, if the current passing through the N-channel layer exceeds the bearing range of the SiC LMOS, the defect that the SiC LMOS is broken down by large current will be caused, so the doping concentration of the N-channel layer cannot be too high, and the N-channel layer with too high doping concentration will also increase the production cost, as a preferred embodiment, the invention sets the doping concentration of the N-channel layer to 4 multiplied by 10 17 cm -3 。
Preferably, the method further comprises: a P-resurf layer;
the P-resurf layer is located between and adjacent to the ILD layer and the drift layer.
The P-resurf layer has the function of reducing the electric field on the surface of the device, the principle is that the N-type drift layer is used up in an auxiliary mode, so that the effect of increasing the concentration of the N-type drift layer is achieved, the P-resurf layer can reduce on-resistance while the breakdown voltage is increased, the problem of compromise between the breakdown voltage and the on-resistance is solved, when the metal electrode is connected with the voltage, the maximum electric field of the longitudinal PN junction reaches a critical electric field first, the requirement of surface electric field distribution is reduced, the P-resurf layer is required to be completely depleted from the drift layer, the doping concentration of the P-resurf layer is larger than that of the drift layer, and the doping concentration of the drift layer is larger than that of the substrate.
Preferably, the P-resurf layer has a doping concentration of 10 16 To 10 17 cm -3 。
The doping concentration of the P-resurf layer affects the breakdown voltage of the LMOS, the breakdown voltage of the LMOS increases with the increase of the doping concentration of the P-resurf layer, when the doping concentration of the P-resurf layer increases to a critical value, the breakdown voltage of the LMOS decreases with the increase of the doping concentration of the P-resurf layer, and the position of the P-resurf layer also affects the breakdown voltage of the LMOS, when the P-resurf layer completely fills the position between the emitter and the collector, the optimal breakdown voltage can be obtained, and as a preferred embodiment, the invention sets the doping concentration of the P-resurf layer to 10 17 cm -3 。
Preferably, the thickness of the N-channel layer is 0.3-0.5um.
The thickness of the N-channel layer influences the width of the current path of the SiC LMOS, and the larger the thickness of the N-channel layer is, the larger the width of the current path of the SiC LMOS is, but the pressure resistance of the SiC LMOS is also reduced, and the thickness of the N-channel layer is in the range of 0.3-0.5um as a preferable embodiment of the invention, because a large area of large current passes through the drift region to generate high electric field intensity.
Preferably, the method further comprises: a gate, a drain, a source, a substrate, a drift layer, an ILD layer, an N+ region and a P+ region;
the substrate is positioned below the drift layer;
the substrate is the material used to support crystal generation in the MOSFET, and the substrate acts as a mechanical support. In the present invention, the substrate is made of silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is critical to ensure uniformity and integrity of crystal growth. In addition, the substrate can also prevent impurities and defects during crystal growth, thereby improving the quality of the MOSFET. Second, the substrate plays an important role in the electrical performance of the MOSFET. In the fabrication of MOSFETs, the electrical properties of the substrate determine the performance and stability of the device. For example, the conductivity of the substrate directly affects the efficiency and speed of current transport. In addition, the electron affinity and the forbidden band width of the substrate are also critical to adjusting the threshold voltage and electron mobility of the MOSFET. In addition, the substrate plays an important role in isolating the insulating layer of the MOSFET. During MOSFET fabrication, the insulating layer of the substrate is typically composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulating properties of the MOSFET, such as electrical insulation and capacitive characteristics. The good insulating layer can effectively isolate different electrodes in the MOSFET structure and reduce leakage current and capacitive coupling effect.
The drift layer is positioned below the N+ region, the P+ region and the P-type space layer;
the electric field distribution of the drift layer plays a key role in the on-characteristics and current control of the MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. During MOSFET operation, current between source and drain is transferred primarily through the N-drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and the magnitude of the current. The structure and characteristics of the drift layer directly affect the current control capability of the MOS transistor. By adjusting the shape, size and doping concentration of the drift layer, accurate control of current can be achieved, so that the requirements of different applications are met.
The source electrode is positioned above the N+ region and the P+ region;
the source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
The drain electrode is positioned above the N+ region;
the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.
An ILD layer located between the source and drain electrodes;
ILD process refers to the dielectric material formed between the transistor and the first layer of metal, with the ILD layer deposited primarily on top of the transistor to form electrical isolation. The ILD dielectric layer can effectively reduce parasitic capacitance between the metal and the substrate, and improve parasitic field effect transistors formed by crossing different areas by the metal, and the filling material of the ILD dielectric layer is silicon dioxide.
The P+ region is positioned below the source electrode;
the N+ region is positioned below the source electrode and the drain electrode;
the gate is located under the source.
The gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.
Example 2
A method for preparing SiC LMOS having a P-type space layer under a gate, referring to fig. 2 and 3, comprising:
s100, epitaxially forming a drift layer above a substrate;
the epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate, and the epitaxial process is a process of growing a crystal layer in the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processing in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like.
S200, forming an N-channel layer, a P+ region, a P-type space layer, a P-resurf layer and an N+ region on the upper layer of the drift layer by ion implantation;
the invention adopts an ion implantation mode to form an N-channel layer, a P+ region, a P-space layer, a P-resurf layer and an N+ region on the upper layer of the drift layer by ion implantation. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S300, etching the N+ region to form a groove;
etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is a chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor whereby the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S400, depositing a grid electrode in the groove, and depositing an ILD layer above the P+ region, the P-resurf layer and the N+ region;
the deposited grid adopts a polysilicon deposition method, namely, a grid electrode and local connection lines are formed on the silicide stack on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forms contact plugs between the source electrode/drain electrode and the unit connection lines. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) process by depositing arsenic trioxide (AH) in a reaction chamber (i.e., in a furnace tube) 3 ) Phosphorus trihydride (PH) 3 ) Or diborane (B) 2 H 6 ) The doping gas of the silicon material is directly input into the silicon material gas of silane or DCS, so that the polysilicon doping process of the in-situ low-pressure chemical vapor deposition can be performed. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.
S500, depositing a source electrode and a drain electrode.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like.
The invention introduces a P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from an emitter to an N+ region, from the N+ region to the P-type space layer, from the P-type space layer to a drift layer and finally to a collector, the interface mobility of the gate oxide layer and silicon carbide is low, the resistance is large, the conductive path shorts the interface channel of the gate oxide layer, thereby reducing the on-resistance of SiC LMOS.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A SiC LMOS having a P-type spatial layer under a gate, comprising: a P-type space layer;
the P-type space layer is positioned between the grid electrode and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region, the P+ region and the drift layer.
2. A SiC LMOS having a P-type space layer under a gate as claimed in claim 1, wherein said P-type space layer has a thickness of 80-100nm.
3. A SiC LMOS having a P-type space layer under a gate as defined in claim 1, further comprising: an N-channel layer;
the N-channel layer is positioned between the drift layer and the P+ region, between the P-type space layer and the N+ region and is adjacent to the drift layer, the P+ region, the P-type space layer and the N+ region.
4. A SiC LMOS having a P-type space layer under a gate as claimed in claim 1, wherein said P-type space layer has a doping concentration of 5 x 10 15 To 10 16 cm -3 。
5. A SiC LMOS having a P-type space layer under a gate as claimed in claim 3 wherein said N-channel layer has a doping concentration of 4 x 10 17 cm -3 。
6. A SiC LMOS having a P-type space layer under a gate as defined in claim 1, further comprising: a P-resurf layer;
the P-resurf layer is located between and adjacent to the ILD layer and the drift layer.
7. The SiC LMOS having a P-type space layer under a gate as claimed in claim 6, wherein said P-resurf layer has a doping concentration of 10 16 To 10 17 cm -3 。
8. A SiC LMOS having a P-type space layer under a gate according to claim 1 wherein said N-channel layer has a thickness of 0.3-0.5um.
9. A SiC LMOS having a P-type space layer under a gate as defined in claim 1, further comprising: a gate, a drain, a source, a substrate, a drift layer, an ILD layer, an N+ region and a P+ region;
the substrate is positioned below the drift layer;
the drift layer is positioned below the N+ region, the P+ region and the P-type space layer;
the source electrode is positioned above the N+ region and the P+ region;
the drain electrode is positioned above the N+ region;
the ILD layer is located between the source electrode and the drain electrode;
the P+ region is located below the source electrode;
the n+ region is located under the source and the drain;
the gate is located below the source.
10. The preparation method of the SiC LMOS with the P-type space layer below the grid electrode is characterized by comprising the following steps of:
epitaxially forming a drift layer over a substrate;
forming an N-channel layer, a P+ region, a P-type space layer, a P-resurf layer and an N+ region on the upper layer of the drift layer by ion implantation;
etching the N+ region to form a groove;
depositing a gate in the trench, depositing an ILD layer over the p+ region, P-resurf layer, and n+ region;
and depositing a source electrode and a drain electrode.
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