CN117457718A - Semiconductor device and chip - Google Patents

Semiconductor device and chip Download PDF

Info

Publication number
CN117457718A
CN117457718A CN202311590176.2A CN202311590176A CN117457718A CN 117457718 A CN117457718 A CN 117457718A CN 202311590176 A CN202311590176 A CN 202311590176A CN 117457718 A CN117457718 A CN 117457718A
Authority
CN
China
Prior art keywords
semiconductor device
epitaxial
metal layer
epitaxial layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311590176.2A
Other languages
Chinese (zh)
Inventor
丁泊宁
胡爱斌
张宁涛
徐朔
李伟叶
沈煜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ruineng Semiconductor Technology Co ltd
Original Assignee
Ruineng Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ruineng Semiconductor Technology Co ltd filed Critical Ruineng Semiconductor Technology Co ltd
Priority to CN202311590176.2A priority Critical patent/CN117457718A/en
Publication of CN117457718A publication Critical patent/CN117457718A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The application relates to a semiconductor device and a chip, wherein the semiconductor device comprises a cell structure, and the cell structure comprises an epitaxial layer, a field plate and a plurality of grid structures. The epitaxial layer comprises an epitaxial part and first grooves distributed on the periphery of the epitaxial part. The epitaxial portion includes a doped region and a plurality of second trenches. The plurality of gate structures are disposed in one-to-one correspondence with the plurality of second trenches. The field plates are arranged in the first grooves, the field plates are distributed on the periphery of the grid structure, and the doped regions are located between the grid structure and the field plates. The method and the device can improve the performance of the semiconductor device.

Description

Semiconductor device and chip
Technical Field
The present disclosure relates to semiconductor devices, and particularly to a semiconductor device and a chip.
Background
Silicon carbide (SiC) power metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) become the most mature SiC power devices with application prospect due to the characteristics of high breakdown voltage, high switching speed, high thermal conductivity, low on-resistance, low switching loss, low driving power and the like.
The MOSFET devices may include planar gate MOSFET devices and trench MOSFET devices. The trench MOSFET device eliminates junction field effect transistor (PN Junction Field Effect Transistor, JFET) resistance, has a higher on-resistance and a higher power density relative to a planar gate MOSFET device.
In the development of semiconductor technology, how to improve the performance of semiconductor devices has been one of the research directions in semiconductor technology.
Disclosure of Invention
The semiconductor device and the chip provided by the embodiment of the application can improve the performance of the semiconductor device.
In one aspect, according to an embodiment of the present application, a semiconductor device is provided that includes a cell structure including an epitaxial layer, a field plate, and a plurality of gate structures. The epitaxial layer comprises an epitaxial part and first grooves distributed on the periphery of the epitaxial part. The epitaxial portion includes a doped region and a plurality of second trenches. The plurality of gate structures are disposed in one-to-one correspondence with the plurality of second trenches. The field plates are arranged in the first grooves, the field plates are distributed on the periphery of the grid structure, and the doped regions are located between the grid structure and the field plates.
According to one aspect of an embodiment of the present application, the orthographic projection of the field plate along the thickness direction of the epitaxial layer is a continuous closed pattern.
According to one aspect of an embodiment of the present application, the number of cell structures includes a plurality, and two adjacent cell structures share a field plate.
According to an aspect of the embodiments of the present application, the epitaxial layer further includes a body portion, the epitaxial portion is disposed on one side of the body portion, the number of the epitaxial portions is plural, and the number of the epitaxial portions is configured to correspond to the number of the cell structures.
According to one aspect of an embodiment of the present application, a plurality of gate structures are spaced apart along a first direction; and/or the plurality of gate structures are distributed at intervals along the second direction, and the first direction, the second direction and the epitaxial layer thickness direction are intersected two by two.
According to one aspect of embodiments of the present application, at least some of the plurality of gate structures are disposed to intersect.
According to an aspect of the embodiments of the present application, the semiconductor device further includes a first metal layer, the first metal layer is located on a side of the epitaxial layer away from the doped region, the first metal layer includes a connection portion, the connection portion extends from the first metal layer toward a side of the epitaxial layer into the epitaxial layer, and the doped region and the field plate are both in contact with the connection portion.
According to an aspect of the embodiments of the present application, the semiconductor device further includes a second metal layer, the first metal layer and the second metal layer are disposed in an insulating manner, the second metal layer is located between the first metal layer and the epitaxial layer, and a side, facing the second metal layer, of the plurality of gate structures is connected to the second metal layer.
According to an aspect of the embodiments of the present application, the cell structures are arranged in rows along the first direction and in rows along the second direction, the second metal layer includes a plurality of extended conductive portions, the plurality of extended conductive portions are spaced apart along the second direction, and each extended conductive portion is disposed in an extending manner along the first direction, and the gate structure in each of the cell structures is connected to one of the extended conductive portions. The first direction, the second direction and the thickness direction of the epitaxial layer are intersected two by two.
On the other hand, the embodiment of the application also provides a chip, wherein the chip comprises the semiconductor device and the integrated circuit in any one of the previous embodiments. The integrated circuit is electrically connected to the semiconductor device.
According to the semiconductor device and the chip provided by the application, the semiconductor device comprises a cell structure, and the cell structure comprises an epitaxial layer, a gate structure and a field plate. The epitaxial layer is provided with a plurality of gate structures, so that the overcurrent area of the gate structures can be increased, and the resistance of the gate structures in the working process of the semiconductor device is reduced. The field plate is arranged around the grid structure, so that the dimension of an electric field effect can be increased, the resistance of the semiconductor device is reduced while the breakdown voltage threshold value is increased, the conduction loss of the semiconductor device is reduced, and the performance of the semiconductor device is improved.
Drawings
Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic top view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 2 is a schematic cross-sectional view of A-A of FIG. 1;
FIG. 3 is a schematic cross-sectional view of the structure B-B of FIG. 1;
fig. 4 is a schematic top view of another semiconductor device according to some embodiments of the present application;
fig. 5 is a schematic top view of another semiconductor device according to some embodiments of the present application;
fig. 6 is a schematic top view of another semiconductor device according to some embodiments of the present application;
fig. 7 is a schematic top view of another semiconductor device according to some embodiments of the present application;
fig. 8 is a schematic top view of another semiconductor device according to some embodiments of the present application;
FIG. 9 is a schematic cross-sectional view of the structure C-C of FIG. 1;
FIG. 10 is a schematic cross-sectional view of the structure D-D of FIG. 1;
fig. 11 is a schematic top view of a chip according to some embodiments of the present application.
Marking:
100. a semiconductor device;
200. a chip; 210. an integrated circuit; 220. a via hole;
10. an epitaxial layer; 11. an extension part; 111. a doped region; 1111. a first doping section; 1112. a second doping section; 1113. a third doping section; 12. a first trench; 13. a second trench; 14. a body portion;
20. a gate structure; 21. a gate; 22. a gate oxide layer;
30. a field plate;
40. a first metal layer; 41. a connection part; 42. a conductive body portion;
50. a second metal layer; 51. extending the conductive portion;
61. a first insulating dielectric layer; 62. a second insulating dielectric layer; 63. a third insulating dielectric layer;
x, a first direction; y, second direction; z, thickness direction.
In the drawings, like parts are designated with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
Currently, there are many factors that affect the performance of MOSFET devices, such as too high an on-resistance of the device, too low a breakdown voltage threshold, etc.
However, the on-resistance is inversely related to the area of the epitaxial layer in the device, and as the area of the epitaxial layer increases, the electric field decreases, which in turn results in a decrease in the threshold of the breakdown voltage.
Accordingly, in order to solve the above-mentioned problems, the embodiments of the present application provide a semiconductor device and a chip. For a better understanding of the present application, in one aspect, the following describes in detail a semiconductor device and a chip according to embodiments of the present application with reference to fig. 1 to 11.
Fig. 1 is a schematic top view of a semiconductor device according to some embodiments of the present application.
FIG. 2 is a schematic cross-sectional view of the structure A-A of FIG. 1. FIG. 3 is a schematic cross-sectional view of the structure B-B in FIG. 1.
As shown in fig. 1 to 3, the embodiment of the present application provides a semiconductor device 100, where the semiconductor device 100 includes a cell structure including an epitaxial layer 10, a field plate 30, and a plurality of gate structures 20. The epitaxial layer 10 includes an epitaxial portion 11 and first trenches 12 distributed on the peripheral side of the epitaxial portion 11. The epitaxial portion 11 includes a doped region 111 and a plurality of second trenches 13. The plurality of gate structures 20 are disposed in one-to-one correspondence with the plurality of second trenches 13. The field plate 30 is disposed in the first trench 12, the field plate 30 is disposed around the gate structure 20, and the doped region 111 is located between the gate structure 20 and the field plate 30.
Alternatively, the semiconductor device 100 may include one or more cell structures.
By way of example, each cell structure includes an epitaxial layer 10, a field plate 30, and a plurality of gate structures 20. Alternatively, the epitaxial layer 10 may be a whole layer structure, and a plurality of epitaxial portions 11 may be included on the whole epitaxial layer 10 to form a plurality of cell structures.
Optionally, the first doping type is opposite to the second doping type, it being understood that the first doping type is one of N-type or P-type and the second doping type is the other of N-type or P-type. For example, when the first doping type is N-type, the second doping type is P-type. For another example, when the first doping type is P-type, the second doping type is N-type.
In the embodiment of the application, the first doping type is N-type, and the second doping type is P-type. In other embodiments, the first doping type may be P-type and the second doping type may be N-type.
Alternatively, the surface of the epitaxial portion 11 may be a surface of the epitaxial portion 11 on the opposite side in the thickness direction Z, and the doped region 111 and the trench may be formed through the surface of the side into the epitaxial portion 11.
Alternatively, the epitaxial layer 10 may be fabricated from a material of the first doping type. Each of the epitaxial portions 11 includes a doped region 111, and the doped region 111 may include a first doped portion 1111, a second doped portion 1112, and a third doped portion 1113, where the first doped portion 1111, the second doped portion 1112, and the third doped portion 1113 are disposed on a peripheral side of the gate structure 20. Optionally, the first doping 1111 is of a first doping type, and the second doping 1112 and the third doping 1113 are of a second doping type. The first doped portion 1111 and the second doped portion 1112 are stacked, the first doped portion 1111 extends from the surface of the epitaxial portion 11 into the epitaxial portion 11 to a predetermined position, and the first doped portion 1111 is adjacent to the gate structure 20. The second doped portion 1112 is located on a side of the first doped portion 1111 facing away from the surface of the epitaxial portion 11, the third doped portion 1113 is located on a side of the first doped portion 1111 facing away from the gate structure 20, and the second doped portion 1112 may be disposed to cover the third doped portion 1113.
The first trench 12 may be concavely formed from one side surface of the epitaxial layer 10, and a region surrounded by the first trench 12 forms the epitaxial portion 11. Alternatively, the orthographic projection shape of the first trench 12 in the thickness direction Z of the epitaxial layer 10 is a continuous closed pattern. Alternatively, the first trench 12 includes a plurality of sub-trenches spaced around the peripheral side of the epitaxial layer 10.
Alternatively, the orthographic projection shape of the extension 11 in the thickness direction Z includes a circle, square, rectangle, pentagon, hexagon, or other polygon.
Accordingly, the orthographic projection shape of the first trench 12 in the thickness direction Z is disposed in match with the orthographic projection shape of the epitaxial portion 11 in the thickness direction Z. For example, the orthographic projection shape of the epitaxial portion 11 in the thickness direction Z is hexagonal, and the orthographic projection shape of the first trench 12 in the thickness direction Z is hexagonal.
The field plate 30 is disposed in the first trench 12, and a first insulating dielectric layer 61 may be further disposed between the field plate 30 and the epitaxial layer 10. Alternatively, the surface of the field plate 30 facing away from the epitaxial layer 10 is flush with the surface of the epitaxial portion 11.
Alternatively, the second trenches 13 are recessed from one side surface of the epitaxial layer 10, and a plurality of the second trenches 13 are located between the first trenches 12. It is understood that the first trench 12 and the second trench 13 are each formed by recessing the same side surface of the epitaxial layer 10.
Alternatively, the recess depth of the first trench 12 may be greater than or equal to the recess depth of the second trench 13.
Optionally, at least some of the plurality of second trenches 13 have the same recess depth.
Optionally, a gate structure 20 is disposed in the second trench 13, and the gate structure 20 may include a gate oxide layer 22 and a gate 21. The material of the gate oxide layer 22 may include an oxide. The material of the gate 21 may include polysilicon.
According to the semiconductor device 100 provided in the present application, the semiconductor device 100 includes a cell structure including an epitaxial layer 10, a gate structure 20, and a field plate 30. Providing a plurality of gate structures 20 in the epitaxial layer 10 may increase the over-current area of the gate structures 20, thereby reducing the resistance of the gate structures 20 during operation of the semiconductor device 100. The field plate 30 is disposed around the gate structure 20, so that the dimension of the electric field effect can be increased, and thus the breakdown voltage threshold can be increased, and meanwhile, the resistance of the semiconductor device 100 can be reduced, and thus the conduction loss of the semiconductor device can be reduced, and further, the performance of the semiconductor device 100 can be improved.
In some alternative embodiments, referring to fig. 1, field plate 30 is orthographically projected in a continuous closed pattern along the thickness direction Z of epitaxial layer 10.
Optionally, the orthographic projection shape of the field plate 30 in the thickness direction Z of the epitaxial layer 10 includes a circle, square, rectangle, pentagon, hexagon, or other pattern. The present embodiment exemplifies a hexagonal orthographic projection shape of the field plate 30 in the thickness direction Z.
Optionally, the plurality of cell structures each include a field plate 30, and the plurality of field plates 30 may be disposed independently of each other.
Through the arrangement, the embodiment of the application can further increase the electric field dimension, reduce the resistance of the semiconductor device 100, and reduce the possibility of electric field interference between two adjacent cell structures.
In some alternative embodiments, referring to fig. 1, the number of cell structures includes a plurality, and two adjacent cell structures share a field plate 30.
The plurality of cell structures may be arranged in an array, and the orthographic projection shape of the field plate 30 along the thickness direction Z is illustrated as a hexagon, where the field plate 30 of one cell structure includes six sides, and the local field plate 30 of each side is multiplexed into the field plate 30 of the adjacent cell structure. As an example, one cell structure is adjacent to six cell structures, and this one cell structure is located in the middle of the other six cell structures, and the six sides of the field plate 30 of this one cell structure are also the local field plates 30 of the other six cell structures, respectively.
Through the arrangement, the whole volume of the cellular structure can be reduced, the manufacturing process difficulty of the field plate 30 is reduced, the manufacturing yield is improved, and the manufacturing cost is reduced.
In some alternative embodiments, referring to fig. 2 and 3, the epitaxial layer 10 further includes a body portion 14, the epitaxial portion 11 is disposed on one side of the body portion 14, the number of the epitaxial portions 11 is plural, and the number of the epitaxial portions 11 is configured to correspond to the number of the cell structures.
Optionally, the doping type of the body portion 14 is the same as the doping type of the epitaxial portion 11.
Alternatively, a surface of the body portion 14 on a side facing away from the epitaxial portion 11 may also be provided with a substrate.
Alternatively, the body portion 14 and the extension portion 11 may be fabricated together. As an example, the first trench 12 is formed on the fabricated epitaxial layer 10 by a process such as etching, the region surrounded by the first trench 12 forms the epitaxial portion 11, and the epitaxial layer 10 not etched by the first trench 12 forms the body portion 14 in the thickness direction Z.
Alternatively, the body portion 14 and the epitaxial portion 11 may be manufactured by a plurality of processes. As an example, a plurality of epitaxial portions 11 disposed at intervals are formed on one side surface of the fabricated body portion 14 by an epitaxial growth process or the like, and a space between adjacent two of the epitaxial portions 11 forms the first trench 12.
Alternatively, each cell structure may include one epitaxial portion 11.
Through the arrangement, the embodiment of the application is beneficial to realizing the mass production of the epitaxial part 11, improving the production efficiency and reducing the manufacturing cost.
Fig. 4 is a schematic top view of another semiconductor device according to some embodiments of the present application.
In some alternative embodiments, referring to fig. 1 and 4, a plurality of gate structures 20 are spaced apart along the first direction X; and/or, the plurality of gate structures 20 are distributed at intervals along the second direction Y, and the first direction X, the second direction Y and the thickness direction Z of the epitaxial layer 10 intersect each other.
It is understood that the extending direction and the spacing arrangement of the gate structures 20, that is, the extending direction and the spacing arrangement of the second trenches 13, are explained in the embodiment of the present application with respect to the gate structures 20.
The first direction X, the second direction Y and the thickness direction Z are intersected two by two. Alternatively, the first direction X, the second direction Y, and the thickness direction Z are disposed perpendicular to each other.
As an example, the explanation will be continued taking the orthographic projection shape of the field plate 30 along the thickness direction Z as a regular hexagon, the orthographic projection shape of the gate structure 20 along the thickness direction Z as a rectangle, two opposite sides of the field plate 30 along the first direction X as the first subfield plate 30, and the long sides of the gate structure 20 may be extended along the second direction Y so that the gate structure 20 and the first subfield plate 30 are opposite. Of course, the long sides of the gate structure 20 may also be disposed to extend along the first direction X.
In some examples, the plurality of gate structures 20 are spaced apart along the first direction X, and the long edges of the gate structures 20 extend along the second direction Y. In other examples, the plurality of gate structures 20 are spaced apart along the second direction Y, and the long sides of the gate structures 20 extend along the first direction X. In some other examples, a portion of the gate structures 20 are spaced apart along the first direction X and another portion of the gate structures 20 are spaced apart along the second direction Y.
Through the arrangement, the embodiment of the application is beneficial to guiding carriers to pass through the channel direction with smaller resistance, so that the on-channel resistance is reduced.
Fig. 5 is a schematic top view of another semiconductor device according to some embodiments of the present application. Fig. 6 is a schematic top view of another semiconductor device according to some embodiments of the present application. Fig. 7 is a schematic top view of another semiconductor device according to some embodiments of the present application.
In some alternative embodiments, referring to fig. 5-7, at least some of the plurality of gate structures 20 are disposed to intersect.
Optionally, a plurality of gate structures 20 are all disposed to intersect each other. Or a plurality of gate structures 20 may be disposed in a staggered relationship. Or a portion of the plurality of gate structures 20 may be disposed to intersect each other or to intersect each other.
The plurality of gate structures 20 may be spaced apart along the first direction X and disposed to intersect along the second direction Y. Alternatively, the orthographic projection shape of the plurality of gate structures 20 in the thickness direction Z may include a cross shape, a chevron shape, an i-shape, a well shape, or other shapes.
By the arrangement, the occupied space of the gate structure 20 in the cell structure is increased, so that the conducting channel area of the gate structure 20 in the working process of the semiconductor device 100 is increased.
Fig. 8 is a schematic top view of another semiconductor device according to some embodiments of the present application. Fig. 9 is a schematic cross-sectional view of the structure C-C in fig. 1. Fig. 10 is a schematic cross-sectional view of D-D in fig. 1.
In some alternative embodiments, referring to fig. 8 to 10, the semiconductor device 100 further includes a first metal layer 40, the first metal layer 40 is located on a side of the epitaxial layer 10 away from the doped region 111, the first metal layer 40 includes a connection portion 41, the connection portion 41 extends from the first metal layer 40 toward the side of the epitaxial layer 10 into the epitaxial layer 10, and the doped region 111 and the field plate 30 are both in contact with the connection portion 41.
Alternatively, the first metal layer 40 may be a source metal layer.
Alternatively, the first metal layer 40 may include a conductive body portion 42 and a connection portion 41, and the conductive body portion 42 may be disposed to cover the entire epitaxial layer 10, for example, the coverage area of the conductive body portion 42 is the same as the area of the body portion 14.
Optionally, an insulating dielectric layer is provided between the conductive body portion 42 and the epitaxial layer 10.
Alternatively, the conductive body portion 42 extends into the epitaxial layer 10 in the thickness direction Z toward one side of the epitaxial layer 10 to form the connection portion 41.
Alternatively, the orthographic projection shape of the connecting portion 41 in the thickness direction Z includes a circle, a square, or a rectangle.
Alternatively, in each cell structure, the number of the connection portions 41 may include two or more, and the two or more connection portions 41 are provided on opposite sides of the gate structure 20 in the second direction Y.
Alternatively, taking an example in which the orthographic projection shapes of the field plate 30 and the epitaxial portion 11 in the thickness direction Z are both regular hexagons, orthographic projections of the connection portion 41 in the thickness direction Z overlap orthographic projections of corners of the hexagons of the field plate 30 in the thickness direction Z, and orthographic projections of the connection portion 41 in the thickness direction Z also overlap orthographic projections of corners of the hexagons of the epitaxial portion 11 in the thickness direction Z.
Alternatively, six cell structures are surrounded around one cell structure, the one cell structure includes three pairs of opposite diagonal corners, the field plates 30 of each pair of diagonal corners are provided with connecting portions 41, one pair of the diagonal corners is a connecting portion 41 for contacting the field plates 30 and the doped regions 111 in the one cell structure, and the other two pairs of diagonal corners are connecting portions 41 for contacting the field plates 30 and the doped regions 111 in four cell structures in the six cell structures.
Alternatively, the first doping 1111 and the third doping 1113 are both disposed in contact with the connection portion 41.
In the embodiment of the present application, the field plate 30 and the doped region 111 share one connection portion 41, so as to simplify the structure of the first metal layer 40 and simplify the overall structure of the cell structure.
In some alternative embodiments, referring to fig. 8 to 10, the semiconductor device 100 further includes a second metal layer 50, the first metal layer 40 and the second metal layer 50 are disposed in an insulating manner, and the second metal layer 50 is located between the first metal layer 40 and the epitaxial layer 10, and a side of the plurality of gate structures 20 facing the second metal layer 50 is connected to the second metal layer 50.
Alternatively, the second metal layer 50 may be provided insulated from the connection portion 41 in the first metal layer 40.
Alternatively, the second metal layer 50 may be provided insulated from the conductive body portion 42 in the first metal layer 40.
Optionally, the second metal layer 50 is insulated from the first metal layer 40 by a second insulating dielectric layer 62.
Alternatively, the material of the first metal layer 40 may be the same as the material of the second metal layer 50. Of course, different materials are also possible.
Alternatively, the second metal layer 50 may be a gate metal layer, and the second metal layer 50 is used to electrically connect the gate structure 20 in each cell structure with the outside.
Optionally, a second metal layer 50 is located between the conductive body portion 42 and the epitaxial portion 11.
In other examples, the second metal layer 50 may also be co-layer with the conductive body portion 42 of the first metal layer 40.
Through the above arrangement, the embodiment of the present application is beneficial to reduce the manufacturing difficulty of the first metal layer 40 while ensuring that the gate structure 20 is electrically connected with the outside.
In some alternative embodiments, referring to fig. 8 to 10, the cell structures are arranged in rows along the first direction X and in rows along the second direction Y, the second metal layer 50 includes a plurality of extending conductive portions 51, the plurality of extending conductive portions 51 are spaced apart along the second direction Y, and each extending conductive portion 51 extends along the first direction X, and the gate structure 20 in each row of cell structures is connected to one extending conductive portion 51. The first direction X, the second direction Y, and the thickness direction Z of the epitaxial layer 10 intersect one another.
Optionally, in each cell structure, a plurality of gate structures 20 are spaced apart along the first direction X. The gate structures 20 of the plurality of cell structures on each column are connected to one extended conductive portion 51.
Alternatively, the connection portion 41 is disposed between two adjacent extension conductive portions 51.
It is understood that the gate structure 20 and the extended conductive portion 51 are connected, that is, the surface of the gate 21 facing the side of the extended conductive portion 51 in the gate structure 20 is disposed in contact with the extended conductive portion 51.
It should be noted that, the extending conductive portion 51 extends along the first direction X to cover the field plate 30 and the doped region 111, and in some examples, as shown in fig. 9 and fig. 10, a side of the field plate 30 and the doped region 111 facing the second metal layer 50 is covered with the third insulating dielectric layer 63.
Through the above arrangement, the embodiment of the present application is beneficial to simplifying the arrangement structure of the second metal layer 50 in the semiconductor device 100, facilitating the mass production of the second metal layer 50, and reducing the manufacturing cost of the semiconductor device 100.
Fig. 11 is a schematic top view of a chip according to some embodiments of the present application.
On the other hand, referring to fig. 11, an embodiment of the present application provides a chip 200, where the chip 200 includes the semiconductor device and the integrated circuit 210 in any of the foregoing embodiments. The integrated circuit 210 is electrically connected to the semiconductor device.
It should be noted that, the chip provided in the embodiment of the present application has the beneficial effects of the semiconductor device in any of the foregoing embodiments, and the specific content refers to the foregoing description of the beneficial effects of the semiconductor device, which is not repeated herein.
Optionally, the integrated circuit 210 includes a gate total signal circuit, the semiconductor device includes a first metal layer 40 and a second metal layer 50, the second metal layer 50 includes an extended conductive portion 51, at least a portion of the gate total signal circuit is disposed in the same layer as the first metal layer 40, and the extended conductive portion 51 is electrically connected to the gate total signal circuit through a via 220.
While the present application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the present application. In particular, the technical features mentioned in the respective embodiments may be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions falling within the scope of the claims.

Claims (10)

1. A semiconductor device comprising a cell structure, the cell structure comprising:
the epitaxial layer comprises an epitaxial part and first grooves distributed on the periphery of the epitaxial part, and the epitaxial part comprises a doping area and a plurality of second grooves;
a plurality of gate structures arranged in one-to-one correspondence with the plurality of second trenches;
the field plates are arranged in the first grooves and distributed on the periphery of the grid structure, and the doped regions are located between the grid structure and the field plates.
2. The semiconductor device of claim 1, wherein the orthographic projection of the field plate along the epitaxial layer thickness direction is a continuous closed pattern.
3. The semiconductor device of claim 1, wherein the number of cell structures includes a plurality, and two adjacent cell structures share a field plate.
4. The semiconductor device according to claim 1, wherein the epitaxial layer further includes a body portion, wherein the epitaxial portion is provided on one side of the body portion, wherein the number of epitaxial portions is plural, and wherein the number of epitaxial portions is configured to correspond to the number of cell structures.
5. The semiconductor device of claim 1, wherein a plurality of the gate structures are spaced apart along the first direction; and/or the number of the groups of groups,
the grid structures are distributed at intervals along the second direction, and the first direction, the second direction and the thickness direction of the epitaxial layer are intersected in pairs.
6. The semiconductor device of claim 1, wherein at least some of the plurality of gate structures are disposed to intersect.
7. The semiconductor device of claim 1, further comprising a first metal layer on a side of the epitaxial layer remote from the doped region, the first metal layer including a connection portion extending from the first metal layer into the epitaxial layer toward a side of the epitaxial layer, and the doped region and the field plate both contacting the connection portion.
8. The semiconductor device of claim 7, further comprising a second metal layer, wherein the first metal layer and the second metal layer are disposed in an insulating manner, wherein the second metal layer is located between the first metal layer and the epitaxial layer, and wherein a side of the plurality of gate structures facing the second metal layer is connected to the second metal layer.
9. The semiconductor device of claim 8, wherein the cell structures are arranged in rows along a first direction and in rows along a second direction, the second metal layer includes a plurality of extended conductive portions, the plurality of extended conductive portions are spaced apart along the second direction, and each of the extended conductive portions is disposed to extend along the first direction, the gate structure in each row of cell structures is connected to one extended conductive portion, and the first direction, the second direction, and the thickness direction of the epitaxial layer intersect one another.
10. A chip, comprising:
a semiconductor device according to any one of claims 1 to 9; and
and the integrated circuit is electrically connected with the semiconductor device.
CN202311590176.2A 2023-11-24 2023-11-24 Semiconductor device and chip Pending CN117457718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311590176.2A CN117457718A (en) 2023-11-24 2023-11-24 Semiconductor device and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311590176.2A CN117457718A (en) 2023-11-24 2023-11-24 Semiconductor device and chip

Publications (1)

Publication Number Publication Date
CN117457718A true CN117457718A (en) 2024-01-26

Family

ID=89585489

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311590176.2A Pending CN117457718A (en) 2023-11-24 2023-11-24 Semiconductor device and chip

Country Status (1)

Country Link
CN (1) CN117457718A (en)

Similar Documents

Publication Publication Date Title
TWI550851B (en) Vertical power mosfet including planar channel
US7446375B2 (en) Quasi-vertical LDMOS device having closed cell layout
US7582519B2 (en) Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction
US8022476B2 (en) Semiconductor device having vertical and horizontal type gates and method for fabricating the same
JP7272775B2 (en) insulated gate bipolar transistor
KR20040036914A (en) Trench dmos transistor with embedded trench schottky rectifier
KR20060040592A (en) Semiconductor device having an edge termination structure and method of manufacture thereof
CN107342326B (en) Power semiconductor device capable of reducing on-resistance and manufacturing method thereof
CN101752375B (en) Groove type power MOS device with improved terminal protective structure
US9818743B2 (en) Power semiconductor device with contiguous gate trenches and offset source trenches
CN105706241B (en) MOS bipolar device
US20220384578A1 (en) Semiconductor device
US11264475B2 (en) Semiconductor device having a gate electrode formed in a trench structure
EP0961325B1 (en) High integration density MOS technology power device
CN116741828A (en) Trench gate transistor assembly
CN117457718A (en) Semiconductor device and chip
CN206471335U (en) Super-junction semiconductor device with terminal protection area
CN214542244U (en) IGBT layout structure capable of improving voltage resistance
US20240055498A1 (en) Semiconductor device and method for producing same
CN111916497B (en) Shielded gate power MOSFET with floating electrode and manufacturing method thereof
JPH0621359A (en) Field-effect transistor provided with deep p-type main-body contact source plug
CN201608184U (en) Groove type power MOS device with improved terminal protection structure
US20240136436A1 (en) silicon carbide semiconductor device
CN114725219B (en) Silicon carbide trench gate transistor and method of manufacturing the same
US20230101553A1 (en) Transistor device and method for producing a transistor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination