CN117452190A - Signal testing circuit, method and storage medium - Google Patents
Signal testing circuit, method and storage medium Download PDFInfo
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- CN117452190A CN117452190A CN202311775617.6A CN202311775617A CN117452190A CN 117452190 A CN117452190 A CN 117452190A CN 202311775617 A CN202311775617 A CN 202311775617A CN 117452190 A CN117452190 A CN 117452190A
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- 238000004458 analytical method Methods 0.000 claims abstract description 7
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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Abstract
The application provides a signal testing circuit, a signal testing method and a storage medium. The circuit comprises: the analysis module is used for analyzing the request of the upper computer, wherein the request content at least comprises the information of the signal to be detected; the separation module is used for separating the signal to be detected from other high-speed signals in the circuit to be detected based on the information of the signal to be detected; and the output module is used for constructing an output channel of the signal to be detected based on the position of the signal to be detected and the information of the output interface, so that external equipment can acquire the signal to be detected through the output interface. The problem that debugging can be performed only by disassembling the debugged product is avoided, the process of re-welding the debugged product during debugging is reduced, the risk that the debugged product is damaged due to misoperation is reduced, and therefore the debugging efficiency is improved, and no additional cost is increased.
Description
Technical Field
The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a signal testing circuit, a signal testing method, and a storage medium.
Background
The electronic product internal circuits include a multiplexing circuit (I2C), a bus (SMBUS) signal, etc., which need to be grasped multiple times during the new product introduction (New Product Introduction, NPI) stage to perform debugging (Debug) analysis. In the conventional technology, in a New Product Introduction (NPI) stage, an I2C signal point to be grasped needs to be found in a circuit design file (for example, brd file) of a product to be debugged, three signal lines of a data signal, a clock signal and a ground signal (SDA, SCL and GND) are soldered at the signal point, and then the three signal lines are connected by a test jig to grasp a corresponding signal. That is, at the time of debugging (Debug), it is necessary to disassemble the debugged product for soldering. For small electronic products, the welding difficulty is high, and as the integration level of the system is higher, the board ends are easy to short in the welding process, so that the electronic products are damaged. As can be seen, the debugging (Debug) approach of the conventional technique is time consuming and labor intensive and extremely inefficient. And the damage risk of the debugged product is increased easily due to operations such as disassembly, welding and the like in the debugging (Debug) process.
Disclosure of Invention
The present application has been made in view of at least one of the above-mentioned problems occurring in the prior art. According to an aspect of the present application, there is provided a signal testing circuit, the circuit comprising:
the analysis module is used for analyzing the request of the upper computer, wherein the request content at least comprises the information of the signal to be detected;
the separation module is used for separating the signal to be detected from other high-speed signals in the circuit to be detected based on the information of the signal to be detected;
and the output module is used for constructing an output channel of the signal to be detected based on the position of the signal to be detected and the information of the output interface, so that external equipment can acquire the signal to be detected through the output interface.
In some embodiments, the parsing module is further to:
based on a first preset protocol, a request for acquiring a signal to be detected, which is sent by an upper computer, is received, wherein the request at least comprises a request type, a request parameter and a request identifier.
In some embodiments, the parsing module is further to:
and based on a second preset protocol, sending the request content obtained through analysis to the separation module.
In some embodiments, the request content further includes a request parameter, the request parameter including a number of the output interface;
in some embodiments, the output module further comprises a selection module; the selection module is used for selecting the output interface for the signal to be detected based on the number of the output interface; wherein the selection module comprises a multiplexing circuit.
In some embodiments, the output interface comprises a universal serial bus interface.
In another aspect, an embodiment of the present application provides a signal testing method, where the method includes:
responding to a request sent by an upper computer, analyzing the request of the upper computer, wherein the request content at least comprises information of a signal to be detected;
separating the signal to be detected from other high-speed signals in the circuit to be detected based on the information of the signal to be detected;
and constructing an output channel of the signal to be detected based on the position of the signal to be detected and the information of the output interface, so that external equipment can acquire the signal to be detected through the output interface.
In some embodiments, the method further comprises: based on a first preset protocol, a request for acquiring a signal to be detected, which is sent by an upper computer, is received, wherein the request information includes a request type, a request parameter and a request identifier.
In some embodiments, the request parameter includes a number of the output interface; the method further comprises the steps of: and selecting the output interface for the signal to be tested based on the number of the output interface.
Yet another aspect of the present embodiments provides a storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform a signal testing method as described above.
According to the signal testing circuit, the request of the upper computer is analyzed, based on the information of the signal to be tested, the signal to be tested is separated from other high-speed signals in the circuit to be tested, and the output channel of the signal to be tested is constructed based on the position of the signal to be tested and the information of the output interface, so that the external equipment can acquire the signal to be tested through the output interface, the problem that debugging can be conducted only by disassembling a debugged product is avoided, the process of re-welding the debugged product during debugging is reduced, the risk that the debugged product is damaged due to misoperation is reduced, the debugging efficiency is improved, and no additional cost is increased.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 shows a schematic block diagram of a signal testing circuit according to an embodiment of the present application;
FIG. 2 (a) is a schematic diagram showing the connection relationship of pins of a dedicated multiplexing chip according to an embodiment of the present application;
FIG. 2 (b) shows a schematic diagram of a dedicated multiplexing chip according to an embodiment of the present application;
FIG. 2 (c) shows a schematic diagram of pin descriptions of a dedicated multiplexing chip according to an embodiment of the application;
FIG. 3 shows a schematic diagram of a signal testing circuit according to another embodiment of the present application;
FIG. 4 shows a schematic flow chart of a signal testing method according to one embodiment of the present application;
fig. 5 shows a schematic flow chart of a signal testing method according to another embodiment of the present application.
Detailed Description
In order to better understand the technical solutions of the embodiments of the present application, the following descriptions will clearly and completely describe the technical solutions of the embodiments of the present application with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Based on at least one technical problem as described above, the present application provides a signal testing circuit, the circuit comprising: the analysis module is used for analyzing the request of the upper computer, wherein the request content at least comprises the information of the signal to be detected; the separation module is used for separating the signal to be detected from other high-speed signals in the circuit to be detected based on the information of the signal to be detected; and the output module is used for constructing an output channel of the signal to be detected based on the position of the signal to be detected and the information of the output interface, so that external equipment can acquire the signal to be detected through the output interface. The problem that debugging can be performed only by disassembling the debugged product is avoided, the process of re-welding the debugged product during debugging is reduced, the risk that the debugged product is damaged due to misoperation is reduced, and therefore the debugging efficiency is improved, and no additional cost is increased.
FIG. 1 shows a schematic block diagram of a signal testing circuit according to an embodiment of the present application; as shown in fig. 1, a signal testing circuit 100 according to an embodiment of the present application may include a parsing module 101, a separating module 102, and an output module 103.
The parsing module 101 is configured to parse a request of the host computer, where the content of the request at least includes information of a signal to be tested.
The separation module 102 is configured to separate the signal to be tested from other high-speed signals in the circuit to be tested based on the information of the signal to be tested. The embodiment of the application can separate the I2C signal from other high-speed signals in the circuit to be tested when the circuit is arranged (layout). For example, ground plane shielding and/or impedance matching methods may be employed, which may further ensure the reliability of the signal under test.
The output module 103 is configured to construct an output channel of the signal to be tested based on the position of the signal to be tested and information of an output interface, so that an external device collects the signal to be tested through the output interface.
In an embodiment of the present application, the parsing module is further configured to receive a request for obtaining a signal to be tested sent by an upper computer based on a first preset protocol, where the request at least includes a request type, a request parameter, and a request identifier.
For example, the first preset protocol may include an advanced configuration and power management interface (Advanced Configuration and Power Management Interface, ACPI) protocol, or a system management basic input output system (System Management BIOS, SMBIOS) protocol.
When a request is sent to a debugged product, the upper computer generally receives the request by a basic input output system (Basic Input Output System, BIOS) of the debugged product based on an ACPI protocol or an SMBIOS protocol, and then analyzes the request to obtain the content of the request.
The request may include, among other things, a request type, a request parameter, and a request identification. For example, the request type is modifying the status of the general input output interface, the request parameters are the number of the output interface and the new status value, the request is identified as the number of the request (Identity document, ID).
In an embodiment of the present application, the parsing module is further configured to send the request content obtained by parsing to the separation module based on a second preset protocol.
For example, the second preset protocol may include an embedded controller boot resource table (Embedded Controller Boot Resources Table, ECDT).
In one embodiment of the present application, the request content further includes a request parameter, and the request parameter includes a number of the output interface. For example, YA and YB pins.
In one embodiment of the present application, the output module further includes a selection module; the selection module is used for selecting the output interface for the signal to be detected based on the number of the output interface; wherein the selection module comprises a multiplexing circuit.
In one example, embodiments of the present application may employ a dedicated multiplexing (mux) chip that does not skew the I2C signal when in use. For example, a PIUSB 14-A chip may be used by a company. The PIUSB 14-A chip. The main function of the chip is to select corresponding signals to be output to the YA/YB pins by controlling the pin level, and the chip can support switching of 4 paths of signals at maximum.
In one embodiment of the application, the output interface comprises a universal serial bus interface (Universal Serial Bus, USB).
Because the universal serial bus interface is a relatively common interface, in the embodiment of the application, a debugged product can be connected with the logic analyzer through the universal serial bus interface, then a signal to be tested is switched to the universal serial bus interface, and then the logic analyzer grabs the signal to be tested by the universal serial bus interface, so that the signal to be tested can be quickly tested (debug) without disassembling the debugged product.
Fig. 2 (a) is a schematic diagram illustrating connection relationships between pins of a dedicated multiplexing chip according to an embodiment of the present application. The chip comprises the following pins: IA (IA) 0 To IA 3 、IB 0 To IB (IB) 3 、EN、S 0 、S 1 、Y A 、Y B . The pins are connected through Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
Fig. 2 (b) is a schematic diagram of a dedicated multiplexing chip according to an embodiment of the present application. The left figure shows a dedicated multiplexing chip with 16-way pins. The right figure shows a special multiple multiplexing chip with 20 pins. In the left panel, the numbers of the pins are as follows: EN pin number 1, S 0 The number of the pins is 14, S 1 The number of the pins is 2 and Y A The number of the pins is 7 and Y B The pins are numbered 9, IA 0 The pins are numbered 6, IA 1 The pin number is 5, IA 2 The pins are numbered 4, IA 3 The pins are numbered 3, IB 0 The pins are numbered 10, IB 1 The pins are numbered 11, IB 2 The pins are numbered 12, IB 3 The number of the pins is 13, and the ground pins (GND) are wovenNumber 8. In the right figure, the numbers of the pins are as follows: EN pin number 2, S 0 The serial number of the pin is 11, S 1 The number of the pins is 3 and Y A The number of the pins is 8 and Y B The pins are numbered 12, IA 0 The pins are numbered 7, IA 1 The pins are numbered 6, IA 2 The pin number is 5, IA 3 The pins are numbered 4, IB 0 The pins are numbered 13, IB 1 The pins are numbered 14, IB 2 The pins are numbered 15, IB 3 The pin number is 16 and the ground pin (GND) number is 10. Wherein, the 1 st pin, the 9 th pin and the 11 th pin have no internal connection (No internal connection, N.C).
The pin numbers of different special multiplexing chips are different, so when the upper computer sends a request to a debugged product, the request content needs to comprise a request parameter, and the pin numbers need to be specified in the request parameter. For example the number of output interfaces is (7.9) or the number of output interfaces is (8, 12).
As shown in fig. 2 (c), a schematic diagram is depicted for each pin of the dedicated multiplexing chip. IA (IA) 0 To IA 3 、IB 0 To IB (IB) 3 Represents the data input pin, EN represents the enable signal pin, S 0 And S is 1 Representing the select input pin, Y A 、Y B Represents data output, GND represents a ground pin, V DD Representing the power supply pins.
The truth table of the output signals of the pins of the special multiplexing chip is shown in the following table 1:
when the EN pin is high (H), the special multiplexing chip is not on-chip. When EN pin is at low level (L), the special multiplexing chip can use X in table 1, Y represents the output terminal, hi-Z represents the high resistance state, I0, I1, I2, I3 represents the input signal, s1—s0=0 represents 0 of decimal corresponding to binary number composed of S1, S0, s1—s0=1 represents 10 of decimal corresponding to binary number 01 composed of S1, S0, s1—s0=2 represents 2 of decimal corresponding to binary number 10 composed of S1, S0, s1—s0=3 represents 3 of decimal corresponding to binary number 11 composed of S1, S0 (note, here "-" is not minus sign, but connection number).
Fig. 3 is a schematic diagram of a signal testing circuit according to another embodiment of the present application. The power supply voltage of the dedicated multiplexing chip in FIG. 3 is 5V, R 1 Representing the pull-up resistance. The general purpose input/output interfaces GPIO1 and GPIO2 of the Embedded Controller (EC) receive the analyzed request content (comprising the signal to be tested) and send the request content to S 0 And S is 1 Pins. The signal to be measured can be obtained by IA 0 And IB (group B) 0 、IA 1 And IB (group B) 1 、IA 2 And IB (group B) 2 、IA 3 And IB (group B) 3 These four sets of pins are then input by S 0 And S is 1 The pins select one group from the four groups of pins to be matched with Y A 、Y B Turned on and pass through Y A 、Y B And outputting.
Y can be seen in FIG. 3 A 、Y B And the D+ and D-pins of the USB female interface (USB-A) are connected, so that signals to be detected are output through the USB interface.
The circuit of the embodiment of the application is as follows, the Embedded Controller (EC) selects the signal to be debugged, the circuit (I2C) signal is switched to the D+ and D-pin of the USB female port (USB-A) interface through the 4-to-1 multiplexing chip, the signal to be debugged can be quickly debugged without disassembling the machine by directly grabbing the signal to be debugged from the USB-A interface through the logic analyzer. In the NPI phase, R can be 2 、R 3 The resistance value is set to 0 ohm, R can be set after the NPI stage is finished 2 、R 3 The resistance value of (ase:Sub>A) is set to ase:Sub>A normal value so that the USB female interface (USB-A) performs normal datase:Sub>A transmission.
According to the signal testing circuit, the request of the upper computer is analyzed, based on the information of the signal to be tested, the signal to be tested is separated from other high-speed signals in the circuit to be tested, and the output channel of the signal to be tested is constructed based on the position of the signal to be tested and the information of the output interface, so that the external equipment can acquire the signal to be tested through the output interface, the problem that debugging can be conducted only by disassembling a debugged product is avoided, the process of re-welding the debugged product during debugging is reduced, the risk that the debugged product is damaged due to misoperation is reduced, the debugging efficiency is improved, and no additional cost is increased.
The signal testing method of the present application is described below with reference to fig. 4. Wherein fig. 4 shows a schematic flow chart of a signal testing method according to an embodiment of the present application. The method comprises the steps of S401, 402 and 403:
in step S401, in response to the request sent by the upper computer, the request of the upper computer is parsed, wherein the content of the request at least includes information of the signal to be tested.
In step S402, the signal to be tested is separated from other high-speed signals in the circuit to be tested based on the information of the signal to be tested.
In step S403, an output channel of the signal to be measured is constructed based on the position of the signal to be measured and the information of the output interface, so that the external device collects the signal to be measured through the output interface.
In one embodiment of the present application, the method further comprises: based on a first preset protocol, a request for acquiring a signal to be detected, which is sent by an upper computer, is received, wherein the request information includes a request type, a request parameter and a request identifier.
For example, the first preset protocol may include an advanced configuration and power management interface (Advanced Configuration and Power Management Interface, ACPI) protocol, or a system management basic input output system (System Management BIOS, SMBIOS) protocol.
In one embodiment of the present application, the request parameter includes a number of the output interface; the method further comprises the steps of: and selecting the output interface for the signal to be tested based on the number of the output interface. For example, the output interfaces are numbered YA and YB.
In another embodiment of the present application, as shown in fig. 5, a schematic flow chart of a signal testing method according to another embodiment of the present application is provided. The signal testing method comprises the steps of step S501, step 502, step 503, step 504, step 505 and step 506:
in step S501, the host selects the need to debug the I2C signal.
In step S502, the upper computer generates a request and packages the request into a data packet.
The data packet of the embodiment of the application generally includes information such as a request type, a request parameter, a request identifier, and the like. For example, in the case of modifying the GPIO state, the request type may be "modify GPIO state", and the request parameter may include the number of GPIO, or the like.
In step S503, the upper computer sends the data packet to the BIOS of the debugged product through ACPI or SMBIOS protocol.
After receiving the request, the BIOS of the embodiment of the application analyzes the request data packet by using a corresponding protocol, and executes corresponding operation according to the request type and parameters.
In step S504, the BIOS sends a request to the EC based on the ECDT protocol.
The ECDT here is a standardized protocol for data exchange between the BIOS and the EC.
In step S505, the EC parses the request and then modifies the state of the corresponding GPIO.
In step S506, the MUX chip switches the output interface to the corresponding I2C signal according to the GPIO setting.
According to the signal testing circuit, the request of the upper computer is analyzed, based on the information of the signal to be tested, the signal to be tested is separated from other high-speed signals in the circuit to be tested, and the output channel of the signal to be tested is constructed based on the position of the signal to be tested and the information of the output interface, so that the external equipment can acquire the signal to be tested through the output interface, the problem that debugging can be conducted only by disassembling a debugged product is avoided, the process of re-welding the debugged product during debugging is reduced, the risk that the debugged product is damaged due to misoperation is reduced, the debugging efficiency is improved, and no additional cost is increased.
Furthermore, according to an embodiment of the present application, there is also provided a storage medium on which program instructions are stored, which program instructions, when executed by a computer or a processor, are adapted to carry out the respective steps of the signal testing method of the embodiments of the present application. The storage medium may include, for example, a memory card of a smart phone, a memory component of a tablet computer, a hard disk of a personal computer, read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, or any combination of the foregoing storage media.
The signal testing method and the storage medium of the embodiment of the application have the same advantages as the signal testing circuit because the signal testing circuit can be realized.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above illustrative embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as set forth in the appended claims.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another device, or some features may be omitted or not performed.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in order to streamline the application and aid in understanding one or more of the various inventive aspects, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the application. However, the method of this application should not be construed to reflect the following intent: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be combined in any combination, except combinations where the features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some of the modules according to embodiments of the present application may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present application may also be embodied as device programs (e.g., computer programs and computer program products) for performing part or all of the methods described herein. Such a program embodying the present application may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
The foregoing is merely illustrative of specific embodiments of the present application and the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A signal testing circuit, the circuit comprising:
the analysis module is used for analyzing the request of the upper computer, wherein the request content at least comprises the information of the signal to be detected;
the separation module is used for separating the signal to be detected from other high-speed signals in the circuit to be detected based on the information of the signal to be detected;
and the output module is used for constructing an output channel of the signal to be detected based on the position of the signal to be detected and the information of the output interface, so that external equipment can acquire the signal to be detected through the output interface.
2. The circuit of claim 1, wherein the parsing module is further configured to:
based on a first preset protocol, a request for acquiring a signal to be detected, which is sent by an upper computer, is received, wherein the request at least comprises a request type, a request parameter and a request identifier.
3. The circuit of claim 1, wherein the parsing module is further configured to:
and based on a second preset protocol, sending the request content obtained through analysis to the separation module.
4. The circuit of claim 1, wherein the request content further comprises a request parameter, the request parameter comprising a number of the output interface.
5. The circuit of claim 4, wherein the output module further comprises a selection module; the selection module is used for selecting the output interface for the signal to be detected based on the number of the output interface; wherein the selection module comprises a multiplexing circuit.
6. The circuit of claim 1, wherein the output interface comprises a universal serial bus interface.
7. A method of signal testing, the method comprising:
responding to a request sent by an upper computer, analyzing the request of the upper computer, wherein the request content at least comprises information of a signal to be detected;
separating the signal to be detected from other high-speed signals in the circuit to be detected based on the information of the signal to be detected;
and constructing an output channel of the signal to be detected based on the position of the signal to be detected and the information of the output interface, so that external equipment can acquire the signal to be detected through the output interface.
8. The method of claim 7, wherein the method further comprises: based on a first preset protocol, a request for acquiring a signal to be detected, which is sent by an upper computer, is received, wherein the request information includes a request type, a request parameter and a request identifier.
9. The method of claim 8, wherein the request parameter comprises a number of the output interface; the method further comprises the steps of: and selecting the output interface for the signal to be tested based on the number of the output interface.
10. A storage medium having stored thereon a computer program which, when executed by a processor, performs the signal testing method of any of claims 7 to 9.
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