CN117438473A - Novel N-column super-junction structure lateral diffusion metal oxide semiconductor - Google Patents

Novel N-column super-junction structure lateral diffusion metal oxide semiconductor Download PDF

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Publication number
CN117438473A
CN117438473A CN202311664273.1A CN202311664273A CN117438473A CN 117438473 A CN117438473 A CN 117438473A CN 202311664273 A CN202311664273 A CN 202311664273A CN 117438473 A CN117438473 A CN 117438473A
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region
drift
type
pillar
doped
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CN202311664273.1A
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许凯
蔡豪
黄贇
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ZJU Hangzhou Global Scientific and Technological Innovation Center
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ZJU Hangzhou Global Scientific and Technological Innovation Center
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The utility model provides a novel N post super junction structure lateral diffusion metal oxide semiconductor, mainly include the silicon substrate, P class Drift concentration doped region, high concentration doped P type district, the source region, drift region, the grid, the drain region, through the overall arrangement of PN junction with the help of its high withstand voltage characteristic, reduce on resistance and exert an influence, reach the super junction structure of punching through and make PN interval can realize the effect of totally depleting, simultaneously, through the lateral length adjustment breakdown voltage of the high concentration doped P type district that the N Drift post has encircled with it, still through the quantity of adjusting the N Drift post or the concentration of the high concentration doped P type district that the N Drift post is encircled with it simultaneously adjustment breakdown voltage and reduction on resistance, make the electric charge of Drift region totally deplete before the breakdown.

Description

Novel N-column super-junction structure lateral diffusion metal oxide semiconductor
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a novel N-column super-junction structure lateral diffusion metal oxide semiconductor.
Background
A laterally diffused metal oxide semiconductor, i.e., a laterally bipolar diffused field effect transistor (LDMOS), is a high voltage device for integrated circuits. LDMOS is a power device of double-diffused structure. The technology is to implant two times in the same source/drain region, one implantation concentration is larger (typical implantation dosage10 15 cm -2 ) Another implant with a smaller concentration (typical implant dose 10 13 cm -2 ) Boron (B) of (B). After implantation, a high temperature drive-in process is performed, and boron diffuses more rapidly than arsenic, so that a channel with a concentration gradient is formed under the boundary of the grid and the channel length is determined by the difference between the two lateral diffusion distances. By precisely controlling the diffusion time and diffusion temperature, the channel dimensions of the device can be precisely controlled. In order to increase the breakdown voltage, a drift region is provided between the active region and the drain region. The drift region in the LDMOS is the key of the design of the device, and the impurity concentration of the drift region is relatively low, so that when the LDMOS is connected with high voltage, the drift region can bear higher voltage due to high resistance.
As a voltage controlled current mode device, LDMOS has a large input impedance and therefore low power consumption in driving applications, and is easy to couple with a pre-stage circuit. In addition, as the LDMOS has the negative temperature characteristic, and the current carrier transversely flows on the surface, when the temperature is higher, the leakage current can automatically flow uniformly, so that local hot spots are not easy to form, and the reliability is higher. The source electrode, the drain electrode and the grid electrode are all positioned on the surface of the chip and can be contacted with an internal well or conveniently integrated with a low-voltage signal circuit, so that the LDMOS device is very suitable to be used as a power output device in a power chip.
The capability of the traditional power LDMOS to bear high voltage when turned off is mainly determined by a lightly doped N drift region with a certain length, wherein the voltage-resistant part is a unilateral abrupt junction PiN of a P+/N-N+ structure. In order to increase the breakdown voltage of the device, it is necessary to increase the length of the drift region and decrease the doping concentration of the drift region. However, these changes have an effect on the on-resistance of the device, resulting in a certain contradictory relationship between breakdown voltage and on-resistance.
Disclosure of Invention
Aiming at the problems and technical requirements existing in the prior art, the invention aims to provide a novel N-column super-junction structure lateral diffusion metal oxide semiconductor, and the on-resistance is reduced to generate influence by adjusting the layout of PN junctions of a drift region.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
a novel N-pillar super-junction structure lateral diffusion metal oxide semiconductor comprises a silicon substrate, a P-type Drift concentration doped region, a high-concentration doped P-type region, a source region, a Drift region, a grid electrode and a drain region;
the source region consists of a P+ type heavily doped region and an N+ type heavily doped region;
the Drift region consists of an N-type higher-concentration doped column (N Drift column) and is surrounded by a high-concentration doped P-type region;
forming a conductive channel above the P-type Drift concentration doped region and between the source region N+ type region and the high-concentration doped P-type region;
a gate electrode adjacent to the insulating layer and above the conductive channel;
the drain region consists of an N+ type heavily doped region;
the gate and drain regions are connected by an N Drift column and a heavily doped P-type region surrounding the N Drift column.
The silicon substrate adopts a P-type epitaxial substrate and is a cavity structure doped with redundant positive charge carrier semiconductor substrates.
The N-type higher concentration doped column (N Drift column) adopts a vertical parallel connection mode.
The occupied area ratio of the N-type higher concentration doped column (N Drift column) to the occupied area ratio of the high concentration doped P-type region is 1:1.
The doping concentration of the N-type higher-concentration doping column (N Drift column) is the same as that of the high-concentration doped P-type region.
The source region, the drift region and the drain region are led out and are conducted.
And a P-type higher-concentration doped column (P Drift column) is vertically added into the Drift region, and the N Drift column and the P Drift column are manufactured into a curve winding structure.
Compared with the prior art, the invention has the beneficial effects that:
according to the novel N-column super-junction structure transverse diffusion metal oxide semiconductor, the PN junction layout of a Drift region is adjusted by means of the high voltage-withstanding characteristic, the breakdown voltage and the lower on resistance are improved, an N Drift column is surrounded by a high-concentration doped P-type region different from the substrate doping concentration, the effect that the PN interval can be completely depleted is achieved through the super-junction structure, the breakdown voltage is adjusted by adjusting the transverse length of the high-concentration doped P-type region which the N Drift column surrounds, and meanwhile the breakdown voltage is adjusted and the on resistance is reduced by adjusting the number of the N Drift column or simultaneously adjusting the concentrations of the N Drift column and the high-concentration doped P-type region which the N Drift column surrounds, so that the charge of the Drift region is completely depleted before avalanche breakdown.
The foregoing description is only an overview of the present invention, and in order that the present invention may be more clearly understood by reference to the following description, the present invention will be described in more detail with reference to the accompanying drawings.
The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art from the following detailed description of the specific embodiments of the present invention taken in conjunction with the accompanying drawings, which are not to be construed as limiting the invention.
Drawings
FIG. 1 is a block diagram of the present invention;
wherein: 1. a silicon substrate; 2. a P-type Drift concentration doped region; 3. a source region; 4. a drift region; 5. a gate; 6. and a drain region.
Detailed Description
The present invention will be described more fully hereinafter in order to facilitate an understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The following detailed description of the embodiments of the invention is provided with reference to the accompanying drawings.
As shown in the figure 1, the novel N-column super-junction structure lateral diffusion metal oxide semiconductor comprises a silicon substrate 1, a P-type Drift concentration doped region 2, a high-concentration doped P-type region, a source region 3, a Drift region 4, a grid electrode 5 and a drain region 6;
the source region consists of a P+ type heavily doped region and an N+ type heavily doped region;
the Drift region consists of an N-type higher-concentration doped column (N Drift column) and is surrounded by a high-concentration doped P-type region;
in this application, drift region generally refers to a region with special charge doping for forming a channel for current transport in the device, which means that this region is mainly composed of additional free electrons when the drift region is of the N-type. Electrons of the N-type semiconductor are the main charge carriers, so that in the N-type Drift region, current is mainly formed by free electron flow, charge balance between the P-type region doped with high concentration and the Drift region is ensured so that complete depletion can be realized at PN intervals before breakdown voltage is reached, net residual charge drops sharply to be almost zero, the P-type region doped with high concentration and the Drift region are directly depleted, electric potential is distributed more uniformly in the Drift region, an electric field of the P-type region doped with high concentration and the Drift region in the transverse direction is gentle, a voltage peak value drops, and the N-Drift region has lower on-resistance compared with a common N-Drift region.
Forming a conductive channel above the P-type Drift concentration doped region and between the source region N+ type region and the high-concentration doped P-type region;
in the application, when the gate-source voltage is larger than the starting voltage, electrons can be transported from the source region to the drain region.
A gate electrode adjacent to the insulating layer and above the conductive channel;
the drain region consists of an N+ type heavily doped region;
the gate and drain regions are connected by an N Drift column and a heavily doped P-type region surrounding the N Drift column.
The silicon substrate adopts a P-type epitaxial substrate and is a cavity structure doped with redundant positive charge carrier semiconductor base.
Wherein the base portion of the silicon substrate semiconductor is P-type, "P" representing a positive type, the P-type base having different electron flow properties than the N-type base, in which electrons move from the hole structure instead of from free electrons.
The N-type higher concentration doped column (N Drift column) adopts a vertical parallel connection mode, so that the resistance of the N-type higher concentration doped column is reduced.
The ratio of the area occupied by the N-type higher concentration doped column (N Drift column) to the area occupied by the high concentration doped P-type region is 1:1.
The doping concentration of the N-type higher concentration doped column (N Drift column) is the same as the doping concentration of the P-type region of the high concentration doping.
The source region, the drift region and the drain region are led out and are set to be conducted, namely metal electrodes, which are used for conducting voltage and controlling functions and use of the device.
And a P-type higher-concentration doped column (P Drift column) is vertically added into the Drift region, and the N Drift column and the P Drift column are manufactured into a curve winding structure. The introduction of the increased PN junction causes the charge of the drift region to be fully depleted prior to avalanche breakdown.
The technical features of the above examples may be arbitrarily combined, and all possible combinations of the technical features in the above examples are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that several variations and insubstantial modifications could be made by those skilled in the art without departing from the spirit of the invention, which would still fall within the scope of the invention. Accordingly, the scope of the invention should be assessed as that of the appended claims.

Claims (7)

1. The novel N-column super-junction structure lateral diffusion metal oxide semiconductor is characterized by comprising a silicon substrate (1), a P-type Drift concentration doped region (2), a high-concentration doped P-type region, a source region (3), a Drift region (4), a grid electrode (5) and a drain region (6);
the source region consists of a P+ type heavily doped region and an N+ type heavily doped region;
the Drift region consists of an N-type higher-concentration doped column (N Drift column) and is surrounded by a high-concentration doped P-type region;
forming a conductive channel above the P-type Drift concentration doped region and between the source region N+ type region and the high-concentration doped P-type region;
a gate electrode adjacent to the insulating layer and above the conductive channel;
the drain region consists of an N+ type heavily doped region;
the gate and drain regions are connected by an N Drift column and a heavily doped P-type region surrounding the N Drift column.
2. The novel N-pillar superjunction structure laterally diffused metal oxide semiconductor of claim 1, wherein said silicon substrate is a P-type epitaxial substrate, and is a hole structure doped with an excess positive charge carrier semiconductor base.
3. The novel N-pillar superjunction structure lateral diffusion metal oxide semiconductor of claim 1, wherein said N-type higher concentration doped pillar (N Drift pillar) is in a vertical parallel connection.
4. The novel N-pillar superjunction structure laterally diffused metal oxide semiconductor of claim 1, wherein the ratio of the area occupied by the N-type higher concentration doped pillar (N Drift pillar) to the area occupied by the high concentration doped P-type region is 1:1.
5. The novel N-pillar superjunction structure lateral diffusion metal oxide semiconductor of claim 1, wherein the doping concentration of the N-type higher concentration doped pillar (N Drift pillar) is the same as the doping concentration of the high concentration doped P-type region.
6. The novel N-pillar superjunction structure laterally diffused metal oxide semiconductor of claim 1, wherein the source region, the drift region, and the drain region are conducted.
7. The novel N-pillar superjunction structure laterally diffused metal oxide semiconductor of any of claims 1-6, wherein P-type higher concentration doped pillars (P Drift pillars) are vertically added to the Drift region, and the NDrift pillars and the P Drift pillars are fabricated into a curved winding structure.
CN202311664273.1A 2023-12-06 2023-12-06 Novel N-column super-junction structure lateral diffusion metal oxide semiconductor Pending CN117438473A (en)

Priority Applications (1)

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CN202311664273.1A CN117438473A (en) 2023-12-06 2023-12-06 Novel N-column super-junction structure lateral diffusion metal oxide semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311664273.1A CN117438473A (en) 2023-12-06 2023-12-06 Novel N-column super-junction structure lateral diffusion metal oxide semiconductor

Publications (1)

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CN117438473A true CN117438473A (en) 2024-01-23

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