CN117436323A - Fault injection sensitive node extraction method, device, equipment and medium - Google Patents
Fault injection sensitive node extraction method, device, equipment and medium Download PDFInfo
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- 238000002347 injection Methods 0.000 title claims abstract description 180
- 239000007924 injection Substances 0.000 title claims abstract description 180
- 238000000605 extraction Methods 0.000 title claims description 12
- 238000004088 simulation Methods 0.000 claims abstract description 176
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- 238000004377 microelectronic Methods 0.000 claims abstract description 38
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- 230000001052 transient effect Effects 0.000 claims description 25
- 238000004891 communication Methods 0.000 claims description 12
- 230000002787 reinforcement Effects 0.000 claims description 10
- 238000013461 design Methods 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 6
- 230000003014 reinforcing effect Effects 0.000 claims description 6
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- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
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Abstract
The invention discloses a method, a device, equipment and a medium for extracting a sensitive node of fault injection, which relate to the technical field of single event effect and are used for solving the problem that the existing method cannot reflect the real working condition. The method comprises the following steps: acquiring circuit information and total simulation times of the microelectronic device to be tested; aiming at any single event effect simulation, the number of injection nodes of the simulation and the fault information to be injected are obtained; randomly selecting fault injection nodes in the node file according to the number of the injection nodes; simulating based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process; determining the node as a sensitive node, and recording the turnover times; and after N times of simulation, obtaining all sensitive nodes corresponding to the microelectronic device to be tested. The method for extracting the sensitive node of the fault injection is used for truly simulating the single event effect response condition of the circuit in the space radiation environment.
Description
Technical Field
The present invention relates to the field of single event effect technologies, and in particular, to a method, an apparatus, a device, and a medium for extracting a sensitive node for fault injection.
Background
Satellites and spacecraft in orbit will inevitably be irradiated with a plurality of charged particles. The charged particles in space may produce radiation effects under interaction with electronic components on the satellite, causing varying degrees of damage to the satellite, thereby threatening safe operation of the satellite. The series of effects that spatial irradiation produces on microelectronic devices is commonly referred to as the single event effect. SEE is a key factor in the normal operation and life of satellites. Thus, the microelectronic device should be tested before application to the satellite. The most accurate method of analysing the effect of radiation on integrated circuits known today is to use a device-level TCAD simulator that supports 3D modeling of the interaction between the impact moment transistor and the ionising particles. This strategy, while accurate, is not typically used to simulate large circuits because the models employed are time consuming, and circuit level simulations are used to better understand the behavior of the circuit under soft errors.
At present, a method for carrying out single event effect simulation by adopting a circuit level only carries out injection of one fault node, and the effect of a plurality of single event nodes on a microelectronic device usually occurs in a real environment, and the existing method cannot reflect the real working condition, so that simulation data is inaccurate. In addition, the existing single event effect simulation is simply carried out, and the specific node which needs to be reinforced cannot be known according to the result, so that the subsequent microelectronic device design is not facilitated.
Disclosure of Invention
The invention aims to provide a method, a device, equipment and a medium for extracting a sensitive node of fault injection, which are used for truly simulating the single event effect response condition of a circuit in a space radiation environment, and the simulation circuit is influenced by single event to trigger a multi-bit overturning condition, so that a basis is provided for the single event effect reinforcement theory of an integrated circuit from a design link, and the irradiation resistance index of a chip is improved.
In order to achieve the above object, the present invention provides the following technical solutions:
in a first aspect, the present invention provides a method for extracting a sensitive node of fault injection, including:
acquiring circuit information and total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
aiming at any single event effect simulation, the number of injection nodes of the simulation and the fault information to be injected are obtained; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
performing single event effect simulation based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
determining one or more nodes with overturn as sensitive nodes, and recording overturn times;
and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested.
Compared with the prior art, the method for extracting the sensitive node of the fault injection comprises the following steps:
acquiring circuit information and total simulation times of the microelectronic device to be tested; in any single event effect simulation, the number of injection nodes of the simulation and the fault information to be injected are obtained; the number of the injection nodes is at least two; the single event effect response condition of the circuit under the space radiation environment can be simulated more truly, when the total node number in the node file is at least three times of the injection node number, the fault injection node is randomly selected in the node file according to the injection node number, and all nodes of the whole circuit do not need to be traversed through a law of large numbers, so that the efficiency is high; performing single event effect simulation based on the fault injection nodes, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process; determining one or more nodes with overturn as sensitive nodes, and recording overturn times; and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested. The anti-interference performance of the microelectronic device can be determined through the recorded sensitive nodes and the turnover times, and a basis is provided for the single event effect reinforcing nodes of the microelectronic device.
In a second aspect, the present invention further provides a device for extracting a sensitive node of fault injection, including:
the circuit information and total simulation times acquisition module is used for acquiring the circuit information and the total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
the system comprises an injection node and a fault information acquisition module to be injected, wherein the injection node and the fault information acquisition module to be injected are used for simulating any single event effect to acquire the number of the injection nodes and the fault information to be injected of the simulation; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
the fault injection node selection module is used for randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
the single event effect simulation module is used for carrying out single event effect simulation based on the fault injection nodes, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
the sensitive node determining module is used for determining one or more nodes with overturn as sensitive nodes and recording overturn times;
and the circulation simulation module is used for obtaining all sensitive nodes corresponding to the microelectronic device to be tested after completing N times of simulation.
In a third aspect, the present invention provides a fault injection sensitive node extraction apparatus, including:
the communication unit/communication interface is used for acquiring circuit information and total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
the processing unit/processor is used for acquiring the number of the injection nodes and the fault information to be injected of the simulation aiming at any single event effect simulation; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
performing single event effect simulation based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
determining one or more nodes with overturn as sensitive nodes, and recording overturn times;
and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested.
In a fourth aspect, the present invention provides a computer storage medium having instructions stored therein, which when executed, implement the above-described fault injection sensitive node extraction method.
Technical effects achieved by the apparatus class scheme provided in the second aspect, the device class scheme provided in the third aspect, and the computer storage medium scheme provided in the fourth aspect are the same as those achieved by the method class scheme provided in the first aspect, and are not described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a flow chart of a method for extracting a sensitive node by fault injection provided by the invention;
fig. 2 is a single event upset waveform diagram of a 32-level trigger chain provided by the invention;
FIG. 3 is a schematic diagram of the number of times of flip-flop chain double node fault injection for 32 stages under different charge amounts;
FIG. 4 is a schematic diagram of a circuit sensitive node provided by the present invention;
fig. 5 is a schematic structural diagram of a fault injection sensitive node extraction device provided by the invention;
fig. 6 is a schematic diagram of a result of a fault injection sensitive node extraction device according to the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
At present, the simulation of the single event effect comprises mixed simulation by combining device simulation, and the process needs to calibrate by establishing a device model aiming at a process, and is complex, long in time consumption and low in efficiency; the single event effect simulation of the circuit level can only perform fault injection of one node, and cannot truly simulate the single event effect response condition of the circuit in a space radiation environment, so that the result is easy to distort; in addition, the drains of all NMOS tubes in the circuit are usually used as sensitive nodes, and the single event effect reinforcement theory of the integrated circuit is not combined with the specific analysis of the circuit, so that the data guidance is lacking.
In order to solve the problems, the invention provides a method, a device, equipment and a medium for extracting a sensitive node of fault injection, which can simulate the single event effect response condition of a circuit in a space radiation environment with low cost and high efficiency, simulate the condition that the circuit is influenced by single event to cause multi-bit overturn, provide theoretical basis for reinforcing the single event effect of an integrated circuit from a design link and improve the irradiation resistance index of a chip. The following description is made with reference to the accompanying drawings.
Fig. 1 is a flowchart of a fault injection sensitive node extraction method provided by the invention, which includes the following steps:
step 101: acquiring circuit information and total simulation times of the microelectronic device to be tested;
the total simulation times are N times, and N is larger than 1; the circuit information comprises a circuit netlist file and a node file; based on the law of large numbers, the total simulation times are generally large numbers of about 10000 times.
Step 102: aiming at any single event effect simulation, the number of injection nodes of the simulation and the fault information to be injected are obtained;
the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number; the number of injection nodes is selected based on the number of single particles affecting the circuit in the simulated spatial radiation environment. When the total number of points is more than twenty nodes and the total number of points is at least three times of the number of injected nodes, a great amount of operation can be generated by the traversal circuit, and the time consumption is long, so that the time can be shortened and the efficiency can be improved by selecting the random injected nodes.
Step 103: and randomly selecting fault injection nodes in the node file according to the number of the injection nodes.
And the number of the injected nodes is corresponding to a plurality of fault injection nodes, and a random function can be adopted or a program can be written to perform random selection of the fault injection nodes.
Step 104: performing single event effect simulation based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
when the simulated output waveform is opposite to the level of the set simulated input setting, this indicates that a single event effect is produced. The current source to which fault information is to be injected is applied to the circuit for simulating charged particles, including the peak value of the injected transient current, the pulse width of the injected transient current, and the injection time when it is applied to the circuit, the delay time of the transient current injection. Transient currents in fault information injected by different fault injection nodes are the same, and injection time and injection delay time can be set according to requirements.
Step 105: determining one or more nodes with overturn as sensitive nodes, and recording overturn times;
step 106: and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested.
The sensitive nodes can be recorded in a marking or extracting mode, reinforcement basis can be provided for the microelectronic equipment according to the sensitive nodes and the turnover times corresponding to the sensitive nodes, and particularly, the sensitive nodes with the turnover times larger than the preset times in the sensitive nodes are determined to be the sensitive nodes needing reinforcement; and reinforcing the microelectronic device to be tested according to the position of the sensitive node to be reinforced.
Before completing N times of simulation, setting fault injection information, injecting transient currents with different charge values every other or multiple times of simulation, specifically judging whether the current simulation times are increased by preset increase times, and if the current simulation times are increased by the preset increase times, increasing the transient current peak value in the fault information to be injected by a preset charge amount; finishing the current simulation; if the current simulation times are not increased by the preset increase times, the fault information to be injected is unchanged, and the current simulation is completed. For example, when the preset number of increases is 5, the preset amount of charge is increased on the basis of the previous charge every 5 increases the number of simulations. The turnover times under different injected charge amounts can be obtained so as to observe the response of the microelectronic device under the single event effect under the condition of different charge amounts and evaluate the anti-interference capability of the microelectronic device.
The method for extracting the sensitive node of the fault injection can simulate the single event effect response condition of the circuit in the space radiation environment more truly, when the total node number in the node file is at least three times of the injection node number, the fault injection node is randomly selected in the node file according to the injection node number, and all nodes of the whole circuit do not need to be traversed through a large number law, so that the efficiency is high; and meanwhile, the anti-interference performance of the microelectronic device can be determined through the recorded sensitive nodes and the turnover times, and a basis is provided for the single event effect reinforcing nodes of the microelectronic device.
As an optional manner, the single event effect simulation is performed based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes that are flipped in the simulation process includes:
determining the injection position of the fault information to be injected in the circuit netlist file according to the fault injection node; injecting transient current into the circuit netlist file according to the fault information to be injected to obtain a simulation netlist;
adding simulation input into the simulation netlist, performing single event effect simulation to obtain a simulation output waveform, determining one or more nodes which are turned in the simulation process according to the simulation output waveform, and counting the times of turning from high level to low level in the corresponding simulation output waveform.
Specifically, a 32-level trigger chain is taken as an example for explanation, the 32-level trigger chain is formed by connecting 32 triggers in series, all nodes of the 32-level trigger chain are firstly obtained and stored in a file to form a node file, and a random function is used for selecting fault injection nodes in the node file. Setting the charge quantity and injection time of the transient current of the fault injection model, injecting delay time, modifying the netlist, and simulating the new netlist. Taking a dual node fault injection as an example, the circuit netlist of the 32-stage flip-flop chain before the fault injection is shown below,
I2(net079 net01 CDN SDN net093 VDD VSS)DFCSND1BWP12T
I1(IN net02 CDN SDN net079 net1 VDD VSS)DFCSND1BWP12T
V8(net039 0)vsource dc＝1.2type＝dc
V6(IN 0)vsource dc＝1.2type＝dc
V4(VSS 0)vsource dc＝0type＝dc
V3(VDD 0)vsource dc＝1.2type＝dc
V0(CLK 0)vsource dc＝0type＝pulse val0＝0val1＝1.2period＝500p delay＝5p/
Rise＝5p fall＝5p width＝250p
V7(CDN 0)vsource type＝pwl wave＝[0 1.2 20n 1.2 20.1n 1.2]
V1(SDN 0)vsource type＝pwl wave＝[0 0 20n 0 20.1n 1.2]
the circuit netlist comprises a list of transistor-level components, models, pins and connection relations among the components in a 32-level trigger chain.
The fault injection method comprises the following steps: generating a plurality of fault injection sentences according to the transient current peak value, the transient current pulse width, the injection time and the injection delay time, wherein the number of the fault injection sentences is the same as the number of the fault injection nodes; two fault injection sentences of the double-node fault injection are adopted, and a plurality of fault injection sentences are added to the tail end of the circuit netlist to generate a new simulation netlist, wherein the new simulation netlist is as follows: the fault injection statement comprises information such as a fault injection node, a peak value of injection transient current, a pulse width of the injection transient current, injection time, injection delay time and the like.
I2(net079 net01 CDN SDN net093 VDD VSS)DFCSND1BWP12T
I1(IN net02 CDN SDN net079 net1 VDD VSS)DFCSND1BWP12T
V8(net039 0)vsource dc＝1.2type＝dc
V6(IN 0)vsource dc＝1.2type＝dc
V4(VSS 0)vsource dc＝0type＝dc
V3(VDD 0)vsource dc＝1.2type＝dc
V0(CLK 0)vsource dc＝0type＝pulse val0＝0val1＝1.2period＝500p delay＝5p/
Rise＝5p fall＝5p width＝250p
V7(CDN 0)vsource type＝pwl wave＝[0 1.2 20n 1.2 20.1n 1.2]
V1(SDN 0)vsource type＝pwl wave＝[0 0 20n 0 20.1n 1.2]
I181(I32.net123 0)SET_MODEL Q＝100fC Inject_time＝10n
I182(I14.net100 0)SET_MODEL Q＝100fC Inject_time＝10n
Importing a newly generated simulation netlist containing the injection fault into circuit design simulation software, performing single event effect on simulation input, and extracting a simulation output waveform after simulation is finished; it is determined whether a single event upset occurs, as shown in fig. 2, that the flip-flop chain output of stage 32 has a high to low level at 310 ns.
If a flip occurs, the number of flip times is increased by one. And when the simulation is completed to the set times, outputting the turnover times. 10000 times of double-node fault injection are carried out on the 32-level trigger chain, the change result of the turnover number along with the injection charge quantity is shown in figure 3, the turnover number is also increased along with the increase of the injection charge quantity, but the turnover number is below 5000 times, which indicates that the irradiation resistance index of the 32-level trigger chain meets the requirement. In addition, after the simulation is completed, the final sensitive node is stored in the output file, and as shown in fig. 4, a point A, B, C, D, E is a sensitive node of the 32-level trigger chain. The determination of the sensitive node can provide a theoretical basis for the single event effect reinforcement of the integrated circuit and improve the irradiation resistance index of the chip.
As an optional way, the method for extracting the sensitive node of fault injection provided by the invention can be realized based on a script written in a skill language. The code adopted in the process of randomly selecting the fault injection node from the circuit node file is as follows: all nodes in the circuit are counted and extracted through a circulation statement When, the nodes are placed in an all_nodes vector, and a random statement random is used for randomly selecting nodes, such as randnode1 and randnode2, in the circuit node vector all_nodes as fault injection nodes.
The code to inject faults in the selected nodes is as follows: firstly, randomly selected fault injection NODEs, such as NODE1 and NODE2, are obtained, two NODE positions are found in a netlist, a fault input sentence is constructed by adopting a fprint function, and the fault input sentence is written into a new netlist file. The fault injection statement comprises parameter data such as injection time, injection charge quantity and the like of a fault injection model, and a new netlist is output through the outfile statement.
Using a new netlist containing fault injection sentences to perform circuit simulation, setting simulation input as high level, setting clock as 100MHz, and performing fault injection simulation process as follows: and continuously injecting fault data into the netlist according to the fault injection time until the time delay of fault injection is over, and storing the data by adopting a savedodata function if simulation is overturned in the process.
The present invention may perform division of functional modules according to the above-described method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated in one processing unit. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present invention, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.
Fig. 5 shows a schematic structural diagram of a fault injection sensitive node extraction apparatus provided by the present invention in the case of dividing each functional module by using corresponding each function. As shown in fig. 5, the apparatus may include:
a circuit information and total simulation times acquisition module 501, configured to acquire circuit information and total simulation times of a microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
the injection node and fault information to be injected acquisition module 502 is configured to acquire the number of injection nodes and fault information to be injected for any one single event effect simulation; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
a fault injection node selection module 503, configured to randomly select a fault injection node in the node file according to the number of injection nodes;
the single event effect simulation module 504 is configured to perform single event effect simulation based on the fault injection node, the fault information to be injected, and the circuit netlist file, and determine one or more nodes that are flipped during the simulation process;
a sensitive node determining module 505, configured to determine one or more nodes that are flipped as sensitive nodes, and record the number of flipping times;
and the cyclic simulation module 506 is configured to obtain all the sensitive nodes corresponding to the microelectronic device to be tested after completing N times of simulation.
Optionally, the apparatus further includes a reinforcement module, which may include:
the needed reinforcement node determining unit is used for determining the corresponding sensitive nodes with the turnover times larger than the preset times in the sensitive nodes as the sensitive nodes needing reinforcement;
and the reinforcement unit is used for reinforcing the microelectronic device to be tested according to the position of the sensitive node to be reinforced.
Optionally, the single event effect simulation module 504 may include:
an injection position determining unit, configured to determine, according to the fault injection node, a position at which the fault information to be injected is injected in the circuit netlist file;
the simulation netlist generation unit is used for injecting transient current into the circuit netlist file according to the fault information to be injected to obtain a simulation netlist; the fault information to be injected comprises a transient current peak value, a transient current pulse width, injection time and injection delay time;
the simulation unit is used for adding simulation input into the simulation netlist, performing single event effect simulation to obtain a simulation output waveform, and determining one or more nodes which are overturned in the simulation process according to the simulation output waveform.
Optionally, the simulated netlist generating unit may specifically be configured to:
generating a plurality of fault injection sentences according to the transient current peak value, the transient current pulse width, the injection time and the injection delay time; the number of the fault injection sentences is the same as the number of the fault injection nodes;
and adding a plurality of fault injection sentences to the circuit netlist file to generate a simulation netlist.
Optionally, the simulation unit may specifically be configured to:
importing the simulation netlist containing the injection faults into circuit design simulation software, adding high-level simulation input into the simulation netlist to perform single event effect simulation, and extracting simulation output waveforms after simulation is finished;
and determining one or more nodes with single event upset in the simulation process according to the simulation output waveform, and counting the times of high-level to low-level upset in the corresponding simulation output waveform.
Optionally, the device further includes a fault injection information modification module, configured to determine whether a current simulation number is increased by a preset increase number, and if the current simulation number is increased by the preset increase number, increase a transient current peak value in the fault information to be injected by a preset charge amount; finishing the current simulation;
if the current simulation times are not increased by the preset increase times, the fault information to be injected is unchanged, and the current simulation is completed.
Optionally, the method is implemented based on a script written in a skill language.
Based on the same thought, the invention also provides sensitive node extraction equipment for fault injection. As shown in fig. 6, may include:
the communication unit/communication interface is used for acquiring circuit information and total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
the processing unit/processor is used for acquiring the number of the injection nodes and the fault information to be injected of the simulation aiming at any single event effect simulation; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
performing single event effect simulation based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
determining one or more nodes with overturn as sensitive nodes, and recording overturn times;
and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested.
As shown in FIG. 6, the processor may be a general purpose central processing unit (central processing unit, CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. The communication interface may be one or more. The communication interface may use any transceiver-like device for communicating with other devices or communication networks.
As shown in fig. 6, the terminal device may further include a communication line. The communication line may include a pathway to communicate information between the aforementioned components.
Optionally, as shown in fig. 6, the terminal device may further include a memory. The memory is used for storing computer-executable instructions for executing the scheme of the invention, and the processor is used for controlling the execution. The processor is configured to execute computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the invention.
As shown in fig. 6, the memory may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), a compact disc read-only memory (compact disc read-only memory) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation. The memory may be stand alone and be coupled to the processor via a communication line. The memory may also be integrated with the processor.
Alternatively, the computer-executable instructions in the embodiments of the present invention may be referred to as application program codes, which are not particularly limited in the embodiments of the present invention.
In a specific implementation, as one embodiment, as shown in FIG. 6, the processor may include one or more CPUs, such as CPU0 and CPU1 in FIG. 6.
In a specific implementation, as an embodiment, as shown in fig. 6, the terminal device may include a plurality of processors, such as the processor in fig. 6. Each of these processors may be a single-core processor or a multi-core processor.
In one aspect, a computer storage medium is provided, in which instructions are stored, and when the instructions are executed, the method for extracting the sensitive node by fault injection is implemented.
The above description has been presented mainly in terms of interaction between the modules, and the solution provided by the embodiment of the present invention is described. It is to be understood that, in order to achieve the above-described functions, they comprise corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user equipment, or other programmable apparatus. The computer program or instructions may be stored in a computer storage medium or transmitted from one computer storage medium to another, for example, from one website site, computer, server, or data center over a wired or wireless connection. The computer storage media may be any available media that can be accessed by a computer or data storage devices such as servers, data centers, etc. that integrate one or more available media. The usable medium may be a magnetic medium, e.g., floppy disk, hard disk, tape; optical media, such as digital video discs (digital video disc, DVD); but also semiconductor media such as solid state disks (solid state drive, SSD).
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. The method for extracting the sensitive node of the fault injection is characterized by comprising the following steps of:
acquiring circuit information and total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
aiming at any single event effect simulation, the number of injection nodes of the simulation and the fault information to be injected are obtained; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
performing single event effect simulation based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
determining one or more nodes with overturn as sensitive nodes, and recording overturn times;
and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested.
2. The method for extracting the sensitive nodes by fault injection according to claim 1, wherein after the N times of simulation are completed, obtaining all the sensitive nodes corresponding to the microelectronic device to be tested further comprises:
determining the corresponding sensitive nodes with the turnover times larger than the preset times in each sensitive node as sensitive nodes needing reinforcement;
and reinforcing the microelectronic device to be tested according to the position of the sensitive node to be reinforced.
3. The method for extracting a sensitive node of fault injection according to claim 1, wherein the performing single event effect simulation based on the fault injection node, the fault information to be injected, and the circuit netlist file, determining one or more nodes that are flipped during the simulation process includes:
determining the injection position of the fault information to be injected in the circuit netlist file according to the fault injection node;
injecting transient current into the circuit netlist file according to the fault information to be injected to obtain a simulation netlist; the fault information to be injected comprises a transient current peak value, a transient current pulse width, injection time and injection delay time;
adding simulation input into the simulation netlist, performing single event effect simulation to obtain a simulation output waveform, and determining one or more nodes which are overturned in the simulation process according to the simulation output waveform.
4. The method for extracting a sensitive node of fault injection according to claim 3, wherein the injecting the transient current into the circuit netlist file according to the fault information to be injected to obtain a simulated netlist comprises:
generating a plurality of fault injection sentences according to the transient current peak value, the transient current pulse width, the injection time and the injection delay time; the number of the fault injection sentences is the same as the number of the fault injection nodes;
and adding a plurality of fault injection sentences to the circuit netlist file to generate a simulation netlist.
5. The method for extracting a sensitive node in fault injection as claimed in claim 3, wherein adding a simulation input to the simulation netlist, performing single event effect simulation, and obtaining a simulation output waveform comprises:
importing the simulation netlist containing the injection faults into circuit design simulation software, adding high-level simulation input into the simulation netlist to perform single event effect simulation, and extracting simulation output waveforms after simulation is finished;
and determining one or more nodes with single event upset in the simulation process according to the simulation output waveform, and counting the times of high-level to low-level upset in the corresponding simulation output waveform.
6. The method for extracting sensitive nodes in fault injection according to claim 3, wherein after completing N times of simulation, before obtaining all sensitive nodes corresponding to the microelectronic device to be tested, the method further comprises:
judging whether the current simulation times are increased by preset increase times, if the current simulation times are increased by the preset increase times, increasing the transient current peak value in the fault information to be injected by a preset charge amount; finishing the current simulation;
if the current simulation times are not increased by the preset increase times, the fault information to be injected is unchanged, and the current simulation is completed.
7. The method for extracting the sensitive node of the fault injection according to claim 1, wherein the method is realized based on a script written in a skill language.
8. A fault injection sensitive node extraction apparatus, comprising:
the circuit information and total simulation times acquisition module is used for acquiring the circuit information and the total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
the system comprises an injection node and a fault information acquisition module to be injected, wherein the injection node and the fault information acquisition module to be injected are used for simulating any single event effect to acquire the number of the injection nodes and the fault information to be injected of the simulation; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
the fault injection node selection module is used for randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
the single event effect simulation module is used for carrying out single event effect simulation based on the fault injection nodes, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
the sensitive node determining module is used for determining one or more nodes with overturn as sensitive nodes and recording overturn times;
and the circulation simulation module is used for obtaining all sensitive nodes corresponding to the microelectronic device to be tested after completing N times of simulation.
9. A fault injection sensitive node extraction apparatus, comprising:
the communication unit/communication interface is used for acquiring circuit information and total simulation times of the microelectronic device to be tested; the total simulation times are N times, and N is greater than 1; the circuit information comprises a circuit netlist file and a node file;
the processing unit/processor is used for acquiring the number of the injection nodes and the fault information to be injected of the simulation aiming at any single event effect simulation; the number of the injection nodes is at least two; the total node number in the node file is at least three times the injection node number;
randomly selecting fault injection nodes in the node file according to the number of the injection nodes;
performing single event effect simulation based on the fault injection node, the fault information to be injected and the circuit netlist file, and determining one or more nodes which are overturned in the simulation process;
determining one or more nodes with overturn as sensitive nodes, and recording overturn times;
and after the simulation is completed for N times, obtaining all sensitive nodes corresponding to the microelectronic device to be tested.
10. A computer storage medium having instructions stored therein which, when executed, implement the fault injection sensitive node extraction method of any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117952047A (en) * | 2024-02-28 | 2024-04-30 | 上海芯思维信息科技有限公司 | Fault checking method, device, computing equipment and computer storage medium |
| CN117952047B (en) * | 2024-02-28 | 2024-11-15 | 上海芯思维信息科技有限公司 | Fault checking method, device, computing equipment and computer storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117952047A (en) * | 2024-02-28 | 2024-04-30 | 上海芯思维信息科技有限公司 | Fault checking method, device, computing equipment and computer storage medium |
| CN117952047B (en) * | 2024-02-28 | 2024-11-15 | 上海芯思维信息科技有限公司 | Fault checking method, device, computing equipment and computer storage medium |
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