JPH10222545A - Parameterized memory circuit degenerating method and logic cell library generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parameterized memory circuit degenerating method and a logic cell library generating method which extract the characteristic value of parameterized memory in a short time and with high accuracy. SOLUTION: When a net list of leaf cells is created from layout data of parameterized memory, the parasitic resistance and parasitic capacity of a leaf cell transistor are extracted (procedure A), and the leaf cell is replaced with a degenerated equivalent circuit (procedure B). When an equivalent circuit of entire memory is created by combining the leaf cells, a part that does not affect characteristic calculation is eliminated, also, a part that affects characteristic calculation and is simplified is degenerated, a circuit simulation execution net list that includes an input vector and an analysis condition is created (procedure C), circuit simulation is carried out (procedure D), characteristic calculation is performed based on the execution result and a logic cell library is automatically created (procedure E).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of reducing a circuit of a parameterized memory and a method of generating a logic cell library which are applied to a system for extracting characteristic values of a parameterized memory required for a theoretical cell library of an LSI design.

[0002]

2. Description of the Related Art Conventionally, characteristic values such as delay time, timing constraints, and power consumption of a parameterized memory required for a theoretical cell library for LSI design have been automatically calculated by a parameterized memory characteristic extraction system. The parameterized memory is configured by repeating and connecting basic circuits (basic cells) called leaf cells. Conventionally, in a parameterized memory characteristic extraction system, for example, by adopting a method of replacing a load transistor node with a simple equivalent node capacitance,
For a transistor other than the signal path of interest, the load is simplified to perform processing. Further, the timing constraint of the memory is defined, for example, similarly to the sequential circuit, and is extracted by an analytical method in order to obtain the minimum value of the output according to the definition. That is,
If the expected value of the output is obtained by simulation, the timing is strictly re-simulated, and if the expected value of the output is not obtained, the timing is relaxed and the re-simulation is performed. The minimum value of the timing can be obtained by repeating the above processing until the convergence condition is satisfied. As described above, in the extraction of the timing constraint characteristics of the memory, an enormous amount of time is required for a large-scale circuit because the simulation is repeatedly performed to find the minimum value. Therefore, conventionally, a clock delay until a latch for taking in data is simulated, and a margin is added to a difference between these values to be used as a timing constraint value.

[0003]

By the way, in the conventional parameterized memory characteristic extraction system which employs a method of replacing a load transistor node with a simple equivalent node capacitance, a large error occurs and a highly accurate processing result cannot be obtained. There was a problem. In addition, instead of replacing the load transistor node with a simple equivalent node capacitance, a method of connecting the nodes other than the load node to V _dd and V _ss to reduce the number of nodes can be considered, but sufficient accuracy is secured. I couldn't do that.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit of a parameterized memory for extracting characteristic values of a parameterized memory required for a theoretical cell library of an LSI design in a short time and with high accuracy, and a logic cell library generation. It is to provide a method.

[0005]

A circuit degeneration method for a parameterized memory according to the present invention relates to a combinational circuit for generating a netlist of leaf cells from layout data of a parameterized memory. Is characterized in that what is the load is simplified and left, and the others are removed.

In the method for degenerating a circuit of a parameterized memory according to the present invention, for example, a circuit portion which is a direct load of a signal passing node of interest is left as it is, and a load further downstream of this circuit portion is omitted.

In the method for degenerating a circuit of a parameterized memory according to the present invention, for example, when a plurality of circuit parts of the same type exist as a load at one signal passing node, the effective W length of the transistor in the circuit part is determined. The sum is reduced to one circuit part.

A circuit degeneration method of a parameterized memory according to the present invention is an equivalent circuit comprising a transistor whose memory cells are fattened by the number of bits when generating a netlist of leaf cells from layout data of the parameterized memory. It is characterized in that it is reduced to a circuit.

A circuit degeneration method of a parameterized memory according to the present invention relates to a combinational circuit when generating a netlist of leaf cells from layout data of a parameterized memory, and loads a transistor other than a signal path of interest with a load. This is characterized in that the memory cell is simplified, the remaining memory cell is removed, and the other memory cells are removed, and the memory cell is reduced to an equivalent circuit formed by using a transistor whose number is increased by the number of bits.

In the method for degenerating a circuit of a parameterized memory according to the present invention, for example, regarding a combinational circuit, a circuit portion directly loading a signal passing node of interest is left as it is, and a load further downstream of this circuit portion is omitted. I do.

Further, in the circuit degeneration method of the parameterized memory according to the present invention, for example, a combinational circuit includes:
When a plurality of circuit parts of the same type exist as a load at one signal passing node, the effective W lengths of the transistors in the circuit parts are summed and degenerated into one circuit part.

According to the method of generating a logic cell library of a parameterized memory according to the present invention, when generating a netlist of a leaf cell from layout data of the parameterized memory, a parasitic resistance and a parasitic capacitance of a transistor of the leaf cell are extracted and a leaf cell is extracted. When creating an equivalent circuit of the entire memory having the required memory size by combining the above-described leaf cells with a degenerated equivalent circuit, a partial circuit that does not affect the characteristic calculation is removed and a part that does not affect the characteristic calculation is created. Degenerate the part that can be simplified by the circuit, generate a circuit simulation execution netlist including input vectors and analysis conditions for characteristic extraction, execute circuit simulation, and perform characteristic calculation based on the result of the above circuit simulation Automatic generation of logic cell library The features.

In the method for generating a logic cell library of a parameterized memory according to the present invention, for example, when generating a netlist of leaf cells from the layout data of the parameterized memory, a combinational circuit may include transistors other than a signal path of interest. On the other hand, it is easy to keep what is the load, remove the others,
Regarding the memory cell, the equivalent circuit is reduced to an equivalent circuit formed by using a transistor whose width is increased by the number of bits.

In the method for generating a logic cell library of a parameterized memory according to the present invention, for example, regarding a combinational circuit, a circuit portion directly loading a signal passing node of interest is left as it is, and a subsequent stage of this circuit portion is left as it is. Is omitted.

Further, in the method for generating a logic cell library of a parameterized memory according to the present invention, for example, when a plurality of circuit parts of the same type are present as a load at one signal passing node with respect to a combinational circuit, the circuit part is Thus, the effective W lengths of the transistors are summed and reduced to one circuit portion.

In the method for generating a logic cell library of a parameterized memory according to the present invention, for example, characteristics of delay time, timing constraint, and power consumption are extracted.

Further, in the method for generating a logic cell library of a parameterized memory according to the present invention, for example, power consumption is extracted using a power consumption model in consideration of the operation mode of the memory and the operation efficiency of input / output data.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a logic cell library generation system will be described below in detail with reference to the drawings.

This logic cell library generation system includes:
Precise RC extraction from leaf cells (Leaf cells), which are the basic cells of parameterized memory, performs circuit degeneration, synthesizes required memory, generates input waveforms, simulates them with a circuit simulator, measures and interprets the resulting waveforms It is an automated processing system that is consistent until data sheets and libraries are generated.

As shown in FIG. 1, the processing in the logic cell library generation system includes two steps, a circuit extraction phase EP and a simulation phase SP.

In the circuit extraction phase EP, first, in step (A), for example, 2.5-dimensional parasitic element extraction software Arcadia ^™ (Epic) is extracted from layout data of leaf cells, which are basic circuits constituting a parameterized memory.
) To extract the transistor, parasitic resistance and parasitic capacitance of the leaf cell. Then, in the procedure (B), a netlist is generated by replacing the leaf cell with a degenerated equivalent circuit as necessary. In the simulation phase SP, in step (C), a circuit simulation execution netlist including input vectors and analysis conditions is generated in accordance with a required memory size [word × bit].

In the procedure (C), when generating the netlist for executing the circuit simulation, the memory generator cuts a portion which does not affect the simulation and combines the netlist of the leaf cells.
At the same time as generating the netlist for the circuit simulator, information necessary for characteristic extraction, such as a layout size of a memory, a signal pin attribute, and an input signal condition, is also output. Further, the memory generator automatically generates an input signal file and a definition file of each signal for each type of characteristic extraction.

The output signal file is described in digital values, and the designation of a signal to be subjected to waveform analysis and the transition state of the signal are also described here. The signal definition file describes input signal conditions [pulse type, data type, signal delay time, pulse width, initial value, etc.]. Here, the pulse type defines performing a rising and falling transition during one cycle, and the data type defines performing a rising or falling transition during a cycle.

Then, an input signal is automatically generated according to the simulator used from the input signal file and the signal definition file.

In the next procedure (D), a circuit simulation is executed, for example, by using a transistor level simulator S
Calculate the characteristics using spectre ^™ (Cadence) or PowerMill ^™ (Epic). Then, the simulation result is read and waveform analysis is performed. That is, the analysis signal designation and the transition state information of the signal described in the input signal file are read, and the waveform analysis is executed according to the information. For example,
In the delay time extraction, the time between the clock and the waveform of the data output is measured. In the timing constraint, a minimum time during which data output is normally performed is searched.

Then, in the next procedure (E), the final data is automatically output in accordance with each model from the result of characteristic extraction for each size. The model for each characteristic extraction can be output in various formats such as a worst value, an average value, and a first-order approximation, and a data sheet is also automatically output. Thereby, for example, the gate level simulator Blossom
(In-house) and RTL power estimation tool WattWacher ^TM (S
Ente) and automatically create a datasheet.

FIG. 2 shows a procedure for calculating the characteristics of the logic cell library generation system using delay as an example.

In the circuit extraction phase EP in the delay amount characteristic calculation, the following procedure (1) is performed. That is, in this procedure (1), degeneration is performed according to the type of the leaf cell from the layout data of the leaf cell, which is a basic circuit constituting the parameterized memory, to generate a netlist.

In the simulation phase SP, the following procedures (2) to (7) are performed.

That is, first, in the procedure (2), a RAM / ROM is generated by combining leaf cells, a partial circuit which does not affect the calculation of the delay value is removed, and the effect of the circuit can be simplified. Then, a netlist for calculating the characteristics of the memory having the size [word × bit] specified by the memory generator is generated.

In the next step (3), a file is created that describes the type of characteristic extraction (delay, timing, power consumption, etc.) and analysis conditions (voltage, input slope, etc.).

In the next procedure (4), each of the above procedures (1),
Using the data generated in (2) and (3), a circuit simulation execution netlist including input vectors and analysis conditions is generated.

In the next step (5), a circuit simulation is executed.

Further, in the next step (6), a delay value is calculated based on the calculation result of the simulator.

Then, in the next procedure (7), a plurality of RAs
A data sheet such as a delay table and a library are generated from the M / ROM size.

Here, in this logic cell library generation system, the delay time, the timing constraint, and the power consumption are automatically calculated, and the power calculation uses the netlist without degeneration. For the delay time and the timing constraint, a reduced model for a combinational circuit or a reduced model for a memory cell is used for a load transistor. The wiring load approximates a π-type equivalent circuit for each line segment. Further, when the load transistor, the resistor, and the capacitor having the same pattern are repeated, they are combined into one.

In this logic cell library generation system, the generation of the circuit simulation execution netlist is performed according to the flowchart of FIG.

That is, when the memory size [word × bit] is specified, the memory generator creates a net list in which portions other than the path where the signal of interest flows are degenerated. The netlist degenerated by this memory generator is as follows: (1) Remove a part unrelated to signal calculation. (2) To simplify the part that simply loads the signal within a range that does not reduce the accuracy. It is created by the two-step process. In the example shown in FIG. 3, only the shortest and longest paths of the signal passing through the memory are a problem, and the other parts, that is, the parts shown with diagonal lines in FIG. 3 are removed.

Next, a detailed description will be given of a transistor degeneration model employed in the logic cell library generation system.

In this logic cell library generation system, the transistors which are the loads on the transistors other than the signal path of interest are simplified and left, and the others are removed.

Normally, for this simplification, a load model (a) based on a method of replacing the load transistor node with a simple equivalent node capacitance is adopted.
In this case, an error is large and a highly accurate processing result cannot be obtained. Also, instead of replacing the load transistor node with a simple equivalent node capacitance, a load model (b) based on a method of reducing the number of nodes by connecting nodes other than the load node to V _dd and V _ss was also examined. Sufficient accuracy could not be secured. For example, FIG.
In the example of the two-input NAND gate which is a load when the signal of the node A is checked as shown in FIG. 4A, the voltage change of the node Y as shown in FIG. Otherwise, accurate calculation cannot be performed, and the above method (a),
With the load model according to (b), a processing result with sufficient accuracy cannot be obtained.

Therefore, in this logic cell library generation system, as a degenerate model of such a combinational circuit,
The logic gate which is directly loaded on the node A is left as it is, and a load further downstream of the logic gate is omitted. Further, when a plurality of logic gates of the same type exist as a load at one signal passing node, the effective W length of each transistor of the logic gate is summed up to 1
Degenerate into two logic gates.

As shown in FIG. 5, the waveform of the NAND gate does not degenerate (Exact Waveform) and the load model (b) has 150 pSec or more near V _dd / 2, and the load model (a) In the logic cell library generation system, there is almost no difference, whereas a large difference appears at a high voltage. As shown in FIG. 6, a similar tendency is observed even in the case of a simple buffer. That is, in the load model (b), although the voltages shifted between FIG. 5 and FIG. 6 are different, the same phenomenon occurs. Looking only at this stage, the load model (b) does not seem to have a problem when V _th = V _dd / 2 or less, but the delay value of the entire signal path as a result of this signal being further input to the subsequent stage Will lose accuracy. Basically, the memory cell should follow the same principle as the combinational circuit. However, in this logic cell library generation system, when the memory cell becomes a load,
Leverage the regular structure to further simplify.

That is, as shown in a circuit diagram of one memory cell in FIG. 7A, when a certain word line WL is selected, two transistors Q ₁ and Q ₂ become loads.
The bit line BL is normally suspended at V _precharge , and regardless of whether “1” or “0” is stored in the memory itself, the two pass transistors Q ₁ and Q ₂ are connected to the node on the memory cell MC side. If one is "1", the other is always "0". Therefore, the memory cell MC is configured using transistors Q ₁ and Q _2, which are fattened by the number of bits, as in the equivalent circuit shown in FIG.

With this logic cell library generation system, a 64-word 36-bit SRAM (Static Random
As a result of analyzing the access memory), as shown in FIG. 8 showing a comparison between the circuit before the degeneration and the circuit after the degeneration, the analysis time is 2% of that before the degeneration and can be greatly reduced. A high accuracy of 0.23% was obtained.

For a large-scale SRAM of 1024 words and 72 bits, a transistor level simulator Spec
When the simulation was performed by tre ^™ (Cadence), as shown in FIG. 9, the simulation could not be executed without degeneration, but the simulation could be executed in about 10 minutes due to the degeneration.
As a degeneration step, the calculation time is reduced to about one hour just by removing the above-mentioned (1) parts unrelated to the signal calculation, and (2) the part that is merely a load on the signal is accurately calculated. Was simplified within a range not to drop, and the time was reduced to 10 minutes by combining the loads repeatedly.

FIG. 10 shows how the difference between load models affects the accuracy of delay of the entire signal path in a large-scale SRAM having 1024 words and 72 bits. In the degeneration model (c) in this logic cell library generation system, the delay value is 5.63 nSec, whereas
There was a difference of 381 pSec in the load model (a) and 115 pSec in the load model (b).

As described above, by applying the present invention to the logic cell library generation system, the calculation time can be reduced and the accuracy can be improved.

It is generally known that a delay time defined by a time difference between an input signal and an output signal depends on a load and a gradient of the input signal, and in a memory, it also depends on a value of output data. I know. In addition, since the signal path of the maximum value and the minimum value is clear from the structure of the parameterized memory, this logic cell library generation system measures the output waveform by changing the output load and the stored data for this path and measures the delay time. Is stored in a table.

In this logic cell library generation system, the timing constraint of the memory has the same definition as that of the sequential circuit as shown in FIG. 11, and the minimum value at which the expected value of the output is obtained according to this definition is shown in FIG. Extraction by a simple method. First, if the expected value of the output is obtained by simulation, the timing is strictly re-simulated. If the expected value of the output is not obtained, the timing is relaxed and the simulation is performed again. The minimum value of the timing can be obtained by repeating the above processing until the convergence condition is satisfied. As described above, in the extraction of the timing constraint characteristic of the memory, iterative simulation is performed to find the minimum value. Therefore, an enormous amount of time is required when the circuit scale is increased. The number of simulations and the simulation time can be significantly reduced,
Extraction can be performed without using a conventional analytical method.

1 port RA of 2048 words and 36 bits
For M, the result of extracting the timing constraint characteristics by this logic cell library generation system is shown in FIG. 1 together with the result of extraction by the conventional analytical method.
3 is shown. The logic cell library generation system satisfies the delay error of 100 pSec or less, and the timing constraint characteristic extraction by the conventional analytic method has a higher degree of approximation. The timing constraint characteristic extraction provides a more accurate extraction result.

In the power consumption extraction in the logic cell library generation system, the operation mode of the memory (read, wri
te, stand-by, etc.), and calculate the power consumption for each cycle specified in each vector. For example, in the case of a 1-port RAM: Read and write operations 2. Neither read nor write is performed. write only 4. It is divided into four operations of read only.

The memory generator generates such a vector that the address, data input, and data output change by 100%, no change, and a combination of only "0" and "1" for these operations. From this vector, the gate level simulator Blossom (in-house) or RTL
The power estimation tool WattWacher ^™ (Sente) calculates each coefficient of the power consumption formula used for calculation for each size.

Here, as shown in FIG. 14, the relationship between the bit width of the memory and the power consumption can be regarded as substantially linear in each operation, and as shown in FIG. 15, the relationship between the number of words and the power consumption. Can also be approximated by a piecewise linear function.
Therefore, it is not necessary to perform characteristic extraction on the memory of the maximum size.

Therefore, in this logic cell library generation system, as shown in FIG. 16, extraction is performed only for sizes having the same number of words and different data bit widths, and only for sizes having the same data bit width and different numbers of words. Do.

Based on the simulation results at these sample points, each coefficient value of the power consumption calculation formula is calculated. Each coefficient [p_base], [p_wr], [p_write], [p_read_0], [p_rea
[d_1], [p_addr], [p_din], [p_dout], and [p_mem] are expressed by linear functions of the number of words and the number of bits, and are incorporated in the logic simulator together with the power consumption calculation formula.

Here, the coefficient [p_base] indicates the minimum power consumed in one cycle when XCE = 0. The coefficient [p_wr] indicates power consumed in a cycle in which writing and reading are performed simultaneously. Coefficient [p_w
rite] indicates the power consumed in the cycle in which writing was performed with XWR == 0 && XRD == 1. Coefficient [p_read_
0] indicates the power consumed in the cycle in which the read data is all “0”. The coefficient [p_read_1] indicates the power consumed in the cycle in which the read data is all “1”. The coefficient [p_addr] indicates the power when all the word address pins have changed from the previous cycle. Coefficient [p_din
] Indicates the power when all data inputs have changed since the previous cycle. The coefficient [p_dout] indicates the power that increases when the read data has all changed from the previous cycle. Further, the coefficient [p_mem] indicates the power that increases when the content of the memory cell is rewritten during writing.

Then, the power consumption POWER is: POWER = [p_base] × (CK fall number when XCE == 0) + [p_wr] + [p_mem] × (memory cell content change probability ^* W / R number) + ([P_write] + [p_mem] × (content change probability of memory cell)) × W times + ([p_read_0] + [p_dout] × (data output change rate)) × R_0 times + ([p_read_1] + [p_dout] × (data output change rate)) × R_1 times + [p_addr] × (1 cycle word address change rate) + [p_din] × (1 cycle data input change rate)

In the logic cell library generation system that performs such processing, a memory of a size that could not be calculated conventionally can be calculated by degenerating the circuit. % Or more. 1% error due to degeneration
(100 pSec) or less.

Actually, when the characteristics of a 1024 word 4-bit 1-port RAM were extracted by this logical cell library generation system, the execution time was as shown in FIG. The execution time in this case includes all (from the creation of the vector to the simulation and the waveform analysis).

When the delay values of the SRAMs of various sizes calculated by the logic cell library generation system are compared with measured values, the results shown in FIG. 18 are obtained.
The error was up to 10%.

Further, by using the operation mode generated by the logic cell library generation system and the power consumption model which makes it possible to see the rate of change of the address and the input data, the output change can be considered in consideration of the operation mode of the memory. The power consumption can be calculated with much higher accuracy than the conventional power consumption model (Simple Model) that calculates the power consumption depending only on the number of times.

[0063]

As described above, in the circuit degeneration method of the parameterized memory according to the present invention, when a netlist of leaf cells is generated from layout data of the parameterized memory, transistors other than a signal path of interest are generated. By simplifying the remaining load and removing the remaining load, the number of elements related to the combinational circuit can be reduced with little influence on the extraction of the characteristic value of the parameterized memory.

In the circuit degeneration method for a parameterized memory according to the present invention, when a netlist of leaf cells is generated from layout data of the parameterized memory, the memory cells are formed using transistors whose thickness is increased by the number of bits. By degenerating to the equivalent circuit described above, the number of elements related to the memory cell can be reduced with little influence on the extraction of the characteristic value of the parameterized memory.

Further, in the circuit degeneration method of the parameterized memory according to the present invention, when generating a netlist of leaf cells from layout data of the parameterized memory, a combinational circuit is used for transistors other than the signal path of interest. By simplifying and keeping the load, and removing the rest, the number of elements related to the combinational circuit can be reduced with little effect on the extraction of the characteristic value of the parameterized memory. By reducing the number of elements related to the memory cell with little effect on the extraction of the characteristic value of the parameterized memory by degenerating into an equivalent circuit using transistors that are fattened by the number of Circuit degeneration of the parameterized memory can be performed.

Further, in the method for generating a logic cell library of a parameterized memory according to the present invention, the circuit of the parameterized memory is degenerated, and a circuit simulation execution netlist including an input vector for characteristic extraction and an analysis condition is generated. The circuit simulation can be executed in a short time, and the characteristic calculation can be performed with high accuracy based on the execution result of the circuit simulation, and the logic cell library can be automatically generated.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a basic processing procedure in a logic cell library generation system to which the present invention is applied.

FIG. 2 is a flowchart illustrating a procedure of calculating a characteristic by taking a delay as an example in the logic cell library generation system.

FIG. 3 is a flowchart showing a procedure of generating a circuit simulation execution netlist in the logic cell library generation system.

FIG. 4 is a two-input NAN for explaining a degenerate model of a combinational circuit in the logic cell library generation system.
It is a figure showing a D gate.

FIG. 5 is a waveform diagram of a NAND gate showing a degeneration model of a combinational circuit in the logic cell library generation system in comparison with a conventional load model.

FIG. 6 is a waveform diagram of a buffer showing a degenerate model of a combinational circuit in the logic cell library generation system in comparison with a conventional load model.

FIG. 7 is a memory cell 1 for describing a degeneration model of a memory cell in the logic cell library generation system.
FIG.

FIG. 8 shows an example of the logic cell library generation system.
FIG. 14 is a diagram illustrating a result of analyzing a 4-word 36-bit SRAM;

FIG. 9 is a diagram showing a result obtained by performing a simulation using a transistor level simulator on a 1024-word 72-bit SRAM in the logic cell library generation system.

FIG. 10 is a diagram showing how the difference between the degenerated model in the logic cell library generation system and the conventional load model affects the accuracy of the delay of the entire signal path in a 1024-word 72-bit SRAM.

FIG. 11 is a diagram showing a definition of memory timing constraints in the logic cell library generation system.

FIG. 12 is a diagram showing a method for extracting a minimum value at which an expected output value is obtained according to a definition of a timing constraint of a memory in the logic cell library generation system.

FIG. 13 is a 1-port RAM having 2048 words and 36 bits.
FIG. 11 is a diagram showing a result of extracting timing constraint characteristics by the above-described logic cell library generation system, together with an extraction result by a conventional analytical method.

FIG. 14 is a diagram showing that the relationship between the bit width and the power consumption of a memory can be regarded as substantially linear in each operation.

FIG. 15 is a diagram showing that the relationship between the number of words and power consumption can also be approximated by a piecewise linear function.

FIG. 16 is a diagram showing sample points when power consumption is extracted in the logic cell library generation system.

FIG. 17 is a diagram showing an execution time when the characteristics of a 1024 word 4-bit 1-port RAM are extracted by the logic cell library generation system.

FIG. 18 is a diagram showing a comparison between delay values of SRAMs of various sizes calculated by the logic cell library generation system and measured values.

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[Procedure amendment]

[Submission date] July 28, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Method for Degenerating Circuit of Parameterized Memory and Method for Generating Logic Cell Library

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parameterized memory circuit degeneration method and a logic cell library generation method applied to a system for extracting characteristic values of a parameterized memory required for a logic cell library of an LSI design.

[0002]

2. Description of the Related Art Conventionally, characteristic values such as a delay time, a timing constraint, and power consumption of a parameterized memory required for a logic cell library for LSI design have been automatically calculated by a parameterized memory characteristic extraction system. The parameterized memory is configured by repeating and connecting basic circuits (basic cells) called leaf cells. Conventionally, in a parameterized memory characteristic extraction system, for example, by adopting a method of replacing a load transistor node with a simple equivalent node capacitance,
For a transistor other than the signal path of interest, the load is simplified to perform processing. Further, the timing constraint of the memory is defined, for example, similarly to the sequential circuit, and is extracted by an analytical method in order to obtain the minimum value of the output according to the definition. That is,
If the expected value of the output is obtained by the simulation, the timing is strictly re-simulated, and if the expected value of the output is not obtained, the timing is relaxed and the re-simulation is performed. The minimum value of the timing can be obtained by repeating the above processing until the convergence condition is satisfied. As described above, in extracting the timing constraint characteristic of the memory, since the simulation is repeatedly performed to find the minimum value, an enormous amount of time is required when the circuit scale becomes large. Therefore, conventionally, a clock delay until a latch for taking in data is simulated, and a margin is added to a difference between these values to be used as a timing constraint value.

[0003]

By the way, in the conventional parameterized memory characteristic extraction system which employs a method of replacing a load transistor node with a simple equivalent node capacitance, a large error occurs and a highly accurate processing result cannot be obtained. There was a problem. In addition, instead of replacing the load transistor with a simple equivalent capacitance, a method of connecting the nodes other than the node of interest to V _dd and V _ss to reduce the number of nodes is conceivable, but it is necessary to secure sufficient accuracy. Could not.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parameterized memory circuit degeneration method and a logic cell library generation method for extracting characteristic values of a parameterized memory required for a logic cell library for LSI design in a short time and with high accuracy. Is to provide.

[0005]

A circuit degeneration method for a parameterized memory according to the present invention relates to a combinational circuit for generating a netlist of leaf cells from layout data of a parameterized memory. Is characterized in that what is the load is simplified and left, and the others are removed.

In the method for degenerating a circuit of a parameterized memory according to the present invention, for example, a circuit portion which is a direct load of a signal passing node of interest is left as it is, and a load further downstream of this circuit portion is omitted.

In the method for degenerating a circuit of a parameterized memory according to the present invention, for example, when a plurality of circuit parts of the same type exist as a load at one signal passing node, the effective W length of the transistor in the circuit part is determined. The sum is reduced to one circuit part.

The circuit degeneration method for a parameterized memory according to the present invention uses a transistor whose memory cell is enlarged by the number of bits to be loaded when generating a netlist of leaf cells from layout data of the parameterized memory. It is characterized in that it is reduced to a configured equivalent circuit.

A circuit degeneration method of a parameterized memory according to the present invention relates to a combinational circuit when generating a netlist of leaf cells from layout data of a parameterized memory, and loads a transistor other than a signal path of interest with a load. In this case, the memory cell is reduced to an equivalent circuit formed by using transistors which are increased in number by the number of bits to be loaded.

In the method for degenerating a circuit of a parameterized memory according to the present invention, for example, regarding a combinational circuit, a circuit portion directly loading a signal passing node of interest is left as it is, and a load further downstream of this circuit portion is omitted. I do.

Further, in the circuit degeneration method of the parameterized memory according to the present invention, for example, a combinational circuit includes:
When a plurality of circuit parts of the same type exist as a load at one signal passing node, the effective W lengths of the transistors in the circuit parts are summed and degenerated into one circuit part.

According to the method of generating a logic cell library of a parameterized memory according to the present invention, when generating a netlist of a leaf cell from layout data of the parameterized memory, a parasitic resistance and a parasitic capacitance of a transistor of the leaf cell are extracted and a leaf cell is extracted. When creating an equivalent circuit of the entire memory having the required memory size by combining the above-described leaf cells with a degenerated equivalent circuit, a partial circuit that does not affect the characteristic calculation is removed and a part that does not affect the characteristic calculation is created. Degenerate parts that can be simplified even in circuits, generate circuit simulation execution netlists including input vectors and analysis conditions for characteristic extraction, execute circuit simulation, and perform characteristic calculation based on the results of the above circuit simulation Automatic generation of logic cell library The features.

In the method for generating a logic cell library of a parameterized memory according to the present invention, for example, when generating a netlist of leaf cells from the layout data of the parameterized memory, a combinational circuit may include transistors other than a signal path of interest. On the other hand, it is easy to keep what is the load, remove the others,
Regarding the memory cell, the equivalent circuit is reduced to an equivalent circuit formed by using a transistor whose width is increased by the number of bits as loads.

In the method for generating a logic cell library of a parameterized memory according to the present invention, for example, regarding a combinational circuit, a circuit portion directly loading a signal passing node of interest is left as it is, and a subsequent stage of this circuit portion is left as it is. Is omitted.

Further, in the method for generating a logic cell library of a parameterized memory according to the present invention, for example, when a plurality of circuit parts of the same type are present as a load at one signal passing node with respect to a combinational circuit, the circuit part is Thus, the effective W lengths of the transistors are summed and reduced to one circuit portion.

In the method for generating a logic cell library of a parameterized memory according to the present invention, for example, characteristics of delay time, timing constraint, and power consumption are extracted.

Further, in the method for generating a logic cell library of a parameterized memory according to the present invention, for example, power consumption is extracted using a power consumption model in consideration of the operation mode of the memory and the operation efficiency of input / output data.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a logic cell library generation system will be described below in detail with reference to the drawings.

This logic cell library generation system includes:
Precisely extract RC from leaf cells (Leaf cells), which are the basic cells of parameterized memory, reduce the circuit, synthesize the required memory, generate input waveforms, simulate with a circuit simulator, measure and interpret the resulting waveforms It is an automated processing system that is consistent until data sheets and libraries are generated.

As shown in FIG. 1, the processing in the logic cell library generation system comprises two steps, a circuit extraction phase EP and a simulation phase SP.

In the circuit extraction phase EP, first, in step (A), for example, 2.5-dimensional parasitic element extraction software Arcadia ^™ (Epic) is extracted from layout data of leaf cells, which are basic circuits constituting a parameterized memory.
) To extract the transistor, parasitic resistance and parasitic capacitance of the leaf cell. Then, in the procedure (B), a netlist is generated by replacing the leaf cell with a degenerated equivalent circuit as necessary. In the simulation phase SP, in the procedure (C), a circuit simulation execution netlist including input vectors and analysis conditions is generated according to a required memory size [word × bit].

In the procedure (C), when generating the netlist for executing the circuit simulation, the memory generator cuts a portion which does not affect the simulation and combines the netlist of the leaf cells.
At the same time as generating the netlist for the circuit simulator, information necessary for characteristic extraction, such as a layout size of a memory, a signal pin attribute, and an input signal condition, is also output. Further, the memory generator automatically generates an input signal file and a definition file of each signal for each type of characteristic extraction.

The output signal file is described in digital values, and the designation of a signal to be subjected to waveform analysis and the transition state of the signal are also described here. The signal definition file describes input signal conditions [pulse type, data type, signal delay time, pulse width, initial value, etc.]. Here, the pulse type defines that a rising and falling transition is performed in one cycle, and the data type defines that a rising or falling transition is performed in one cycle.

Then, an input signal is automatically generated according to the simulator used from the input signal file and the signal definition file.

In the next step (D), a circuit simulation is executed, for example, a transistor level simulator S
Calculate the characteristics using spectre ^™ (Cadence) or PowerMill ^™ (Epic). Then, the simulation result is read and waveform analysis is performed. That is, the analysis signal designation and the transition state information of the signal described in the input signal file are read, and the waveform analysis is executed according to the information. For example,
In the delay time extraction, the time between the clock and the waveform of the data output is measured. In the timing constraint, a minimum time during which data output is normally performed is searched.

Then, in the next procedure (E), the final data is automatically output in accordance with each model from the result of characteristic extraction for each size. The model for each characteristic extraction can be output in various formats such as a worst value, an average value, and a first-order approximation, and a data sheet is also automatically output. As a result, for example, the gate level simulator Blossom
(In-house) and RTL power estimation tool WattWacher ^TM (S
Ente) is automatically generated.

FIG. 2 shows a procedure for calculating the characteristics of the logic cell library generation system using delay as an example.

In the circuit extraction phase EP in the delay amount characteristic calculation, the following procedure (1) is performed. That is, in this procedure (1), degeneration is performed according to the type of the leaf cell from the layout data of the leaf cell, which is a basic circuit constituting the parameterized memory, to generate a netlist.

In the simulation phase SP, the following procedures (2) to (7) are performed.

That is, first, in the procedure (2), a RAM / ROM is generated by combining leaf cells, a partial circuit that does not affect the calculation of the delay value is removed, and a part that does not affect the calculation of the delay value is reduced. Then, a netlist for calculating the characteristics of the memory having the size [word × bit] specified by the memory generator is generated.

In the next step (3), a file is created which describes the type of characteristic extraction (delay, timing, power consumption, etc.) and analysis conditions (power supply voltage, input slope, etc.).

In the next procedure (4), each of the above procedures (1),
Using the data generated in (2) and (3), a circuit simulation execution netlist including input vectors and analysis conditions is generated.

In the next step (5), a circuit simulation is executed.

Further, in the next step (6), a delay value is calculated based on the calculation result of the simulator.

Then, in the next procedure (7), a plurality of RAs
A data sheet such as a delay table and a library are generated from the M / ROM size.

Here, in this logic cell library generation system, the delay time, the timing constraint, and the power consumption are automatically calculated, and the power consumption calculation uses the netlist without degeneration. For the delay time and the timing constraint, a reduced model for a combinational circuit or a reduced model for a memory cell is used for a load transistor. The wiring load approximates a π-type equivalent circuit for each line segment. Further, when the load transistor, the resistor, and the capacitor having the same pattern are repeated, they are combined into one.

In the logic cell library generation system, the generation of the circuit simulation execution netlist is performed according to the flowchart of FIG.

That is, when the memory size [word × bit] is specified, the memory generator creates a net list in which portions other than the path where the signal of interest flows are degenerated. The netlist degenerated by this memory generator is as follows: (1) Remove a part unrelated to signal calculation. (2) To simplify the part that simply loads the signal within a range that does not reduce the accuracy. It is created by the two-step process. In the example shown in FIG. 3, only the shortest and longest paths of the signal passing through the memory are a problem, and the other parts, that is, the parts shown with diagonal lines in FIG. 3 are removed.

Next, a detailed description will be given of a transistor degeneration model employed in the logic cell library generation system.

In this logic cell library generation system, the transistors which are the loads on the transistors other than the signal path of interest are simplified and left, and the others are removed.

Normally, for this simplification, a load model (a) based on a method of replacing the load transistor node with a simple equivalent node capacitance is adopted.
In this case, an error is large and a highly accurate processing result cannot be obtained. Also, instead of replacing the load transistor with a simple equivalent capacitance, nodes other than the node of interest are connected to V
A load model (b) using a method of reducing the number of nodes by connecting to _dd and V _ss was also examined, but sufficient accuracy could not be secured. For example, in the case of a two-input NAND gate serving as a load when checking the signal of the node A as shown in FIG. 4A, the voltage of the node Y as shown in FIG. If you don't take it into account,
Accurate calculations cannot be performed, and the load models based on the methods (a) and (b) cannot provide sufficiently accurate processing results.

Therefore, in this logic cell library generation system, as a degenerate model of such a combinational circuit,
The logic gate which is directly loaded on the node A is left as it is, and a load further downstream of the logic gate is omitted. Further, when a plurality of logic gates of the same type exist as a load at one signal passing node, the effective W length of each transistor of the logic gate is summed up to 1
Degenerate into two logic gates.

As shown in FIG. 5, the waveform of the NAND gate does not degenerate (Exact Waveform) and the load model (b) has a difference of 150 pSec or more near V _dd / 2. In (a), there is a large difference at a high voltage, whereas in the degenerate model (c) in this logic cell library generation system, there is almost no difference. As shown in FIG. 6, a similar tendency is observed even in the case of a simple buffer. That is, in the load model (b), although the voltages shifted between FIG. 5 and FIG. 6 are different, the same phenomenon occurs. Looking only at this stage, the load model (b) does not seem to have a problem when V _th = V _dd / 2 or less, but the delay value of the entire signal path as a result of this signal being further input to the subsequent stage Will lose accuracy. The memory cell should basically follow the same principle as the combinational circuit, but in this logic cell library generation system, when the memory cell is a load, the regular structure is utilized to further simplify the operation.

That is, as shown in a circuit diagram of one memory cell in FIG. 7A, when a certain word line WL is selected, two transistors Q ₁ and Q ₂ become loads.
The bit line BL is normally suspended at V _precharge , and one of the nodes in the memory cell of the _two pass transistors Q ₁ and Q ₂ regardless of whether “1” or “0” is stored in the memory itself. If "1", the other is always "0"
become. Therefore, regarding the memory cell, FIG.
When a plurality of equivalent circuits are degenerated as shown in the equivalent circuit shown in FIG. 2B and the word line WL has a plurality of equivalent circuits, the transistors Q ₁ and Q ₂ are made thicker by the number of the equivalent circuits.

With this logic cell library generation system, a 64-word 36-bit SRAM (Static Random
As a result of analyzing the access memory), as shown in FIG. 8 showing a comparison between the circuit before the degeneration and the circuit after the degeneration, the analysis time is 2% of that before the degeneration and can be greatly reduced. A high accuracy of 0.23% was obtained.

For a large-scale SRAM of 1024 words and 72 bits, a transistor level simulator Spec
When a simulation was performed using tre ^™ (Cadence), as shown in FIG. 9, the simulation could not be executed without degeneration, but the simulation could be executed in about 10 minutes due to the degeneration.
As a degeneration step, the calculation time is reduced to about one hour just by removing the above-mentioned (1) parts unrelated to the signal calculation, and (2) the part that is merely a load on the signal is accurately calculated. Was simplified within a range not to drop, and the time was reduced to 10 minutes by combining the loads repeatedly.

FIG. 10 shows how the difference between load models affects the accuracy of delay of the entire signal path in a large-scale SRAM having 1024 words and 72 bits. In the degeneration model (c) in this logic cell library generation system, the delay value is 5.63 nSec, whereas
There was a difference of 381 pSec in the load model (a) and 115 pSec in the load model (b).

As described above, by applying the present invention to the logic cell library generation system, the calculation time can be reduced and the accuracy can be improved.

It is generally known that a delay time defined by a time difference between an input signal and an output signal depends on a load and a gradient of the input signal, and in a memory, it also depends on a value of output data. I know. In addition, since the signal path of the maximum value and the minimum value is clear from the structure of the parameterized memory, this logic cell library generation system measures the output waveform by changing the output load and the stored data for this path and measures the delay time. Is stored in a table.

Further, in this logic cell library generation system, the timing constraint of the memory has the same definition as that of the sequential circuit as shown in FIG. 11, and the minimum value at which the expected value of the output is obtained according to this definition is shown in FIG. It is extracted by such a method. First, if the expected value of the output is obtained by the simulation, the timing is strictly re-simulated, and if the expected value of the output is not obtained, the timing is relaxed and the re-simulation is performed. The minimum value of the timing can be obtained by repeating the above processing until the convergence condition is satisfied. As described above, in extracting the timing constraint characteristics of the memory, iterative simulation is performed to find the minimum value. Therefore, an enormous amount of time is required when the circuit scale is large. The number can be reduced, and the simulation time can be significantly reduced, whereby the extraction can be performed without using the conventional analytical method.

1 port RA of 2048 words and 36 bits
For M, the result of extracting the timing constraint characteristics by this logic cell library generation system is shown in FIG. 1 together with the result of extraction by the conventional analytical method.
3 is shown. The logic cell library generation system satisfies the delay error of 100 pSec or less, and the timing constraint characteristic extraction by the conventional analytic method has a higher degree of approximation. The timing constraint characteristic extraction provides a more accurate extraction result.

In the power consumption extraction in the logic cell library generation system, the operation mode of the memory (read, wri
te, stand-by, etc.), and calculate the power consumption for each cycle specified in each vector. For example, in the case of a 1-port RAM: Read and write operations 2. Neither read nor write is performed. write only 4. It is divided into four operations of read only.

The memory generator generates such a vector that the address, data input, and data output change by 100%, no change, and a combination of only "0" and "1" for these operations. From this vector, the gate level simulator Blossom (in-house) or RTL
The power estimation tool WattWacher ^™ (Sente) calculates each coefficient of the power consumption formula used for calculation for each size.

Here, as shown in FIG. 14, the relationship between the bit width of the memory and the power consumption can be regarded as substantially linear in each operation, and as shown in FIG. 15, the relationship between the number of words and the power consumption. Can also be approximated by a piecewise linear function.
Therefore, it is not necessary to perform characteristic extraction on the memory of the maximum size.

Therefore, in this logic cell library generation system, as shown in FIG. 16, extraction is performed only for sizes having the same number of words and different data bit widths, and only for sizes having the same data bit width and different numbers of words. Do.

Each coefficient value of the power consumption calculation formula is calculated based on the simulation results at these sample points. Each coefficient [p_base], [p_wr], [p_write], [p_read_0], [p_rea
[d_1], [p_addr], [p_din], [p_dout], and [p_mem] are expressed by linear functions of the number of words and the number of bits, and are incorporated in the logic simulator together with the power consumption calculation formula.

Here, the coefficient [p_base] indicates the minimum power consumed in one cycle when XCE = 0. The coefficient [p_wr] indicates power consumed in a cycle in which writing and reading are performed simultaneously. Coefficient [p_w
rite] indicates the power consumed in the cycle in which writing was performed with XWR == 0 && XRD == 1. Coefficient [p_read_
0] indicates the power consumed in the cycle in which the read data is all “0”. The coefficient [p_read_1] indicates the power consumed in the cycle in which the read data is all “1”. The coefficient [p_addr] indicates the power when all the word address pins have changed from the previous cycle. Coefficient [p_din
] Indicates the power when all data inputs have changed since the previous cycle. The coefficient [p_dout] indicates the power that increases when the read data has all changed from the previous cycle. Further, the coefficient [p_mem] indicates the power that increases when the content of the memory cell is rewritten during writing.

Then, the power consumption POWER is: POWER = [p_base] × (CK fall number when XCE == 0) + [p_wr] + [p_mem] × (memory cell content change probability ^* W / R number) + ([P_write] + [p_mem] × (content change probability of memory cell)) × W times + ([p_read_0] + [p_dout] × (data output change rate)) × R_0 times + ([p_read_1] + [p_dout] × (data output change rate)) × R_1 times + [p_addr] × (1 cycle word address change rate) + [p_din] × (1 cycle data input change rate)

In the logic cell library generation system that performs such processing, a memory of a size that could not be calculated conventionally can be calculated by degenerating the circuit. % Or more. 1% error due to degeneration
(100 pSec) or less.

Actually, when the characteristics of a 1024 word 4-bit 1-port RAM were extracted by this logical cell library generation system, the execution time was as shown in FIG. The execution time in this case includes all (from the creation of the vector to the simulation and the waveform analysis).

When the delay values of the SRAMs of various sizes calculated by the logic cell library generation system are compared with measured values, the results shown in FIG. 18 are obtained.
The error was up to 10%.

Further, by using the operation mode generated by the logic cell library generation system and the power consumption model which makes it possible to see the rate of change of the address and the input data, the output change can be considered in consideration of the operation mode of the memory. The power consumption can be calculated with much higher accuracy than the conventional power consumption model (Simple Model) that calculates the power consumption depending only on the number of times.

[0063]

As described above, in the circuit degeneration method of the parameterized memory according to the present invention, when a netlist of leaf cells is generated from layout data of the parameterized memory, transistors other than a signal path of interest are generated. By simplifying the remaining load and removing the remaining load, the number of elements related to the combinational circuit can be reduced with little influence on the extraction of the characteristic value of the parameterized memory.

Further, in the circuit degeneration method of the parameterized memory according to the present invention, when a net list of leaf cells is generated from layout data of the parameterized memory, a transistor whose memory cell is enlarged by the number of bits serving as a load is used. By degenerating to an equivalent circuit configured using the above, it is possible to reduce the number of elements related to a memory cell with little influence on extraction of characteristic values of a parameterized memory.

Further, in the circuit degeneration method of the parameterized memory according to the present invention, when generating a netlist of leaf cells from layout data of the parameterized memory, the combinational circuit is not used for transistors other than the signal path of interest. By simplifying and keeping the load and removing the others, the number of elements related to the combinational circuit can be reduced with little effect on the extraction of the characteristic value of the parameterized memory, and the load can be reduced. By degenerating into an equivalent circuit using transistors that are fattened by the number of bits, the number of elements related to the memory cell can be reduced with little effect on the extraction of the characteristic value of the parameterized memory. It is possible to perform circuit degeneration of parameterized memory very efficiently. Kill.

Further, in the method for generating a logic cell library of a parameterized memory according to the present invention, the circuit of the parameterized memory is degenerated, and a circuit simulation execution netlist including input vectors and analysis conditions for characteristic extraction is generated. In addition, the circuit simulation can be executed in a short time, and the characteristic calculation can be performed with high accuracy based on the execution result of the circuit simulation, and the logic cell library can be automatically generated.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a basic processing procedure in a logic cell library generation system to which the present invention is applied.

FIG. 2 is a flowchart illustrating a procedure of calculating a characteristic by taking a delay as an example in the logic cell library generation system.

FIG. 3 is a flowchart showing a procedure for generating a circuit simulation execution netlist in the logic cell library generation system.

FIG. 4 is a two-input NAN for explaining a degenerate model of a combinational circuit in the logic cell library generation system.
It is a figure showing a D gate.

FIG. 5 is a waveform diagram of a NAND gate showing a degeneration model of a combinational circuit in the logic cell library generation system in comparison with a conventional load model.

FIG. 6 is a waveform diagram of a buffer showing a degenerate model of a combinational circuit in the logic cell library generation system in comparison with a conventional load model.

FIG. 7 is a memory cell 1 for describing a degeneration model of a memory cell in the logic cell library generation system.
FIG.

FIG. 8 shows an example of the logic cell library generation system.
FIG. 14 is a diagram illustrating a result of analyzing a 4-word 36-bit SRAM;

FIG. 9 is a diagram showing a result of a simulation performed by a transistor level simulator on a 1024-word 72-bit SRAM in the logic cell library generation system.

FIG. 10 is a diagram showing how the difference between the degenerated model in the logic cell library generation system and the conventional load model affects the accuracy of the delay of the entire signal path in a 1024-word 72-bit SRAM.

FIG. 11 is a diagram showing a definition of memory timing constraints in the logic cell library generation system.

FIG. 12 is a diagram showing a method for extracting a minimum value at which an expected output value is obtained according to a definition of a timing constraint of a memory in the logic cell library generation system.

FIG. 13 is a 1-port RAM having 2048 words and 36 bits.
FIG. 11 is a diagram showing a result of extracting timing constraint characteristics by the above-described logic cell library generation system, together with an extraction result by a conventional analytical method.

FIG. 14 is a diagram showing that the relationship between the bit width and the power consumption of a memory can be regarded as substantially linear in each operation.

FIG. 15 is a diagram showing that the relationship between the number of words and power consumption can also be approximated by a piecewise linear function.

FIG. 16 is a diagram showing sample points when power consumption is extracted in the logic cell library generation system.

FIG. 17 is a diagram showing an execution time when the characteristics of a 1024 word 4-bit 1-port RAM are extracted by the logic cell library generation system.

FIG. 18 is a diagram showing a comparison between delay values of SRAMs of various sizes calculated by the logic cell library generation system and measured values.

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

FIG. 2

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Yoshihiko Kinoshita, Inventor 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Noriyuki Ishikawa 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation

Claims (13)

[Claims] When generating a netlist of leaf cells from layout data of a parameterized memory, a combinational circuit is simplified by leaving a load on transistors other than a signal path of interest. A method for degenerating a circuit of a parameterized memory, characterized in that a method other than the above is removed. 2. The circuit degeneration of a parameterized memory according to claim 1, wherein a circuit portion directly loading a signal passing node of interest is left as it is, and a load at a subsequent stage of this circuit portion is omitted. Method. 3. When a plurality of circuit portions of the same type exist as a load at one signal passing node, the effective W lengths of the transistors in the circuit portions are reduced to one circuit portion by summing. 2. The circuit reduction method of a parameterized memory according to claim 1, wherein: 4. A parameterized memory characterized in that when generating a netlist of leaf cells from layout data of a parameterized memory, the memory cell is reduced to an equivalent circuit formed by using transistors having the number of bits increased by the number of bits. Circuit degeneration method for memory. 5. A method for generating a netlist of leaf cells from layout data of a parameterized memory, in a combinational circuit, simplifies and leaves a load on transistors other than a signal path of interest. A circuit degeneracy method for a parameterized memory, characterized in that, except for the above, a memory cell is degenerated into an equivalent circuit using transistors with the number of bits increased for the memory cell. 6. A combinational circuit, wherein a circuit portion directly loading a signal passing node of interest is left as it is,
6. The method according to claim 5, wherein a load at a stage subsequent to the circuit is omitted. 7. When a plurality of circuit parts of the same type exist as a load at one signal passing node in a combinational circuit, the effective W lengths of the transistors in the circuit parts are summed to degenerate into one circuit part. 7. The method according to claim 6, further comprising the step of: 8. When generating a netlist of leaf cells from layout data of a parameterized memory, a parasitic resistance and a parasitic capacitance of a transistor of the leaf cell are extracted, the leaf cell is replaced with a degenerated equivalent circuit, and a combination of the leaf cells is required. When creating an equivalent circuit for the entire memory with a memory size of と, the partial circuit that does not affect the characteristic calculation is removed, and the part that can be simplified even in the partial circuit that affects the characteristic calculation is reduced. Generating a circuit simulation execution netlist including input vectors and analysis conditions for performing the circuit simulation, performing characteristic calculation based on the execution result of the circuit simulation, and automatically generating a logic cell library. How to create a logic cell library for metallized memory . 9. When generating a netlist of leaf cells from the layout data of the parameterized memory, a combinational circuit is simplified by leaving a load on transistors other than a signal path of interest. 9. The method according to claim 8, wherein the other components are removed, and the memory cells are reduced to an equivalent circuit configured by using transistors that are increased by the number of bits. 10. The parameterized circuit according to claim 9, wherein a circuit portion directly loading a signal passing node of interest in the combinational circuit is left as it is, and a load further downstream of the circuit portion is omitted. A method of generating a memory logic cell library. 11. When a plurality of circuit parts of the same type are present as a load at one signal passing node in a combinational circuit, the effective W lengths of the transistors in the circuit parts are summed and reduced to one circuit part. 11. The method for generating a logic cell library of a parameterized memory according to claim 10, wherein: 12. The method according to claim 8, wherein characteristics of delay time, timing constraint, and power consumption are extracted. 13. The method according to claim 12, wherein the power consumption is extracted using a power consumption model in consideration of an operation mode of the memory and an operation efficiency of input / output data.